MODELLING OF DIGITAL CIRCUITS

USING
VERILOG HDL

COURSE MATERIAL

PREPARED BY

SRIRAM SUNDAR S
ASSISTANT PROFESSOR

CONTENTS

CHAPTER

PAGE
TITLE

NO.

NO.

1.

INTRODUCTION

2.

VERILOG HDL

2.1

Introduction

2.2

Why Verilog HDL?

2.3

Syntax

2.4

Structure

2.5

Gate Level Modelling (Structural Level)

10

2.6

Dataflow Modelling

18

2.7

Behavioral Modelling

24

2.8

Switch Level Modelling

35

3.

SIMULATION & VERIFICATION OF VERILOG DESIGN BY

OF TEST BENCH CIRCUITS

37

4.

XILINX PROCEDURES TO SIMULATE A VERILOG

PROGRAM

38

5.

SCHEMATIC DESIGN

54

VERILOG HARDWARE DESCRIPTION LANGUAGE

1. INTRODUCTION
With the advent of VLSI technology and increased usage of digital circuits, designers has to design
single chips with millions of transistors. It became almost impossible to verify these circuits of
high complexity on breadboard. Hence Computer-aided techniques became critical for verification
and design of VLSI digital circuits. As designs got larger and more complex, logic simulation
assumed an important role in the design process. Designers could iron out functional bugs in the
architecture before the chip was designed further. All these factors which led to the evolution of
Computer-Aided Digital Design, intern led to the emergence of Hardware Description Languages
(HDL). Designs described in HDL are technology-independent, easy to design and debug, and
are usually more readable than schematics, particularly for large circuits.
VLSI Design Flow

2. VERILOG HDL

2.1Introduction
The two types of popular HDLs are
1. Verilog HDL
2. Very High Speed Integrated Circuit HDL (VHDL)
Verilog HDL It can be used to describe designs at four levels of abstraction
1. Behavioral or Algorithmic level (much like c code with if, case and loop statements).
2. Dataflow level (Symbols for Boolean equations).
3. Gate level (Interconnected AND, NOR etc.).
4. Switch level (The switches are MOS transistors inside gates).

2.2Why Verilog HDL ?

Easy to learn and easy to use, due to its similarity in syntax to that of the C programming
language.

Different levels of abstraction can be mixed in the same design.

Availability of Verilog HDL libraries for post-logic synthesis simulation.

Most of the synthesis tools support Verilog HDL.

2.3Syntax
Comments Verilog comments are the same as in C++.

//

/* */

for a single line comment

for a multiline comment

White Space - The white space characters are

space (\b)

tabs (\t)

newlines (\n)
These are ignored except in strings.
Constants The generic declaration for a constant in Verilog is

<size>'<base><number> : for a full description

<base><number> : this is given a default size which is machine

dependant but at least 32 bits.

<number> : this is given a default base of decimal

In this declaration size indicates the number of bits and 'radix gives the number base (d = decimal,
b = binary, o = octal, h = hex). The default radix is decimal.

16

//The number 16 base 10

4'b1010

//The binary number 1010

8'bx

//An 8-bit binary number of unknown value

12'habc

//The hex number abc = 1010 1011 1100 in binary

8'b10

//The binary number 0000 0010

Signal values - signals in Verilog have one of four values.

0 (logic 0)

1 (logic 1)

?, X, or x ( dont care or unknown)

Z or z for high impedance tri-state.

The example representations are

4'b10x0 // 4 bit binary with 2nd least significant is unknown

4'b101z // 4 bit binary with least significant is high impedance

12'dz

// 12 bit decimal high impedance number

12'd?

// 12 bit decimal high impedance 'don't-care' number

8'h4x // 8 bit number in hexidecimal representation with the 4 LSBs unknown

Numbers Negative Number

A number can be declared to be negative by putting a minus sign infront of the size.

-8'd5 // 2's compliment of 5, held in 8 bits

8'b-5 // illegal syntax

Underscore
Underscores can be put anywhere in a number, except the beginning, to improve readability.

16'b0001_1010_1000_1111

8'b_0001_1010

// illegal use of underscore

Real
Real numbers can be in either decimal or scientific format, if expressed in decimal format they
must have at least one digit either side of the decimal point.

1.8

3_2387.3398_3047

3.8e10

2.1e-9

3. // illegal

// e or E for exponent

Strings Strings are delimited by " ... ", and cannot be on multiple lines.
"hello world"; // legal string

"good
bye
world";

// illegal string

Operators

Unary operators appear on the left of their operand

clock = ~clock; // ~ is the unary bitwise negation operator, clock is the operand

c = a || b;

Binary in the middle

// || is the binary logical or, a and b are the operands

Ternary separates its three operands by two operators.

r = s ? t : u; // ?: is the ternary conditional operator, which reads r = [if s is true then t else u]
List of Operators
1.
2.
3.
4.
5.

Logical Operators
Arithmetic Operators
Bitwise Operators
Relational Operators
Equality Operators

6. Reduction Operators
7. Shift Operators
8. Conditional Operators
9. Replication Operators
10. Concatenation Operators

Logical Operators
Symbol
!
||
&&

Description
Logical negation
Logical OR
Logical AND

#Operators
One
Two
Two

The logical operators are logical and, logical or and logical not.
All logical operators evaluate to either true (1), false (0), or unknown (x).
a = 2; b = 0; c = 4'hx;
(a && b); // logical and, evaluates to 0
(a || b); // logical or, evaluates to 1
(!a); // logical not, evaluates to 0
(a || c); // evaluates to 1, unknown || 1 (=1)
(!c); // evalutes to unknown
Arithmetic Operators
Symbol
+
-

Description
Add
Substract

#Operators
Two
Two

*
/
**
%

Multiply
Divide
Power
Modulus

Two
Two
Two
Two

The binary operators are multiply, divide, add, subtract and modulus used as shown in the
examples below.
(a * b); // multiplication,
(a / b); // division, evaluate(a + b); // addition, evaluates to 15
(a - b); // subtraction, evaluates to 9
((a + 1'b1) % b); // modulus, evaluates to 1
* Note If any bit of an operand is unknown: x, then the result of any arithmetic operation is also
unknown.
Bitwise Operators
Symbol
~
&
|
^
^~ or ~^

Description
Bitwise negation
Bitwise AND
Bitwise OR
Bitwise XOR
Bitwise XNOR

#Operators
One
Two
Two
Two
Two

The bitwise operators are negation, and, or, xor and xnor. Bitwise operators perform a bit-bycorresponding-bit operation on both operands, if one operand is shorter it is bit extended to the
left with zeros. See examples below.
a = 4'b1100; b = 4'b0011; c = 4'b0101;
(~a); // bitwise negation, evaluates to 4'b0011
(a & c); // bitwise and, evaluates to 4'b0100
(a | b); // bitwise or, evaluates to 4'b1111
(b ^ c); // bitwise xor, evaluates to 4'b0110
(a ~^ c); // bitwise xnor, evaluates to 4'b0110

Equality Operators
Symbol
==
!=
===
!==

Description
Equality
Inequality
Case equality
Case inequality

#Operators
Two
Two
Two
Two

The equality operators are

logical equality,
logical inequality,
case equality
case inequality

These operators compare the operands bit-by-corresponding-bit for equality. The logical
operators will return unknown if "significant" bits are unknown or high-impedance (x or z). The
case operators look for "equality" also with respect to bits which are unknown or high impedance.
If one operand is shorter than the other, it is expanded with 0s unless the most significant bit is
unknown.
a = 4; b = 7; // these default to decimal bases
c = 4'b010; d = 4'bx10; e = 4'bx101; f = 4'bxx01;
$display(c);
// outputs 0010
$display(d);
// outputs xx10
$display(a == b); // logical equality, evaluates to 0
$display(c != d); // logical inequality, evaluates to x
$display(c != f); // logical inequality, evaluates to 1
$display(d === e); // case equality, evaluates to 0
$display(c !== d); // case inequality, evaluates to 1

Relational Operators
Symbol
>
<
>=
<=

Description
Greater than
Less than
Greater than or equal to
Less than or equal to

#Operators
Two
Two
Two
Two

The relational operators are less than, more than, less then or equal to and more than or equal to.
a=2; b=5; c=2; d=4'hx;
(a < b); // LHS less than RHS, evaluates to true, 1
(a > b); // LHS more than RHS, evaluates to false, 0
(a >= c); // more than or equal to, evaluates to true, 1
(d <= a); // less than or equal to, evaluates to unknown

Reduction Operators
Symbol
&
~&
|
~|
^
^~ or ~^

Description
Reduction AND
Reduction NAND
Reduction OR
Reduction NOR
Reduction XOR
Reduction XNOR

#Operators
One
One
One
One
One
One

The reduction operators are and, nand, or, nor, xor xnor and an alternative xnor. They take one
operand and perform a bit-by-next-bit operation, starting with the two leftmost bits, giving a 1-bit
result.
a = 4'b1111; b = 4'b0101;c = 4'b0011;
$displayb(& a); // bitwise and, (same as 1&1&1&1), evaluates to 1
$displayb(| b); // bitwise or, (same as 0|1|0|1), evaluates to 1
$displayb(^ b); // bitwise xor, (same as 0^1^0^1), evaluates to 0
Note: the bitwise xor and xnor are useful in generating parity checks.
Shift Operators
Symbol
>>
<<

Description
Right shift
Left shift

#Operators
Two
Two

$displayb(a << 2); // shift left by 1, evaluates to 4'b0100

$displayb(a >> 2); // shift right by 2, evaluates to 4'b0010

Conditional Operators
Symbol
?:

Description
Conditional

#Operators
Two

assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;

if s1 and s2 is true, out is i3
if s1 is true and s2 is false, out is i2
if s1 is false and s2 is true, out is i1
if s1 and s2 are false, out is i0
Concatenation Operators
Symbol
{}

Description
Concatenation

#Operators
> One

a = 1'b1;
b = 2'b00;
c = 6'b101001;
$display({a, b});
// produces a 3-bit number 3'b100
$display({c[5:3], a});
// produces 4-bit number 4'b1011

2.4 Structure

The Verilog structure contains the following,

Modules

Ports

Signals

Module
A module is the top-level syntactic item in a Verilog source file. Each module starts with the word
module and ends with endmodule and between the two are module declarative items.
module module_name (port_name list);
[declarations]
[assign statements] or [initial block] or [always block] or [gate instantiations]
endmodule
Ports
Ports in Verilog can be a type of the following

input - signal coming into the module

output - signal going out of the module

inout - bidirectional signal

The module ports are given in the port name list and are declared in the beginning of the module.
Here is a sample module with input and output ports.
module mymodule(a, b);
input a;
output b;

endmodule
Signal and Vectors (Bus)
A signal is represented by either a net type or a variable type in Verilog.
The two net types most often used are

wire

tri
The two variables types most often used are

reg

integer
Both the register and net data types can be any number of bits wide if declared as vectors. Vectors
can be accessed either in whole or in part, the left hand number is always the most significant
number in the vector. See below for examples of vector declarations.

Examples:
input [4:0] d, e;
// Ports d and e are each five bit busses
wire [2:0] x, y; // Two local busses of three bits each
wire w;
//w is a single net of type wire
wire[2:0] w;
//Declares w[2], w[1], w[0]
tri[7:0] bus
//An 8-bit tri state bus
integer i;
//i is a 32-bit integer used for loop control
reg r;
//r is a 1-bit register
reg[7:0] buf;
//buf is an 8-bit register
reg[3:0] r1, r2 //r1 and r2 are both 4-bit registers

2.5Gate Level Modelling (Structural Level)

Gate Primitives:

and

nor

or

xor

not

xnor

nand

buf

Gate The general form for declaring the instance of a gate in Verilog is

gate_type [gate_name] (out_port, in_port );

and myand(out, in1, in2, in3);
or (out, in1, in2, in3);

// The [gate_name] is given for our reference

or or1(out1,in1,in2), or2(out2,in2,in3);

Exercise 1:
Write Verilog code for all the logic gates in a single module.
module all_logic_gate(or_out,and_out,xor_out,not_out,nand_out,nor_out,xnor_out,x,y);
input x,y;
output or_out,and_out,xor_out,not_out,nand_out,nor_out,xnor_out;
or g1(or_out,x,y);
and g2(and_out,x,y);
xor g3(xor_out,x,y),
not g4(not_out,x);
nand g5(nand_out,x,y);
nor g6(nor_out,x,y);
xnor g7(xnor_out,x,y);
endmodule

Output:
Gate
and
or
not
nand
nor
xor
xnor

out

Exercise 2:
Design a Full adder circuit using Gate Level Modelling.

Use wire concept for representing the intermediate output of Gate primitives.
Verilog Code:

Output:
i1
0
0
0
0
1
1
1
1

INPUT
i2 c_in
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1

OUTPUT
sum
c_out

Adding Delay in Verilog Modelling:

and #(30) G1(e,A,B);
not #(10) G2(Y,C);
or #(20) G3(X,e,y);

Types of delays
There are three basic types of delay which can be used:

The time it takes to set an output high (trise); this applies to a transition which may
start from any (`0', `1', `X' or `Z') state

The time it takes to set an output low (tfall); similarly, applies to transitions which
begin in any state.

and finaly, the time it takes to cut-off a buffer (toff).

Syntax follows the below template:

gate_type #(t_rise, t_fall, t_off) gate_name (par1, par2, ...)
For example:
and #(1, 3) g1 (o1, i1, i2);
nor #(2) g2 (o2, i3, i4);
bufif #(3, 4, 6) g3 (o3, i5, i6);
not # 2

n0(not_cnt, cnt);

and #(2,3) a0(a0_out, a, not_cnt);

/* Rise=2, Fall=2, Turn-Off=2 */

/* Rise=2, Fall=3, Turn-Off=2 */

and #(2,3) a1(a1_out, b, cnt);

or #(3,2) o0(out, a0_out, a1_out);

/* Rise=3, Fall=2, Turn-Off=2 */

Exercise 3:
Design a 4x1 Multiplexer circuit using Gate Level Modelling and represent the delay for
AND gates and 20ns delay for OR gate.

Y d 0 Sel1 Sel0 d1 Sel1 Sel0 d 2 Sel1 Sel0 d 3 Sel1 Sel0

Note:
1. Instead of using wire, use unary operators
2. Single AND gate to be common for all the AND gate primitives.
module mux4to1(y, sel,d);
output y;
input [1:0]sel;
input [3:0]d;
wire [1:0]nsel;
wire [3:0]a;
not nots0(nsel[0], sel[0]);
not nots1(nsel[1], sel[1]);
and #10 and0(a[0], nsel[0], nsel[1], d[0]);
and #10 and1(a[1], sel[0], nsel[1], d[1]);
and #10 and2(a[2], nsel[0], sel[1], d[2]);
and #10 and3(a[3], sel[0], sel[1], d[3]);
or #20 or1(y, a[0], a[1], a[2], a[3]);
endmodule
Inputs
d0 = 1
d1 = 0
d2 = 1
d3 = 0

module mux_4X1_gate(d,sel,y);
input [3:0]d;
input [1:0]sel;
output y;
wire [3:0]w;
and g0(w[0],d[0],~sel[0],~sel[1]),
g1(w[1],d[1],sel[0],~sel[1]),
g2(w[2],d[2],~sel[0],sel[1]),
g3(w[3],d[3],sel[0],sel[1]);
or g4(y,w[0],w[1],w[2],w[3]);
endmodule

Select Lines
Sel0
Sel1
0
0
0
1
1
0
1
1

Output
Y

Exercise 4:
Design a 8x1 Multiplexer circuit using Gate Level Modelling and represent the delay for
AND gates and 20ns delay for OR gate.
Inputs

E0 = 0
E1 = 1
E2 = 1
E3 = 0
E4 = 1
E5 = 0
E6 = 1
E7 = 1

Verilog Coding:

Structural Level Modelling:

Select Lines

Output

A complex circuit can be constructed by combining the simple modules. Modules can be
instantiated from within other modules. When a module is instantiated, connections to the ports
of the module must be specified.
<module_name> <instance_name> (<port_list>);
Parameter Declaration:
Parameter is used to assign a constant value for a variable. Form below example,
Whenever n presents, it take the value of 4.
parameter n=4;
For example a ripple carry adder can be constructed as follows:
module ripple_ca(sum,x,y,z);
// input and output port declarations
fulladder fa1(s[0],c[0],a[0],b[0],cin);
endmodule

module fulladder (sum,carry, a,b,c)

// contents
endmodule

Exercise 5:
Design a 5 bit Ripple Carry Adder using Structural Modelling by instantiating full adders.

Note:
Use Parameter or reg concept to declare the Cin value.
Use Vector logic to declare the inputs and outputs.
Verilog Code:

Inputs:
A = 11111110
B = 10101010

2.6 Dataflow Modelling

Outputs:
Sum =
COUT

Dataflow modeling provides a powerful way to implement a design. Verilog allows a design
processes data rather than instantiation of individual gates. Dataflow modeling has become a
popular design approach as logic synthesis tools have become sophisticated.
Continuous Assignments
A continuous assignment is the most basic statement in dateflow modeling, used to drive a value
onto a net, A continuous assignment replaces gates in the description of the circuit and
describes the circuit at a higher level of abstraction. A continuous assignment statement starts
with the keyword assign
//Syntax of assign statement in the simplest form
< continuous_assign >: : = assign < drive_strength > ? < delay > ? < list_of_assignments > ;
assign out = i1 & i2 ;
Exercise 6:
Design a 4x1 Multiplexer using Dataflow model.
Note: Use the Example 3 diagram
Verilog Code:
module mux_dataflow(i0, i1, i2, i3, s1, s0, out);
input i0, i1, i2, i3;
input s1, s0;
output out;
assign out = (~s1 & ~s0 & i0) | (~s1 & s0 & i1) | (s1 & ~s0 & i2) |(s1 & s0 & i3) ;
endmodule

Inputs
d0 = 1
d1 = 0
d2 = 1
d3 = 0

Select Lines
Sel0
Sel1
0
0
0
1
1
0
1
1

Output
Y

Exercise 7:
Design a BCD to Decimal Decoder using Dataflow modelling:
X3

Verilog Code:

X2

X1

X0

Truth Table:

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

X3
0
0
0
0
0
0
0
0
1
1

X2
0
0
0
0
1
1
1
1
0
0

X1
0
0
1
1
0
0
1
1
0
0

X0
0
1
0
1
0
1
0
1
0
1

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

Concatenation Statement:
Concatenations are expressed using the brace characters { and }, with commas separating the
expressions within.
assign { c_out , sum[ 3 : 0 ] } = a [ 3 : 0 ] + b [ 3 : 0 ] + c_in ;
+ {a, b[3:0], c, 4'b1001} // if a and c are 8-bit numbers, the results has 24 bits
Unsized constant numbers are not allowed in concatenations
Exercise 8:
Use Example 2 and combine the output using Concatenation operator:
Verilog Code:

Replication Operator
Replication operator is used to replicate a group of bits n times. Say you have a 4 bit variable and
you want to replicate it 4 times to get a 16 bit variable: then we can use the replication operator.
n{m}} - Replicate value m, n times
Repetition multipliers (must be constants) can be used:
{3{a}} // this is equivalent to {a, a, a}
Nested concatenations and replication operator are possible:
{b, {3{c, d}}} // this is equivalent to {b, c, d, c, d, c, d}
Conditional Operators
The conditional operator has the following C-like format:
cond_expr ? true_expr : false_expr
The true_expr or the false_expr is evaluated and used as a result depending on what cond_expr
evaluates to (true or false).
Exercise 9:
Design a 4x1 Multiplexer using conditional operators.
Verilog Code
module mux4_to_1_cond (i0, i1, i2, i3, s1, s0, out);
input i0, i1, i2, i3;
input s1, s0;
output out;
assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;
endmodule
Inputs
d0 = 1
d1 = 0
d2 = 1
d3 = 0

Select Lines
Sel0
Sel1
0
0
0
1
1
0
1
1

Output
Y

Exercise 10:
Design a Decimal to BCD Encoder using conditional operators.

Verilog Code:

Sl.
No.

I1

I2

I3

I4

I5

I6

I7

I8

I9

2.7 Behavioral Modelling

Modelled with procedural blocks or continuous assignment statements. This statement is simply
the sequencing construct required to extend the range of behavioural statements which include
behavioural statements (such as if and always) to cover multiple behavioural statements. The
syntax is
module

//declaration of input and output ports

begin
<behav-statement> [ <behav-statement> ]
end
Registers
Despite the name, registers do not imply memory. They are simply a language construct denoting
variables that are on the left hand side of an always block (and in simulation code, initial and
forever blocks). You declare registers, like wires, at the top level of a module, but you use them
within always blocks. You cannot assign registers values at the top level of a module, and you
cannot assign wires while inside an always block.
Always Blocks
Always blocks are blocks which model behavior that occurs repeatedly based on a sensitivity list.
Whenever a signal in the sensitivity list changes values, the statements in the always block will be
run sequentially in the simulator. In terms of actual hardware, the synthesis tool will synthesize
circuits that are logically equivalent to the statements within the always block.
module bitwise_not(a_in, a_out);
input [1:0] a_in;
output [1:0] a_out;
// Declare a_out as a register, since it is used on the LHS of an always block
reg [1:0] a_out;
// better to use always @(*),which represents all the inputs declared in ports
always @(a_in) begin
a_out = ~a_in;
end
endmodule

if-then-else Behavioural Statement

The if statement enables selective execution of behavioural statements. The target behavioural
statement (which can be any type of behavioural statement, including further if statements) is
executed if the signal expression is non-zero.
if ( <signal-expr> )
<behav-statement>
[ else <behav-statement> ]

Exercise 11:
Design a D flip-flop in Behavioural Verilog modelling using if-then-else statements.

INPUT
CLK

OUTPUT
D
0
1
X

QN
X
X
X

QN+1
0
1
QN

STATE
RESET
SET
NO CHANGE

Verilog Coding:
module dff(q,qbar,d,clk,clr);
output q,qbar;
input d,clk,clr;
reg q,qbar;
always @ (negedge clr or posedge clk)
begin
if (~clr)
begin
q = 1'b0;
qbar = 1'b1;
end
else
begin
q = d;
assign qbar = ~q;
//assign statement from dataflow mod
end
end
endmodule

Exercise12:
Design a JK flip-flop in Behavioural Verilog modelling using if-then-else statements.
PREVIOUS
STATE

INPUTS

OUTPUTS

QN

Qn+1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
1
1
1
0
1
0

Note:
1. Use Negative edge clock and positive clear.
2. Use logical AND operation (&&) and Conditional equality (==).
3. For invalid inputs outputs are HIGH Impedance state (1bz).
Verilog Code:

Exercise 13:
Design a 4-bit Counter in Behavioural Verilog modelling using if-then-else statements.
module counter(clk, reset,count);
input clk, reset;
output [3:0]count;
reg [3:0] count;

Count Values:

always @(negedge clk or posedge

reset)
begin
if (reset)
count = 0;
else
count = count + 1;
end
endmodule

Exercise 14:
Design the 4-bit Ripple Counters represented given below in Structural Verilog modelling.
Instantiate JK flip from Example 7. Compare the outputs for several conditions

Conditions:
1. Negative Edge Flip-Flop & driving successive flip-flops by Real output of Flip-flop
2. Negative Edge Flip-Flop & driving successive flip-flops by Complementary output of Flipflop
3. Positive Edge Flip-Flop & driving successive flip-flops by Real output of Flip-flop
4. Positive Edge Flip-Flop & driving successive flip-flops by Complementary output of Flipflop

Verilog Code:

Output:
Count Values
Condition 1

Condition 2

Condition 3

Condition 4

Exercise 15:
Design a 4-bit UP/DOWN Counter in Behavioural Verilog modelling using if-then-else
statements.
Count
module up_down_counter(clk, rst, ud, count) ;
parameter n = 4 ;
input clk, rst, ud ;
output reg[n-1:0] count ;
always@(negedge clk or posedge rst)
begin
if (rst)
count = 4'b0;
else if (ud)
count = out + 1'b1;
else
count = count - 1'b1;
end
endmodule

ud=1

ud=0

Exercise 16:
Design a 4-bit Decade Counter in Behavioural Verilog modelling using if-then-else
statements.
Count
module decade(clk, rst, count) ;
parameter n = 4 ;
input clk, rst ;
output reg[n-1:0] count ;
always@(negedge clk or posedge rst)
begin
if (rst)
count = 4'b0;
else if (count==4'b1001)
count = 4'b0;
else
count = count + 1'b1;
end
endmodule

Blocking and Non-Blocking Statements:

Verilog supports two types of assignments inside an always block.

Blocking assignments use the = statement.

Non-blocking assignments use the <= statement.

Do not confuse either type with the assign statement, which cannot appear inside always blocks
at all.

The non -blocking assignment operator allows the two statements to execute
concurrently instead of sequentially in ALWAYS block.

The blocking assignment operator allows the two statements to execute

sequentially in ALWAYS block.

The Shift registers examples can be used to represent the Blocking and Non-Blocking
Statements
Exercise 17:
Design a Serial-In Serial-Our Shift Register using non-blocking statements. Analyse the
output, if non-blocking statements are changed into blocking statements.
module SISO(clk, sr_in,sr_out);
input clk;
input sr_in;
output sr_out;
reg [3:0]sr;
always@(negedge clk)
begin
sr[0] <= sr_in;
sr[1] <= sr[0];
sr[2] <= sr[1];
sr[3] <= sr[2];
end
assign sr_out = sr[3];
endmodule
Non Blocking:
Input: 1010
Output after Clocks :

Blocking:
Input: 1010
Output after Clocks :

CASE Statement:
The case structure has a slightly different syntax than its counterpart in C++ in that no break
statement is necessary and the word switch is not used. A typical case structure might look like
this:
case (t)
0: y = w[0];
1: y = w[1];

7: y = w[n];
default: y = x;
endcase
In this example each alternative in the case statement takes up only one line. Multiline blocks can
be used with begin and end statements.
Case -Can detect x and z! (good for testbenches)
Casez - Uses z and ? as dont care bits in case items and expression
Casex - Uses x, z, and ? as dont care bits in case items and expression
Exercise 18:
Design a 3x8 Decoder using CASE statement.
module mux (sel, res);
input [2:0] sel;
output reg [7:0] res;
always @(sel or res)
begin
case (sel)
3b000 : res = 8b00000001;
3b001 : res = 8b00000010;
3b010 : res = 8b00000100;
3b011 : res = 8b00001000;
3b100 : res = 8b00010000;
3b101 : res = 8b00100000;
3b110 : res = 8b01000000;
3b111 : res = 8b10000000;
default : res = 8bx;
endcase
end
endmodule

Input: 101
Output:

Exercise 19: Design a 8x1 Multiplexer using the CASE Statements.

Note:
Refer the Multiplexer Truth Table in Gate Level Modelling
Verilog Code:

Exercise 20: Design a 4 bit UP/DOWN Counter using the CASE Statements.
Verilog Code:
module up_down(clk, rst, set, ud,count) ;
parameter n = 4 ;
input clk, rst,set, ud;
output reg[n-1:0] count ;
always@(negedge clk or posedge rst or posedge set)
begin
case ({rst, set, ud })
//
3'b10x: count = {n{1'b0}} ;
3'b01x: count = {n{1'b1}} ;
3'b001: count = count + 1'b1 ;
3'b000: count = count - 1'b1 ;
default: count = {n{1'bz}} ;
endcase
end
endmodule

Output Sequence:
When rst=1, set=0, ud=x =>
When rst=0, set=1, ud=x =>
When rst=0, set=0, ud=1 =>
When rst=0, set=0, ud=0 =>

2.8 Switch Level Modelling

MOS Switch
Two types of MOS switches, nmos is used to model NMOS transistor, pmos is used to model
PMOS transistors.
Suppl1, supply 0, nmos and pmos are predefined functions

nmos n1(out , data , control ) ;

pmos p1(out , data , control ) ;
Exercise 22: Design a NOR Gate using Switch Level Modelling.
Verilog Coding;
module my_nor(out, A, B);
output out;
input A, B;
wire c;
supply1 pwr;
//pwr is connected to Vdd
supply0 gnd;
//gnd is connected to Vss(ground)
pmos (c, pwr, B);
pmos (out, c, A);
nmos (out, gnd, A);
nmos (out, gnd, B);
endmodule
Output:
Inputs
A

Output
out

Exercise 23: Design a NAND Gate using Switch Level Modelling.

Verilog Coding:

Output:

Inputs
A

Output
out

3 SIMULATION & VERIFICATION OF VERILOG DESIGN BY OF TEST BENCH

CIRCUITS
The Test bench circuits are used to verify the functionality without force the input every time
while simulation. This is very useful while verify a complex circuit contains large number of
inputs.
The following test bench is written for Exercise 22.
module stimulus;
reg A, B;
wire out;
my_nor n1(out, A, B);
initial
begin
A = 1'b0; B = 1'b0;
#10 A = 1'b0; B = 1'b1;
#10 A = 1'b1; B = 1'b0;
#10 A = 1'b1; B = 1'b1;
#10 A = 1'b0; B = 1'b0;
end
endmodule

4 XILINX PROCEDURES TO SIMULATE A VERILOG DESIGN

1

Double Click and Open the Xilinx ISE software

File New Project. New Project Wizard Opened.

Give the Name and Location for the project. Ensure TOP-LEVEL design as HDL. Click
Next.

Select the Device of your FPGA board and its corresponding specifications. Click Next.

Ensure all the details given and click FINISH.

In the Hierarchy window you can able to see the FPGA details.

Right Click on the FPGA create NEW SOURCE. A new source window will open.

Select VERILOG MODULE and give the file name (Module Name) and check is present
in ADD TO PROJECT. Click Next.

Assign INPUT and OUTPUT ports

10 Verify the Input and Outputs. CLICK FINISH.

11 Type the program and save it.

12 Select View as SIMULATION. Select example.v file in Hierarchy window. In process window
right click On BEHAVIORAL CHECK SYNTAX and Run the program.

13 If NO error a GREEN color Tick will present. If error is present, it will be in RED color.
Correct the ERRORs with help of report present in console window.
14 Double Click on Simulate Behavioral Model. A Waveform window is get opened. If any
unwanted port is present in the waveform , right click and DELETE.

15 Right Click on INPUT and FORCE the values. If CLOCK signal is present, use Force CLOCK

16 Change the RUN time, if you want and RUN the program

17 Change the INPUT values and re-RUN the program and verify the output with the truth table.

Simulating the Program using Test Bench circuits

18 To simulate through Test bench program, proceed from step 13. Right Click on the FPGA
device and create new source. In the New Source Wizard, select Verilog Test Fixture and give
different name. Click NEXT.

19 Select the main module and click NEXT and Click FINISH.

20 Write the Test Bench code and check syntax if any present.

21 Double Click on Simulate Behavioral model. The waveform window is opened and verify the
functionality.
22 Change View as IMPLEMENTATION in Hierarchy and RUN the SYNTHESIZE

23 Run View RTL Schematic

24 Run View Technology Schematic

25 Run Implementation

26 Double Click on Floorplan Area/IO/Logic (PlanAhead) and PlanAhead window is opened

27 Assign corresponding Input and Output PIN numbers by referring the FPGA hardware manual
provided by vendor. SAVE the file and close it.
28 Now a UCF file is added in your project. If you double click that it will ask to open in text
file and click YES.

29 You can see the PlanAhead constraints and Right Click on IMPLEMENTATION and click
RERUN ALL. This process will assign your programs input and output ports in the FPGA.

30 After synthesis is completed, Connect the FPGA with PC. Run Generate Programming
FILE. It will generate the BIT file. It can be loaded in FPGA device. No

31 To Implement in Hardware, open the JTAG software provided by Vendor. If you refresh that,
it will automatically detect the

32 Right Click on FPGA and assign the BIT file already you generated.

33 Right Click on FPGA and Program the FPGA. Click OK in after that.

34 After Program Succeeded, Vary the input pins in the FPGA Board and Analyze the Output in
LED in that board.

5 SCHEMATIC DESIGN
1

File New Project Give File name (example.sch)

Choose Top Level Design as Schematic and Click Next

Select the FPGA devices specifications and Click NEXT and FINISH

Right Click on FPGA device and Click New Source. Select the Schematic and give the
name. Click NEXT and FINISH. Schematic window is opened.

Click Design and you can see your design files

Change to Simulation Mode

The Components can be picked from ADD toolbar

Or else Components can be picked simply from the following window. Draw your
Combinational circuit

Click ADD Symbol. Choose LOGIC in the categories window for Logic gates and select the
GATE from SYMBOLS and Track it work area.

Connect the net connections using ADD WIRE and Track Input and Output ports to the work
area using I/O marker.

10 Right Click on the I/O ports and check their specifications. Left Click on the I/O Port,
RENAME the I/O Ports if needed.

11 Rename all the I/O ports and SAVE the Design and go to Design.

12 Create a Test Bench to Simulate the Circuits.(Use the same procedure earlier)
13 The Same procedure to be followed to implement in the Hardware