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Approval
Name:
Robert Sobot
Degree:
Title of Thesis:
Examining Committee:
Dr. Glenn Chapman,Khairrnan
School of Engineering Science, SFU
Dfl&kKyrzyc)d,
Senior Supervisor
School of Engineering Science, SFU
Date Approved:
Author:
(signature)
Robert Sobot
(name)
(date)
Abstract
Complexity of silicon integrated circuits (IC) in very large scale of integration (VLSI)
using binary logic is reaching a point where most of the silicon area is occupied with interconnecting lines among devices on the chip, which represents a drawback of the approach.
First implication of the high wiring complexity is increased packing complexity with
increased number of pins (in today's VLSI IC number of pins exceeds 250). Therefore,
high density layout must be used for data bus both in the silicon and on the printed circuit
board. Second implication is increased cross-talk noise which is one of the limiting factors
in design of high-speed and sophisticated ICs, especially in a low-power voltage environment and high-speed chips for arithmetic applications.
Alternate approaches for design of integrated circuits for arithmetic operations that would
use standard complementary metal-oxide-semiconductor (CMOS) technology and address
the above issues have been proposed. One possible solution for reduction of high wiring
complexity, without affecting performance of a chip, is injecting more than two levels of
signal into a single wire. This is known as multiple-valued logic (MVL), however, due to
narrow voltage margins, especially in low power designs, current mode (CM) is proposed
as a better approach to MVL design. Multiple-valued logic (MVL) has been studied extensively due to its potential advantages in chips performing arithmetic intensive operations.
Reduction in the wiring density leaves space for relaxed distance between the data lines,
therefore reducing parasitic capacitances between the lines and, finally, reducing cross talk
noise.
Research effort in this thesis is directed towards the development of functional currentmode multiple-valued logic (CMMVL) circuits, as well as such basic building blocks as
current sources, current mirrors and current comparators. In this thesis, the CMMVL
approach is used to design high-speed low-power CMMVL adders that can be used in
higher level designs such as CMMVL multipliers.
...
lll
to Ljubica
Acknowledgments
I would like to thank professor Dr. Marek Syrzycki for all the help, guidance
and support that he provided during my work on this thesis. Also, I would
like to thank the Canadian Microelectronic Corporation for providing silicon
space for my designs.
Table of Contents
Approval ............................................................................................................................
..
...
ii
...
.................................................................................................................. viii
List of Figures ................................................................................................................... ix
List of Tables
Introduction ..................................................................................... 1
1.
2.
3.
4.
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
CHAPTER 2
2.1
2.2
2.3
CHAPTER 3
3.1
3.2
3.2.3
3.3
3.4
3.5
CHAPTER 4
4.1
4.2
4.3
4.4
CHAPTER 5
5.1
Design
and Implementation of Current-Mode Multiple-Valued
. CMOS
Log~c
Adders.......................................................................... 38
5.2
5.3
5.4
CHAPTER 6
Conclusions ......................................................................................... 49
References ......................................................................................................................... 52
vii
List of Tables
Table: 1.
Table: 2.
Table: 3.
Table: 4.
..................................................................39
List of Figures
Figure: 1.1. Comparison of binary (a) and MVL logic (b) signals and signal noise margins .............................................................................................................. -7
Figure: 1.2. Noise margin definitions for n-level CMMVL logic ................................... 8
Figure: 2.1.
Figure: 2.2.
Figure: 2.3.
Figure: 2.4.
Figure: 3.1.
Super NMOS transistor (a) and its schematic symbol (b) ......................... 18
Figure: 3.2.
Figure: 3.3.
Figure: 3.4.
Figure: 3.5.
Open-loop current comparator with voltage output (a) and current output
(b) ............................................................................................................... 22
............................................................... 22
Figure: 3.6.
Figure: 3.7.
Figure: 4.1.
Figure: 4.2.
Figure: 4.3.
Figure: 4.4.
Figure: 4.5.
Figure: 4.6.
Photomicrograph of the HSCM cell (215pm x 73pm) (a); and STCM cell
layout (75pm x 95pm) (b) ........................................................................ -32
Figure: 4.9.
Figure: 5.2.
One stage of the PDA: current mirror. current comparator and VCCS .....40
Figure: 5.3.
40
Schematic diagram of the PDA cell [6] .....................................................
Figure: 5.4.
Figure: 5.5.
Figure: 5.6.
Delay time for rising edge (td. ) and falling edge (tdf) of the PDA cell .....42
Figure: 5.7.
Figure: 5.8.
Figure: 5.9.
43
Introduction
Binary logic, based on switching between two voltage levels, V(0) and V(l), is
certainly the dominant technique of signal coding today. However, for a digital system to
interact effectively with inherently analogue world, analogue signal processing and data
conversion circuits are still required. Most often complex systems consist of a digital signal environment and a layer of analogue interface circuits [I]. As a result mixed-mode
IC's are common approach today in applications where both digital and analog signal processing is required. Basically, analog part of the chip has to be technologically compatible
to the digital part.
High level of sophistication does not come without a price in increased complexity
and its related problems. Today's ICs are at the point where devices on the chips are so
small and so fast that time delay in interconnection lines is an order of magnitude higher
than the internal device time delay. Moreover, with increased density of chips, the number
of inter-chip connections is greatly increased as more and more functions are put on the
same chip [2]. Secondly the high number of external pins per chip package represents
technical challenge of its own for both circuit and the packaging designers.
Furthermore, the requirement for low-power dissipation in a single chip has been
rapidly increased in the present deep submicron ULSI technology. Low power dissipation
can be achieved by reducing the supply voltage, signal capacitance, and the number of
active devices to perform a given function. Therefore, it is very important to explore techniques that will meet requirements of future high speed, low powered ULSI integrated
chips and beyond, and to develop new circuit designs using lower device count per function and lower wiring complexity.
lower number of data wires leads to lower number of pins required for the data bus.
reduced number of wires allows the space between any two wires in the data bus to be
larger without paying penalties in silicon area, leading to smaller fringe capacitance
and reduced cross-talk.
power consumption is proportional to the clock frequency, proportional to load capacitance and proportional to the square power of the supply voltage. Obviously, reduction
of the voltage is the first choice for reducing power consumption, leading into reduced
dynamic range of the voltage-mode data signal. However, dynamic range of current
mode signals is several order of magnitude higher than the voltage ones, allowing
application of MVL.
basic current-mode circuits are, in general, slower than equivalent voltage mode ones.
However, using algorithms that take advantage of multiple-valued logic it is possible to
design fully current-mode arithmetic circuits that perform arithmetic operation with the
same (or higher) speed as equivalent voltage-mode circuits.
Parallel multiplier presented in [6] is based on the redundant number representation using positive digits (called redundant positive-digit number presentation, or simply
PD number representation). The proposed 12x12 bit parallel multiplier is constructed in
5pm CMOS technology powered by 5V. Seven current levels were used and the unit current step was 50pA with typical worst-case delay time in order of 100ns. The PD algorithm allows simpler circuit implementation because only positive current signals are used
for the coding.
Parallel multiplier presented in [7] is 32x32 bit parallel multiplier fabricated in
2pm CMOS technology including depletion-mode PMOS. Its operation is based on radix4 signed-digit (SD) number system that requires seven levels of current signals: three positive values, three negative values and zero with the unit current of 31pA. Typical delay
time is 59ns which was very close to the fastest binary multiplier of that time. Furthermore, space occupied by the CMMVL multiplier is only 52% of space occupied by equivalent binary-mode multiplier.
Parallel multiplier presented in [27] is 54x54 bit pipelined multiplier fabricated in
0.8pm CMOS technology powered by 1.5V. Algorithm used is radix-2 SD number presentation that uses three levels of the input signal with the unit current step of 20pA. Its clock
frequency is 200MHz (4.6ns delay time) resulting in 1.4 times higher speed for the same
power consumption in comparison to corresponding binary multiplier.
As it can be seen from the above brief presentation of state of the art CMMVL circuits first natural application is in such arithmetic circuit as adders and multipliers and circuits that use multipliers for their operation [8][9]. Two major issues in efficient design of
CMMVL adders and multipliers are the numerical representation of the numbers and the
unit current step per logic level. Choice of the numerical representation is based on
required speed and robustness of the algorithm, trading for complexity of the circuit
implementation. Two of the numerical representation will be discussed in Chapter 1 in
more detail. A unit current step per logic level is usually chosen as a trade-off between the
resolution of a current comparator and the repeatability of current mirrors. In designs published so far the unit step current was chosen in range of 20pA to 200pA depending upon
used technology, application and the circuit configuration [4] [7]. Obvious challenge is to
investigate how far we can go into the low-unit-step current by using today's technology.
We will investigate this issue by aiming at the current range bellow 20pA.
Using the CMMVL approach to realize MVL arithmetic ICs simplifies adding and
subtracting operations on the chip, because these operations can be performed simply by
interconnecting current sources and mirrors [9]. Thus, the CMMVL circuits will use current-mode (CM) building blocks such as current sources, mirrors and comparators to perform most of arithmetic operations. Since standards for the CMMV circuitry have not yet
been established, it is important to investigate various combinations of signal levels and
circuit architectures, as well as to optimize them for the best possible yield.
present the results and conclusions regarding technology constraints for the design, as
well as potential advantages and disadvantages of the CMMVL approach.
CHAPTER 1
Similar to definitions of binary logic signals used to perform complex mathematical operations in Boolean algebra and corresponding algorithms, "n" levels of current signal, corresponding noise margins, and arithmetic algorithms have to be defined in order to
perform arithmetic operations in n-valued current-mode multiple-valued logic (CMMVL).
This chapter provides definition of MVL signals, introduces definitions of MVL signal
noise margins, and next discusses redundant positive-digit (PD) number representation,
decimal number presentation, and basic mathematical functions required for implementation of CMMVL adders. The two algorithms will be used in this thesis as the engine to
demonstrate proposed CMMVL approach by developing and building two CMMVL
adders that would use them.
Figure 1.1. Comparison of binary (a) and MVL logic (b) signals and signal noise margins
where I, is inside current range NM, set by its low margin NML, and its high margin
NMH,:
I,
(NMH, - NML,) .
(2)
Unit current step ISOdefined as a difference between any two subsequent levels of current
signal
Iso = ( I x - I x - l ) ; ( x ~ { I , ..., n - I } ) :
(3)
therefore, every level of the signal is integer multiple of the unit signal step Is0. Accordingly, every level has its own noise-margin NM, where
{ 1, ..., n
- 1} (see
Fig. 1.1.b).
Here, we introduce definitions of noise margins NML and NMH similar to the ones used in
the binary logic [ll]. The transfer characteristics IOU,vs. Ii, of the current-mode binary
circuit is shown in Fig. 1.2. The slope of the transfer characteristic equals -1 at the two
unity current gain points. Nominal logic levels IOL and
ated by the stage. Now, we can define the high and low noise margins as:
- IIH.
NML = IIL- IoLand NMH = IOH
but
IIL
Figure 12. Noise margin definitions for n-level CMMVL logic
IIH
Iin
In binary logic the noise margins are defined for only two levels of signal. Here, it should
be noted that in MVL logic noise margins are different for each level of the same signal. It
makes sense to use the worst case among all noise margins for all the levels as the ones to
characterize CMMVL circuit. In this thesis we will refer to the worst case among all the
margins as the ones relevant for cell characterization.
length. Therefore, CMMVL circuits have a potential to execute operations of addition and
multiplication of long words equally fast as voltage-mode circuits using standard binary
adding and multiplication algorithms, in spite of fact that basic current-mode circuits may
require more time than voltage-mode ones to perform a single bit operations.
..., n - 1)
Xi
+ yi
Step 2: Generates the intermediate sum wi and the carry digits ci('), c ~from
( ~r-.
1- ~
Step 3: Adds up linearly w iand the carry digits of (i - 1) and (i - 2)th position on the right:
algebraic value X = 59
Augend Y:
0
1
1
1
0
1
3
6
2
4
2
5
algebraic value X = 34
Carry (c/'3
Carry (c/~>
Final sum (si)
where Si = (0, 1,..., 9) is partial sum, and C , is carry-over value. CMMVL implementation
of this algorithm requires ten levels of current signal to represent all the digits. However,
adding block where execution of Eq. 7 takes place has to have resolution of 20 levels of
current signal, because Si E (0, 1, ..., 19) .
'
function:
Iou,~
=
O ( F ( X i ) = 0 ; (i= 1, ..., n ) )
(F (xi)
= 1;(i= 1, ..., n) ) ; here the output cur-
rent value I,,, can be either zero or some positive value "IO" depending upon outcome
of some logical function F(Xi) (i = 1,..., n), where "Xi" can be either voltage or current
variable.
Each of the above functions will be realized by designing appropriate building block and
after that the blocks will be used for synthesis of higher level functional blocks that will be
required by the intended MVL algorithm.
CHAPTER 2
memory
multiplier
F
Ir---
4
adder
chip level
functional blocks
SDDA
I
Sn
I
Sn-1
...
s2
I
s1
I
I
so
through array of nine n-type current mirrors. This simple operation results in reducing
sizes of transistors required to set the mirrors output currents. The array of n-type current
mirrors generates identical current at all the outputs, Iref = h;,+ 0.510, to the array of
closed-loop current comparators (CC). From the other side p-type array generates 10 current levels for comparison with the IreF The array of CC compares each level miISOwith
Ire, in parallel and generates voltage outputs Vi from each CC. The CC's execute the comparison operation synchronized with the clock pulses at node "clk". Outputs from the
array of DCC would go to decoder block where decoding would be performed depending
of what numerical representation is used and what adding algorithm is implemented. This
circuit will be built without the decoding part for the purpose of performance evaluation
and comparison with adders presented in Sec. 2.1 and Sec. 2.3.
>
array of 10
ptype CM mi IS
T)
ldata
dk
n-type CM
DECODER
CHAPTER 3
In this chapter we will discuss practical realization of arithmetic functions introduced in Sec. 1.5. They will be materialized here in a form of basic building blocks in
CMOS technology. CMOS current mirrors (CM) will serve as the linear function generator; CMOS current comparators (CC) will serve as the step function generator; current
sources (CS) will be materialized in form of either single NMOSPMOS transistors or in
form of current mirrors and will generate the constant function; and voltage-switched current source (VSCS) will be used as the general step function generator. Ln some of the proposed configurations the ordinary CMOS transistors will be replaced by Super MOS
transistors [13] for an improvement in low-current operations.
Fig. 3.1, while p-type Super MOS transistor is complementary structure. Transistors MI
and M2 are the main transistor and its cascode transistor respectively. The circuits mimics
DC transfer characteristic of a single n-MOS transistor of the same size as the MI, except
that operational gate voltage VGS for this circuit is considerably lower and, of course, the
output resistance is order of magnitude higher. The two features make this "device" very
promising candidate for low-power low-current applications.
b)
Figure 3.1. Super NMOS transistor (a) and its schematic symbol (b)
the signal mirror ratio M=IO&IIN; should depend of the magnitude of the currents,
over many decades of the input current, as little as possible;
Figure 3.2. Simple current mirror (a) and cascoded current mirror (b)
input current lineOutside of that limit the output current IOutbegins to differ from the input
current Ii, significantly.
1
-
1
--
'out
Figure 3.4. Current mirror with the Super MOS transistors (STCM)
Figure 3.5. Open-loop current comparator with voltage output (a) and current output (b)
transistor M3 is turning "on" and "off' transistor M3, which serves as a switch between the
current source M2 and the output terminal.
This type of a current comparator is very popular due to its simplicity and little
space it occupies [16]. Nevertheless, transient response time of these current comparators
can be long especially when Ii, is very close to Iref.
clock signal pulses. While the clock is at its high level, the switches M5-M6 are closed and
potentials at both nodes N1 and N2 are equalized to V D d 2 regardless of relation between
Ii, and IEf. When the clock changes its state to low level and opens the switch Ms and M6,
there is potential difference (caused by currents Ii, and IRf) between the nodes N1 and N2
that will be amplified by the feedback loop. Two possible outcomes can result from that
action: a) if Iin<Iref the output voltage Voutl will oscillate between GND and V D d 2 ; and
b) if Ih>IEf, the output voltage Voutl will oscillate between VDD and V D d 2 . VOut1 and
T
voltage
control
switch
block
and p-MOS transistors depending of the function F(X), Fig. 3.6. The current
b will reach
the output terminal only when the logic function turns "on" the switch logic block. The
entire building block is called voltage switched current source (VSCS).
CHAPTER 4
the two will have big influence on the overall circuit performance. Basic idea was to make
this circuit as a modular block for wide range of sizes of the two transistors. We decided to
use the minimum channel length of 1.5pm for all transistors, make it constant, and to
make the width of the M1 and the M2 variable, Fig. 3.1. Furthermore, we will use the same
two-stage amplifier for all sizes of the M1 and the M2. We found fiom simulation that ratio
of 5 to 1 for the M2 width versus the M1 width is good enough ratio above which the output resistance does not change significantly. Using higher ratio would only result in bigger
sizes of the cascoded transistors without significant improvement in the output resistance.
By doing the above steps we have designed parameterized modular block that has
only one parameter in its description: width of the M1 transistor. Therefore, width of the
M1 transistor is variable, the length of M1 is 1.5pm, width of the M2 will be always 5
times width of the M1, the length of M2 will be as well 5 times longer then the length of
M1 e.g. 7.5pm, and lengths of the rest of the transistors will be 1.5pm. Diagram in Fig. 4.1
shows simulated DC transfer curves for Super NMOS transistors in range of 25pm to
lOOpm as well as the curves for a single NMOS transistor of the same size.
VGS = 0.9V
VGS = 3 V
Vds [VI
LEGEND:
.............
NMOS
Super NMOS
Figure 4.1. DC characteristicsof Super NMOS transistor and a single NMOS transistor
It can be seen that the single NMOS transistor, at VGS=0.9V, exhibits an Early
voltage of less than 5V whereas the Super MOS has an Early voltage which is several
orders of magnitude higher. At VGS'3V
around 10V, while the Super NMOS transistor is again several orders of magnitudes
higher. Note that the "device" is already saturated at voltage only slightly above the saturation voltage of one single NMOS transistor indicating a large possible output swing.
Another important characteristic that should be compared is transient response of
the two devices. Fig. 4.2 shows transient response of the two devices under the same test
conditions: VDD = 5V, W = 5pm, L = 1.5pm excited by the same pulse (Vh=5V, t, = Ins,
tf = Ins, pulse width is 20011s). Note that delay time of the Super MOS transistor is considerably longer in comparison to a single transistor. Here, it can be seen that the delay time
is in order of 5011s for the Super MOS transistor vs. a few ns for a single transistor. So the
improvement in high output resistance is compromised by degraded high frequency performance.
I
-25
0
LEGEND:
Both NMOS and PMOS versions of Super MOS transistor were designed and
saved as modular blocks that can accommodate transistors in wide range of sizes, Fig. 4.3.
In Fig. 4.4 testing result of the actual circuit are presented. It can be seen that the
circuits indeed exhibit very high output resistance. Furthermore, the simulation results are
more accurate for low VGSvoltages which is one of the side effects of the design. The best
operational results of the circuit can be expected for VGS in range of 0.9V to 1.2V. From
the above experiment we can conclude that Super MOS transistor is feasible and can be
LEGEND:
.........................................................
test
vGs=2.3v
Oo
2
Vd,
Figure 4.4.
- - - - . simulation
used as a basic building block in higher level designs. However, we should keep in mind
that cost for improved output resistance of the block is in lower operating speeds of the
circuits and, in some cases, increased space requirements.
butvs.
.....STCM
-CCM
HSCM
-SCM
swept from OV to 5V and Iin is 10pA; accuracy IOutvs. Iin over range for the Iin from
lOnA to 100pA; and transient response of all the circuits to a current pulse of 200ns
length, with rise and fall time of Ins and amplitude of 10pA.
Sensitivity: In order to determine working range for proposed current mirror configurations the circuits were tested under the same conditions. The output load was ideal
voltage source holding potential of the output node at 2.5V. This value was chosen as
acceptable output node potential for all involved current mirrors, because diagram in Fig.
40
30
-0
20
10
2
X
-20
-30
-40
-50
1 e-02
le-01
1 e+00
1 e+01
1 e+02
1 e+03
4.5 shows that above 2V all the circuits are already saturated and they generate proper
copy of the input current.
By comparing the sensitivity of the mirrors (Fig. 4.6) one can see that the current
mirror built by using Super MOS transistors features superior accuracy over the entire
range from lOnA to 401A of the input current. It is interesting to note that cascoded configuration shows identical results in the range up to 301A, and with its smaller complexity
and much better high-frequency performance it will be a potential candidate for high
speed applications.
Transient response: As it was mentioned earlier, the circuits were excited with
the input current pulse and the response was observed at the output load resistor. Value of
the resistor is not critical therefore value of 1KR was used. Ideal current pulse source of
lO1A was chosen as, again, acceptable low current value for all the circuits.As we
expected STCM has the worst transient response, since it is the most complicated structure, among the four, Fig. 4.7. It's delay time at rising edge is in order of 200ns, which is
much worse in comparison to approximately 30ns delay time of the others. At the falling
edge all the circuits have similar response.
15
LEGEND:
I
I
I
I
10 -
I
I
I
..
.,..,*.., STCM
.................. HSCM
'
.
.
A
5
= 5 -
,,.,/
/'
2
0
.j: - ,,
L
-5o
3 :
100
time [ns]
*.,A.
..... .
CCM
SCM
input pulse
/ /"
A
..
200
300
Figure 48. Photomicrograph of the HSCM cell ( 2 1 5 x~73pm) (a);and STCM cell layout (75pm x
95pm)(b)
Testing results of HSCM,Fig. 4.9, show relatively wide distribution of the output
current characteristics for sample of 53 cells originally designed for but= 10pA set by
internal transistor. As it can be seen from the diagram that most of the output current error
is as high as 30% and possibly results from poor transistor matching in manufacturing process. Obviously, external current source should have been used to provide tuning capability for this current mirror (resistor would have done fine) as well as some of transistor
matching techniques.
LEGEND:
The STCM sensitivity was compared with the simulated characteristics, Fig. 4.10.
It should be noted that accuracy of the models for this technology is obviously not sufficient for low-current simulations. Mismatch between simulated and measured results is
obvious in range below 1pA. However, accuracy of the STCM in range of input currents
of up to 200pA is better than 5% which proves the statement made before that this type of
current mirror is suitable for high-accuracy low-current applications.
Input Current
Figure 4.10.
w]
a)
- voltage response
b)
time [ns]
Figure 4.11. DC transfer curve (a) and transient response (b) of the open-loop current comparators
Transient response curves of the open-loop current comparators are shown in Fig.
4.1 1b. The comparators were excited by a current pulse Ii, = 20pA with rise and fall time
of 1ns and length of 150ns. As they have similar configurations and the complexity, delay
times are in range of 1511s to 30ns for both of them.
input signal
,.*,.
200
Figure 4.12.
time [ns]
300
lin=19.75pA
half-cycle. That time determines delay time of the output signal. However, resolution of
200nA has been reported for this type of a current comparator in 1201. The layout of produced circuit is shown in Fig. 4.13.
Testing results of this circuit are presented in Fig. 4.14. The diagram shows a
quasi- transient output from the circuit. Operation of this type of the circuit is based on the
clocking signal, therefore real transient analysis is possible only by using an oscilloscope.
In order to present the transition of the output voltage which shows exact moment of
crossing the reference current the following method was applied. External clock generator
delivering 5Hz positive square pulses from OV to 5V was used. HP Semiconductor Parametric Analyzer was used to: generate VDD=5V, to generate 1,f-150pA,
to generate a
1001-step sweep DC current ranging from Ii,=lOOpA to 300pA, and to measure the output voltage VOut.The slow clock rate was well synchronized with the sweeping rate delivering diagram in Fig. 4.14. However, fast clocking measurements of more than 5OOKHz
were observed using oscilloscope. Estimated resolution of this circuit is better than lOpA
~ ~ 0 ~ 1 ~ 0 ~ 1 ~ 0 ~ 1
160~ 0
170' 180
1 ~ 190
0 ~ 200
1 ~ 0
Input Current [pA]
Figure 4.14.
CHAPTER 5
Figure 5.1.
Pin
Zi
Function
- input
Signal description
input signal is current that represents sum of two augends and
can have discrete values equal to multiplies of the unit current
step miISOwhere m iE (0, 1,2,3,4: 5,6} .The input current
levels are: 0, l l p A , 22pA, 33pA, 44pA, 55pA, 66pA.
Si
- output sum
ci(')
b.However,
by doing so multiple output current mirrors that generate the current values would end up
with very long transistors. One possible approach to this problem is to do a simple adding
operation at the input stage and use half values of the current levels and, therefore, use half
-I-
Figure 5.2.
-L
I ' - , ~= 2
One stage of the PDA: current mirror, current comparator and VCCS
size transistors. The input stage of current mirror (MI, M2, M,) consists of two identical
transistors M1 and M2 effectively dividing the sum of zi and b/2 by two. That value is
being copied through M, and compared with IrefiNOW,the reference currents, IRf, are set
to: 0.5, 1. 1.5, 2, 2.5, and 3 times IOresulting in much smaller transistors.
Complete schematic diagram of the cell is shown in Fig. 5.3. Full implementation
the single VSCS stages is now obvious.
Figure 53.
Table 2.
.n 1
,LEGEND:
measured
15 r
......... simulated
. A , % ,
5
I
9b- 10 (j0 /
"0
~
10
10
I
I
, ,
20
30
40
50
60
70
20
30
40
50
60
70
lin [PA]
Figure 5.4.
Batch of 27 PDA cells was manufactured and tested. All the falling edges are overlapped with the rising edges and spread of the DC characteristics is shown in Fig. 5.5.
Here I, denotes the measured current at the rising or falling edge for Iou,=5.5pA. It can be
seen that the distribution of the results is within +2pA which can be viewed as a sufficient
noise margin for the unit current step IS0 = 11pA.
1,- 3
1,- 2
I,- 1
1x
I,+ 1
I,+ 2
I,+ 3
Iin MA1
Figure 5.5.
Simulated delay diagram time for rising edge td, and falling edge tdf is shown in
Fig. 5.6 for the input current in range of lOpA to 70pA. The outputs have different delay
times due to different complexity of VSCS at the outputs. The worst case delay time is
close to 80ns.
LEGEND:
-td,
...........tdf
Figure 5.6.
Delay time for rising edge (td,) and falling edge (tdf) of the PDA cell
Photomicrograph of the cell is shown in Fig. 5.7. Size of the cell is 1XOp.m x
75pm. Dynamic power consumption of the cell is 775p.W, while DC power consumption
Figure 5.7.
Figure 5.8.
Pin description of the SDDA cell is shown in Table 3. Standard decimal numerical
presentation and adding algorithm described in Sec. 1.4 was implemented.
TABLE 3. Pin description of the SDDA cell
Pin
zi
Function
-
input
Signal description
input signal is current that represents sum of two augends and
can have discrete v a h e s equal to multiplies of the unit current
step ISO=lpA where ziE {OpA, lpA, 2pA,
..., 19pA)
Si
- output sum
CO~
- carry-over
signal
Transfer function of the block is presented in the Table 4. Here, each number from
zero to nineteen is represented by current levels at both the sum pin and the carry-over
pins. For example number 15 (represented by current level of 15pA at the input pin zi) is
decoded as l p A current at the carry-over pin and 5pA current at the sum pin. Number 4 is
decoded as OpA current at the carry-over pin and 4pA current at the sum pin.
TABLE 4. Logical table for single-digit decimal adder (SDDA)
1CrA
i switch
Figure 5.9.
current Ii, and generate two identical replicas of the current. One copy goes into the output
current mirror CMp (2) while the second copy goes into the open-loop current comparator
(CC), where it is compared against the 9.5pA reference current set by CM, (3). If Iin is
smaller than 9.5pA, the switch stays open, resulting in the output signals S = Iin and C,=O.
When the input current Iin> 9.5pA, the current comparator turns the switch on, effectively
connecting the 1pA current source STp (4) to the C, output and the lOpA current source
to the common node, producing the output signals C, = 1pA and S = Iin - 10pA.
I, [PA]
Figure 5.10. DC transfer characteristics of the one digit adder
Layout of the SDDA cells is shown in Fig. 5.1 1. It can be seen in upper right corner of the SDDA cell that HSCM was used as 9.5pA reference source, also STCM were
used for input current mirrors (left side of the SDDA cell). The size of the adder is 392p.m
x 150pm in 1.5pm CMOS (the manufactured SDDA cell has not been manufactured yet
due to delay in the production).
Figure 5.11. Layout of the SDDA ceU (392pmx 150pm in CMOS 15pm)
Simulated output from this cell is shown in Fig. 5.12. Input current signal for this
cell is shown at the top of the figure. There are ten levels of input current from OpA to
270pA in steps of 30pA. Shape of the output signals is already known and have been
described in Chapter 3.3.2. The clock cycle was 100ns.
It is visible from the diagram how the ten levels of the current comparators were
set producj
"0
2
time [ms]
Layout of this circuit is shown in Fig. 5.10. It is obvious that complexity of this
circuit is much grater than the other presented in this thesis. Consequently, the space occupancy is prohibitively high. It is obvious that the choice of working algorithm is the most
important decision in this kind of design.
Figure 5.13. Photomicrograph of dynamic CMMVL adder (first stage) (415pm x 426pm in 1.5pm
CMOS)
CHAPTER 6
Conclusions
Concept of current-mode multiple-valued logic (CMMVL) was studied and presented. As a result of effort put into this thesis work a set of basic building blocks for
CMMVL applications was manufactured and examined. The building blocks were used in
higher level of design for two versions of working CMMVL adders and one demonstration version of dynamic mode-mode circuit.
One of the conclusions from this thesis is that choice of numerical representation
and adding algorithm is the most important factor for success of the approach. The algorithm determines number of required signal levels and, therefore, feasibility in today's
ULSI technology. It has been demonstrated that circuits built in today's CMOS can distinguish up to 20 levels of current signal. However, reported MVL circuits in voltage mode
used up to 4 levels of voltage signals.
Obviously low-power voltages of 3.3V, and below, will even more support choice
of current mode approach. It should be noted, once more, that carry-over propagation free
algorithms (such as radix algorithms) have clear advantages for long-words operations
due to the fact that the operational time of the single step can be even slower than in usual
binary application, while the overall executing time is independent of the word length.
Radix algorithms proved useful for MVL applications. First CMMVL adder cell
called positive-digit adder (PDA) was designed in 0.8pm CMOS technology, powered by
VDD = 3.3V, with seven levels of current signal using unit current step ISO= 1l p A and
implemented positive-digit radix-2 algorithm, noise margins are less than 20%, and the
size is 180pm x 75pm. In comparison PDA cell from [4] was designed in 5pm CMOS,
was powered by VDD = 5V, used ISO= 70pA, with noise margins approximately 30%,
and occupied 252.5pm x 450pm of silicon space. The improvement in effective area is
25%, in noise margins approximately 3096, while maintaining the same level of delay time
of approximately 70ns. Both designs proved feasibility of the concept, with clear advantages showing when a more advanced CMOS technology was used.
The second design was single digit decimal adder (SDDA) designed in 1.5pm
CMOS technology, powered by VDD = 5V, with ten levels of current signal using unit
current step ISO= l p A and implemented decimal current adding algorithm. Size of the cell
is 392pm x 150pm. Effective area is close to the PDA design in 0.8pm, but the unit current step is extremely low. Lower current will result in longer delay time (estimated worst
case delay time is around 200ns). Application of current mirrors using the Super MOS
transistors and open-loop current comparators with voltage output decreased the unit current step down to 1pA. However, overall complexity of the adder circuit is increased significantly. It should be noted here that area of the decimal adder is larger than area of a
typical binary adder in the same technology. Full advantage of CMMVL approach in saving silicon area can be expected in higher level designs such as CMMVL multipliers.
In the last presented design yet another approach was demonstrated. The circuit
was built by using current mirrors built of the Super MOS transistors, and closed loop current comparators. The increase in overall complexity of this circuit is obvious resulting in
increase size of the adder. However, the structure is very regular, due to regular shapes of
both the CMOS transistor and the current comparator.
Introduction of CMMVL approach clearly reduces number of a data bus wiring
complexity. For example, 4-digit adder using SDDA cell requires 4 wires for the input
data bus and covers range of numbers from 0 to 9999. In the same time similar binary
adder would require input data bus 14 wires wide. By the experiments, it is verified that
the circuits operate satisfactorily with sufficient noise margins as far as the characteristic is
concerned. In the actual ULSI implementation, however, a more detailed investigation is
required on various aspects, such as the tolerance against supply voltage variation and the
tolerance in the device parameters in the fabrication.
By comparing the results of the two used technologies it can be seen that one of the
key factors for success of this type of analog design is maturity of used technology. Naturally, more mature technology has less fluctuation in production resulting in higher uniformity of the chips. Furthermore, for designs that operate "on the edge" it is very important
to have extremely accurate device models that show real device response at low voltages
and low currents.
Finally, it can be concluded that initial testing of CMMVL logic circuits prove feasibility of the CMMVL concept. Future work will focus on CMMVL multipliers for DSP
applications.
References
C. Toumazou, F.J. Lidhey, D.G. Haigh "Analogue IC design: the current mode
approach", Peter Peregrinus Ltd., London, 1990.
R. W. Kayes, "The Wire Limited Logic Chip" IEEE J. of Solid State Circuits, Vol.
SC- 17, NO. 6, pp. 1232-1233, 1982.
K. W. Current, "Memory Circuits for Multiple Valued Logic Voltage Signals",
International Symposium on Multiple-Valued Logic Proc., pp. 52-57, 1995.
S. Kawahito, K. Mizuno, T. Nakamura "Multiple Valued Current Mode Circuits
Based on Redundant Positive-Digit Number Representation" International Symposium on Multiple-Valued Logic Proceedings, pp. 330-339, 1991.
M. Stark "Two bits per cell R O W COMPCON Proc., pp. 209-212, 1981.
M. Kameyama, T. Higuchi, S. Kaqahito, M. Ishida, T. Nakamura, K. Mizuno "A
Multiple Valued Current Mode Parallel Multiplier Based on Redundant Positive
Digit Number Representation", Systems and Computers in Japan, Vol. 24, pp. 4052, No. 5, 1993.
S. Kawahito, M. Kameyama, "A 32 x 32 Multiplier Using Multiple-Valued MOS
Current-Mode Circuits", IEEE J, of Solid State Circuits, Vol. 23, pp. 124-132, No.
1, 1988.
B.A. Taheri "Proposed CMOS VLSI Implementation of an Electronic Neuron
Using Multi-Valued Signal Processing", International Symposium on Multiple-Valued Logic Proc. Vol. 21, pp. 203-209, 1991.
M. Karneyama, "Toward The Age Of Beyond-Binary Electronics And Systems",
International Symposium on Multiple-Valued Logic Proc., pp. 162-166, 1990.
K. W. Current, "A CMOS Quaternary Threshold Logic Full Adder Circuit With
Transparent Latch", International Symposium on Multiple-Valued Logic Proc., pp.
168-173, 1990.
R.L. Geiger, P.E. Allen and N.R. Strader "VLSI Design Techniques for Analog and
Digital Circuits" McGraw-Hill, 1990.
[24] T. Hanyu, T. Higuchi, Y. Kojima, "A multiple valued logic array VLSI based on
two transistor delta literal circuit and its application to real time reasoning systems", International Symposium on Multiple-Valued Logic Proc. Vol. 2 1, pp. 1623, 1991.
1251 E.A. Vittoz "The design of High-Performance Analog Circuits on Digital CMOS
Chips" IEEE J. of Solid State Circuits, Vol. SC-20, No. 3, 1985.
1261 B. Radanovic, M. Sy-rzycki "Current-Mode CMOS Adders Using Multiple-Valued
Logic" Canadian Conference on Electrical and Computer Engineering CCECE'96
Calgary, Alberta, May 1996.
1271 S. Kawahito, M. Karneyama "A 200 MHz Pipelined Multiplier Using 1.W Supply
Multiple Valued MOS Current Mode Circuits with Dual Rail Source Coupled
Logic", IEEE J. of Solid State Circuits, Vol. 30, pp. 1239-1245, No. 11, 1995.
[28] R. Hobson, private conversation, August 1996