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DATA SHEET
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The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40374B
MSI
Octal D-type flip-flop with 3-state
outputs
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF40374B
MSI
DESCRIPTION
The HEF40374B is an octal D-type flip-flop with 3-state
buffered outputs with a common clock input (CP). The
device is used primarily as an 8-bit positive edge-triggered
storage register for interfacing with a 3-state bus. Data on
the D-inputs is transferred to storage during the
LOW-to-HIGH transition of the clock (CP) input. The
3-state output buffers are controlled by an active LOW
output enable input (EO). A HIGH on EO forces the eight
outputs to a high impedance OFF-state. When EO is
LOW, the data in the register appears at the outputs.
PINNING
HEF40374BP(N): 20-lead DIL; plastic (SOT146-1)
D0 to D7
data inputs
HEF40374BD(F):
CP
clock input
EO
HEF40374BT(D):
O0 to O7
January 1995
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Philips Semiconductors
January 1995
Fig.3 Logic diagram.
Product specification
HEF40374B
MSI
Philips Semiconductors
Product specification
HEF40374B
MSI
CP
Dn
INTERNAL
REGISTER
OUTPUTS
O0 TO O7
Notes
1. H = HIGH state (the more positive voltage)
h = HIGH state (one set-up time prior to the LOW-to-HIGH clock transition)
L = LOW state (the less positive voltage)
I = LOW state (one set-up time prior to the LOW-to-HIGH clock transition)
Z = high impedance OFF-state
= LOW-to-HIGH clock transition
January 1995
Philips Semiconductors
Product specification
HEF40374B
MSI
II
max.
10 mA
IO
max.
25 mA
max.
100 mA
DC CHARACTERISTICS
VSS = 0 V
VDD
V
VOH
V
VOL
V
Tamb (C)
SYMBOL
40
MIN.
Output current
HIGH
Output current
HIGH
Output current
LOW
Hysteresis
4,6
10
9,5
15
13,5
3,6
10
8,4
15
13,2
IOH
0,4
10
0,5
15
1,5
voltage at
10
15
VH
MIN.
TYP.
0,6
1,2
0,45
mA
1,5
3,0
1,1
mA
15,5
mA
15
50
9,3
10
24
10,7
mA
14,4
15
46
15,0
mA
19,5
20
62
19,8
mA
9,5
30,0
TYP.
0,75
2,9
IOL
MIN.
+ 85
1,85
14,5
IOH
TYP.
+ 25
2,3
7,6
25
5,4
17
45
1,75
mA
5,50
mA
19,0
mA
220
mV
250
mV
320
mV
January 1995
Philips Semiconductors
Product specification
HEF40374B
MSI
SYMBOL
MIN.
TYP.
TYPICAL EXTRAPOLATION
FORMULA
MAX.
Propagation delays
CP On
HIGH to LOW
5
10
tPHL
15
CP On
LOW to HIGH
5
10
tPLH
15
Output transition
times
HIGH to LOW
LOW to HIGH
125
250
ns
55
110
ns
54 ns + (0,01 ns/pF) CL
40
80
ns
36 ns + (0,07 ns/pF) CL
125
250
ns
55
110
ns
53 ns + (0,03 ns/pF) CL
40
80
ns
39 ns + (0,02 ns/pF) CL
40
80
ns
20
40
ns
15
15
30
ns
30
60
ns
20
40
ns
15
15
30
ns
60
120
ns
30
60
ns
10
10
tTHL
tTLH
LOW
10
tPHZ
15
24
48
ns
70
140
ns
35
70
ns
15
30
60
ns
65
130
ns
10
tPLZ
LOW
10
tPZH
30
60
ns
15
24
48
ns
85
170
ns
35
70
ns
25
50
ns
10
tPZL
15
Set-up time
Dn CP
Hold time
Dn CP
5
10
ns
20
ns
20
ns
20
10
ns
15
ns
10
ns
15
January 1995
15
10
tsu
20
thold
see Fig.6
Philips Semiconductors
Product specification
HEF40374B
MSI
VDD
V
Minimum clock
pulse width; LOW
Maximum clock
pulse frequency
SYMBOL
MIN.
5
10
tWCPL
TYP.
TYPICAL EXTRAPOLATION
FORMULA
MAX.
50
25
ns
25
12
ns
15
20
10
ns
25
MHz
12
MHz
17
MHz
10
fmax
15
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 C; input transition times 20 ns
Dynamic power
VDD
V
dissipation per
10
15 700 fi + (foCL)
package (P)
15
40 575 fi + (foCL)
VDD2
VDD2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
(foCL) = sum of outputs
VDD = supply voltage (V)
tTLH
tTHL
January 1995