UNIVERSITY OF EDINBURGH

COLLEGE OF SCIENCE AND ENGINEERING

SCHOOL OF ENGINEERING AND ELECTRONICS

Convenor of the Board of Examiners: Professor A F Murray

External Examiner: Professor L Hanzo and Professor W Milne

17th August 2005

2.30pm 4.30pm

ELECTRONICS 2:
ANALOGUE CIRCUITS
DIGITAL CIRCUITS

This paper consists of SIX sections.

Candidates must answer ALL QUESTIONS in SECTION A and D, and ONE question in
each of SECTIONS B, C, E, F.

Students should assume reasonable values for any data not given in a question nor available on a
datasheet, and should make any such assumptions clear on their script.
Students in any doubt as to the interpretation of the wording of a question, should make their own
decision, and should state it clearly on their script.
Only a calculator from the list approved by the College of Science and Engineering may be used in this
examination.
The examination paper that you are now sitting is to be marked ANONYMOUSLY.
Please write your name in the space indicated at the top right hand corner on the front cover of
the answer book. Also enter your examination number in the appropriate space on the front
cover.
Write ONLY your examination number on any extra sheets, worksheets or graph paper used and
firmly attach these to the answer book(s).
Relevant supporting data and equations are bound with the examination paper.

SECTION A
Question A1

Attempt all parts of this question.

With reference to an operational amplifier, write short notes on the
following:-

a)

Input current.

(2)

b)

Input offset voltage.

(2)

c)

Output voltage range.

(2)

d)

Power supply rejection ratio.

(2)

e)

Slew rate.

(2)

Electronics 2 August 2005

SECTION A
Question A2

Attempt all parts of this question

a)

Draw the hybrid- small-signal model for an NPN transistor.

(2)

b)

Show that the transconductance of an NPN transistor is given by

gm = IC /VT , where IC is the collector current and VT is the thermal voltage
given by VT = kT/q and is approximately 26mV at room temperature.
(4)

c)

Show that the output resistance of an NPN transistor is given by

r0 = VA /IC , where VA is the transistor Early voltage (which is negative
for an NPN transistor).

(4)

Electronics 2 August 2005

SECTION B
Question B1

Attempt all parts of this question.

An operational amplifier circuit is shown in Figure QB1. Z1 and Z2 are
impedances.

a)

Derive an expression for the transfer function of the amplifier circuit (2)
shown in Figure QB1. Show your working.

b)

Assume that Z1 is comprised of a resistor, R1, and a capacitor, C1, in

series. Assume also that Z2 is comprised of a resistor, R2, in parallel with
a capacitor, C2. Derive an expression for the transfer function of this
circuit. Express the transfer function as a product of standard forms i.e. a
product of constant, j, low pass, inverted low pass and high pass forms.
(5)

c)

Sketch a Bode plot for this circuit showing both the magnitude and phase
2
R2 , R1C 1
1 10 seconds and
response. Assume that R 1
5
1 10 seconds. State any assumptions made.
that R 2 C 2
(7)

d)

What type of filter is this?

(1)

Figure QB1

Electronics 2 August 2005

SECTION B
Question B2

Attempt all parts of this question.

An operational amplifier has an open loop DC gain of 60dB and poles
or cut-off frequencies at 100kHz and 100MHz.

a)

Sketch a Bode plots for this amplifier showing both the magnitude and
phase response.
(6)

b)

At what frequency is the open loop gain unity?

c)

What is potentially the most unstable circuit configuration that this

operational amplifier might be used in?
(1)

d)

What is the worst case phase margin for this amplifier circuit?

e)

Using this operational amplifier, design an inverting amplifier with a

closed loop gain of 26dB.
(3)

f)

Estimate the bandwidth of the resulting inverting amplifier.

(1)

(2)

(2)

Electronics 2 August 2005

SECTION C
Question C1

Attempt all parts of this question.

Figure QC1 shows a common-emitter amplifier.

a)

Assuming that we know the transistor current gain, , and the resistor
values, show that the transistor collector current is given by:
VBB VBE
IC =
RBB + ( + 1)R E

(10)

b)

If we would like the collector current to be relatively stable for high

(2)
but variable, should we design RBB to have a high or a low value?

c)

What is the function of resistor RE in the circuit shown in Figure QC1?

How does a resistor RE with a positive value, affect the operation of the
circuit?
(3)

d)

If an AC signal, vin , is injected directly onto the base of the transistor in

Figure QC1, and if we take as our output vout , the AC signal on the
transistor collector, give an approximate expression for the AC gain of
the transistor, vout /vin, in terms of resistor values.
(2)

e)

Will the actual AC gain of the circuit will be more or less than the
estimated value? What practical factors will cause this to be the case?
(3)

Figure QC1: Common Emitter Transistor Amplifier

Electronics 2 August 2005

SECTION C
Question C2

Attempt all parts of this question.

Figure QC2 shows a common-collector amplifier.

a)

Write down the small-signal model for this circuit based on the hybrid-
(5)
transistor model.

b)

Show that the AC gain of this circuit is given by

v out
(g + g m )
=
v in
(g + g m + g 0 + GE ) , where GE = 1/RE , g = 1/r and g0 = 1/r0 .

(5)

c)

Find the small-signal output impedance of this circuit in terms of the

transistor parameters and the resistor values.
(5)

d)

For normal transistor parameters and resistor values would you expect the
numerical value for Rout to be less than 10, in the tens of ohms, hundreds
(2)
of ohms, kilo-ohms or mega-ohms?

e)

Is the calculated value for Rout realistic? If not, why not, and what would
be a more realistic value?
(3)

Figure QC2: Common Collector Transistor Amplifier

Electronics 2 August 2005

SECTION D
Question D1

Attempt all parts of this question.

a)

Figure QD1a shows the design of a synchronous counter. Determine the

count sequence.
(2)

b)

Given a positive edge triggered D-type flip flop, as shown in Figure

QD1b, design a flip flop whose input can be preset (set to one) when an
external preset signal goes high. You may use any combination of logic
gates.
(3)

c)

Draw the circuit diagram for a device that will generate an active high,
power on reset signal. This signal should return to low after a preset
time. Identify all the components of the circuit clearly.
(3)

d)

What do the three states of a tristate output represent?

5V

(2)

5V
R

D
Clk

Clk
D-type

Clk
D-type

Clk
D-type

Figure QD1a

Figure QD1b

Electronics 2 August 2005

SECTION D
Question D2

a)

State the result of each of the following six Boolean logic operations:
(i)
(ii)
(iii)
(iv)
(v)
(vi)

b)

A
A
A
A
1
A

+
+

+
+

1
A
1
A
1
0

(2)

Give the truth table for the Boolean logic expression:

A + B

c)

(2)

Give the minimum term product of sums form for the Boolean expression:
AB + CD

(2)

d)

Give an example of De Morgans theorem, using the variables X and Y .

(2)

e)

Give the CMOS transistor circuit for a positive logic two-input NAND
gate.

(2)

Electronics 2 August 2005

SECTION E
Question E1 Solutions to this question must include intermediate working, or other
annotation showing the process used, for full credit to be obtained.
a)

b)

c)

d)

The three-bit variable M 2 : 0 {m 2 , m 1 , m 0 } holds values encoded with

sign & magnitude code. The three-bit variable T 2 : 0 {t 2 , t 1 , t 0 } holds
values encoded with twos complement code.
Give two tables, one for each of M 2 : 0 and T 2 : 0 , showing all binary codes
and their corresponding values.

(4)

By equating codes in M 2 : 0 and T 2 : 0 representing the same value, give a

canonical sum of products expression for each of: t 2 , t 1 and t 0 ; in terms of
m 2 , m 1 and m 0 .

(2)

Enter each expression from b) on a Karnaugh map and thence extract, in

product of sums form, minimised expressions.

(5)

Starting from the results of c), derive a gate efficient network using only
two-input and three-input NOR gates, which converts three-bit
sign & magnitude code into twos complement code.

(4)

Electronics 2 August 2005

SECTION E
Question E2 Solutions to this question must include intermediate working, or other
annotation showing the process used, for full credit to be obtained.
a)

b)

c)

d)

A tank for holding liquid has three binary sensors, L 2:0 {l 2 , l 1 , l 0 },

arranged such that when the tank is empty, L 2:0 = 000. For each
additional litre of liquid in the tank, the corresponding L 2:0 codes are:
001, 011 and 111.
With the aid of Karnaugh maps, derive the minimised sum of products
equations for a two-bit word, B1:0 {b1 , b0 }, in which the value indicated
by the sensors is given in unsigned natural binary arithmetic code.

(5)

Give a minimum gate circuit for the conversion of L 2:0 to B1:0 , using only
two-input NOR gates.

(3)

Derive an expression for, and draw, a minimised two-input NOR gate

circuit, which produces an output Q from inputs V and C. When C is true
Q is false; otherwise, when V is true Q is true, and when V is false Q
retains its previous value.

(5)

Hence, give a circuit using only two-input NOR gates, which converts
L 2:0 to B1:0 retaining and emitting the peak value until reset to 00 by the
signal C.

(2)

Electronics 2 August 2005

SECTION F
Question F1

Attempt all parts of this question. Solutions to this question must

include intermediate working, or other annotation showing the process
used, for full credit to be obtained.

a)

Figure QF1a shows the state transition diagram for a synchronous state
machine. An X indicates that the input may be a 0 or a 1 for that
particular transition to occur. Write out a next state table for this state
machine.
(5)

b)

Use the state assignment given in Table QF1b below, determine sums of
products expressions for the outputs Y, Z and W.
(4)

c)

Determine sums of products expressions that will calculate the next state
+

variables, A and B , when the state assignment in Table QF1b is used.

The expressions should be minimised to contain as few product terms as (6)
possible.
Input values U,V

Key:

?,?
State Name
0,0

X = don't care

?,?,?
Output values Y,Z,W

S0
0,0
0,0,0
1,0
X,1

1,X

S2
S1
1,1,1
0,0,1
0,1

0,0

X,1
1,0

X,X
S3

0,1,1

Figure QF1a

State
S0
S1
S2
S3

A
0
0
1
1

B
0
1
0
1

Figure QF1b
Electronics 2 August 2005

SECTION F
Question F2

Attempt all parts of this question. Solutions to this question must

include intermediate working, or other annotation showing the process
used, for full credit to be obtained.

a)

Describe one major difference between programmable array logic (PAL)

and read only memory (ROM) devices.
(2)

b)

The next state and output equations for a state machine may be written
as:

A = X + ABY + ABY
B = BXY + ABX + AXY + BXY
K = AB
L = AB + AB
(6)
These equations are to be implemented on the PAL device shown in the
attached worksheet. The PAL device will then be connected to external
flip flop devices in order for the state machine to function. Show on the
worksheet how the PAL device should be programmed to implement
these equations, clearly identifying all inputs and outputs that you use in
the design.
c)

Is the state machine in Figure QF2 a Moore machine or a Mealy

machine? Justify your answer.
(2)

d)

The engineer who defined the state machine in question QF2 proposes to
add an extra output equation to the machine:

M = YAB + XA + BAYX +AX + ABYX + BA

Find a minimum sum of products for this expression (do not attempt to
programme this output into the PAL device). Would the addition of this
(5)
output to the state machine change your answer to QF2?

Electronics 2 August 2005

END OF PAPER

Electronics 2 August 2005

WORKSHEET FOR QUESTION F2b

Figure QF2b
Electronics 2 August 2005