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F CAPACITORS
TABLE 1POWER-SUPPLY PARAMETERS WITH ALL 1-
VOUT
(V)
5.06
5.01
4.9
IOUT
(mA)
10
20
30
POUT
(mW)
50.6
100.2
147
IIN at VIN=3.3V
(mA)
20.9
41.1
62.2
PIN
(mW)
68.8
135.6
205.3
VRIPPLE
(mV p-p)
358
312
420
F CAPACITORS
TABLE 2POWER-SUPPLY PARAMETERS WITH ALL 3-
VOUT
(V)
4.99
4.99
4.98
4.93
4.9
IOUT
(mA)
10
20
30
40
45
POUT
(mW)
49.9
99.8
149.4
197.2
220.5
IIN at VIN=3.3V
(mA)
20.37
40.4
60.6
80.5
90.5
PIN Efficiency
(mW)
(%)
68.8
74.2
133.3
74.9
200
74.7
265.7
74.2
298.7
73.8
VOUT low-dropout
regulator (V)
2.63
2.76
2.89
3.02
3.09
VRIPPLE
(mV p-p)
154
104
154
192
214
voltage regulator. The low-dropout regulator, IC1, reduces the 3.3V input to a
lower value, and the unregulated charge
pump, IC2, doubles that value to 5V. To
cancel the voltage drop that chargepump output impedance causes, the circuit feeds the 5V output back to the lowdropout regulator, which alters its output
to maintain output regulation. The available headroom of at least 1V allows output currents to approximately 30 mA or
even higher with larger capacitors. Although it requires two ICs instead of a
single regulated charge pump, this approach can be cheaper because high-vol5V power supply teams low-dropout
regulator, charge pump ..............................59
Four-quadrant power supply provides
any-polarity voltage and current ..............60
Simple circuit controls
stepper motors................................................64
Simple dc/dc converter increases available
power in dual-voltage system ....................66
Publish your Design Idea in EDN. See the
Whats Up section at www.edn.com.
design
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a regulated-charge-pump circuit.
Table 1 demonstrates the circuits ability to maintain output-voltage regulation
and deliver currents as high as 30 mA; the
input, output, and flying capacitors are
all 1 F. Similarly, Table 2 shows the regulation for output currents to 45 mA; all
17
ISRC
for a minus supply,
19
ICONTROL
CW
ISNK
261
for example, or the
VCSNK
V+ 3
12 V LT1970CFE
CSNK
V
10k
S+
13 V
fourth quadrant as a
10k
CSRC
S
2
100
4
OUTPUT
discharge-testing a
FILTER
220 pF
CW
IRLZ24
6
9 VEE
VCSRC
+
battery with a specif10k
5
10k
ic constant current,
1, 10,
10
11, 20
for example. It also
2 F
0.1 F
cannot transition
3.01k
10k
BAV99TA
1
nF
100
seamlessly between
+
VCONTROL
4.7 F
the various modes as
50V
a function of load
17V
RETURN
10 F
condition or control
0.1 F
+
35V
input. The circuit in
0.1
1W
Figure 1 achieves full
VOLTAGE DIGITAL
CURRENT
PANEL METER VIN
COMMON
four-quadrant capaDIGITAL PANEL METER
VIN
CURRENT DIGITAL
bility with an output
PANEL METER +VIN
topology simiFigure 1
lar to that of an
You can obtain four-quadrant power-supply operation by using a power op amp in the output section.
ordinary audio power amplifier by using
a complementary pass-transistor con- least 16V adjustability with as much as ICONTROL, respectively (Figure 2). You can
figuration. The complementary section 2A output capability. Figure 1 shows adjust VCONTROL from 5 to 5V, and the
may be the basic op-amp output in low- the basic LT1970-based regulator section. LT1970 regulator circuit amplifies it to
er current designs or use external power Figure 2 shows the user-control analog form the nominal 16.5V output range.
MOSFETs in cases involving higher pow- section, using an LT1790-5 reference and You can adjust ICONTROL from 0 to 5V; 5V
er. Controlling the output in the various an LT1882 quad-precision op amp. The represents the maximum user currentmodes is a simple matter when you use entire circuit operates from a preregulat- limit command. The VCSNK and VCSRC
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trimmers attenuate the ICONTROL signal to to compensating the op amp for minimal Schottky diode, such as a 1N5821 cathset the precise full-scale currents for sink overshoot under all loading conditions. ode, to the more positive connection, to
and source modes, respectively (Figure 1). As with most op amps, the LT1970s in- the output binding posts. Alternatively,
A 0.1 resistor in the load return sens- ner- and outer-loop feedback accomplish you could use a disconnect relay and powes the output current and provides the capacitive-load tolerance. In this situa- er sequencer in the design to protect the
LT1970 with feedback during current- tion, the op amp itself is resistively de- load from any energetic reverse transients
limiting operation. With this sense re- coupled from the load. The dc feedback during turn-on and turn-off of the main
sistance, setting the current-limit trim- for the LT1970 uses differential voltage bulk supply.
mers to 100% would allow the LT1970 to sensing to eliminate the regulation error
An adjustable power supply is an inlimit at approximately 5A, but, because that would otherwise occur with the cur- dispensable tool in any electronics lab. It
this application requires
a 2A maximum current,
CW
you set the trimmers to
ILIMIT
1k
10
50k
approximately 40% ro+ 1/4
8
ICONTROL
tation when calibrated.
LT1882
9 _
100k
To prevent internal control contention at low
CW
output current, the LTVSET
1k
1970 sets a minimum100k
0.1 F
current-limit threshold
10-TURN
5
17V
+
that corresponds to ap1/4
1k
7
VCONTROL
proximately 40 mA for
100k 6 _LT1882
3
1
F
4
12
+
+
1/4
the sense resistance. An5V
1
1/4
14
LT1882
REFERENCE
other nice feature of the
LT1882
2 _
13 _
LT1970 is the availabili11
ty of status flags, which,
in this case, provide a
49.9k
49.9k
simple means of driving 17V
1k
a front-panel LED to in0.1 F
dicate when current5V REFERENCE
2k
4
6
LT1790-5
17V
limiting is active. The
LT1970 features
1 F
1 F
Figure 2
1
2
split power connections that allow you
to power the internal
output section independently from the analog-control portion. The The user-control section allows you to set the voltage range and current-limit parameters for the output section in
flexibility of this config- Figure 1.
uration allows direct
sensing of the op amps output current rent-sense and lead resistances in series can be even more useful in many circumvia resistance in the V (Pin 19) and V with the load. You can connect a pair of stances if it provides the ability to adjust
(Pin 2) connections. This feature gives a inexpensive digital panel meters to the continually through 0V to the polarity,
convenient means of establishing Class output to monitor the output conditions adjustably limit current, or both in either
B operation of the MOSFET-output de- in real time (Figure 1). (The two digital the source or the sink directions. These
vices using a current-feedback method, panel meters do not share commoncon- additional capabilities provide convenient
in which the op-amp output current is nections, which may complicate their methods of driving or loading circuits
converted to a gate-drive potential, there- powering.) Note that the selected current- that are under development or test that
by having the MOSFETs turn on only to sense resistance optimizes a digital-pan- might otherwise require very special or
the extent needed to help the op amp el-meter display with the usual 200-mV custom equipment, such as active-load
provide the output demand.
full-scale sensitivity to present as much as units or dc-offset generators. You can
Because power supplies inherently 1.999A, for example. One word of cau- readily obtain these features if you base
must drive heavy capacitive loads tion: When you use this supply in place the linear-regulator design on the versanamely, circuits with high-value bypass of a conventional single-quadrant supply tile LT1970 power op amp, which includes
capacitorsand any overvoltage could to power sensitive electronics, its good built-in adjustable- closed-loop currentdamage the circuit, pay careful attention practice to connect a reverse-biased limiting functions.
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AGND
VDD
DGND
CAP/2.5V
ONBOARD
REFERENCE
REGULATOR
MCLK
FULL-SCALE
CONTROL
AVDD/
DVDD
2.5V
FREQUENCY 0 REGISTER
28-BIT PHASE
ACCUMULATOR
FREQUENCY 1 REGISTER
COMPARATOR
MULTIPLEXER
12
10-BIT
DAC
SIN
ROM
MSB
MULTIPLEXER
PHASE0 REG
PHASE1 REG
Figure 2
DIVIDE
BY 2
MULTIPLEXER
VOUT
MULTIPLEXER
CONTROL REGISTER
200
SERIAL INTERFACE
AND CONTROL LOGIC
AD9833
FSYNC SCLK SDATA
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47
1k*
OUT
15V
Figure 1
6 _
10 F
6V 1k*
+
4.22k*
5V
HEAT SINK
221
24V
15V
7815
47 F
25V
220 F
16V
100*
39
MCT4052
4
3
2 2
3
C
51 V
D
1 0
11
3 B
9
2 _
2k
+
5
15V +15
OP37
GP
7
6
IC
2 _
3 +
3 +
IC3
S2 4
1
390 pF
200 kHz
0.1
F
3.01k*
1k*
1k
2
LF353N
15V
8
7
IC4
4
15V
LF353N
S1
66.5*
+
220 F
16V
200*
402*
+
+ 22 F
16V
1620*
6.49k*
15V
MCT
DETECTOR
15V
2 _
220 +
F
2k
6V
BIAS
220
F
6V
IN914
IC1
14
12
0
8
10
4
15V
10k
5V
13
5V
6 14
5V
GREEN
LED
24V
7915
100
9 10
11
1k
G0
12 13
1k
G1
15V
10k
390
47 F
25V
1k
+ 220 F
16V
HCT14
4
15V
GND
S3
16
MULTIPLEXER
Q2
2N3094
OP37GP
OR
LT1028
CN8
22 F
6V
1.33k*
0.1
F
+
22 F
16V
3 +
+
A
VE
20k
Q1
2N4403
13k*
15 2
220 F
6V
2.4k
15V
220 F
6V
5V
GAIN
S1
S2
S3
1
2
4
8
16
32
64
128
O
C
O
C
O
C
O
C
C
C
O
O
C
C
O
O
O
O
O
O
C
C
C
C
O=OPEN=OFF.
C=CLOSED=ON.
5.1k
15V
In this programmable-gain circuit, the on-resistance of the gain-setting multiplexer plays no role in the determination of gain.
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design
ideas
C2
capacitor from the sensed voltage
0.01 F
before sampling the voltage across
13
50k
R2
COMP
REFERENCE
the capacitor.
100k
VOLTAGE
V2
15 PB2
To use a typical microconGND 10
D
2
trollers I/O ports, one terminal of
1N916
the capacitor remains connected
to the input source through a
Figure 1
resistor. During most of the
operating time, pins 12, 14, and 15
are configured as output pins and The LEDs in this circuit indicate when the sampled input voltages are above the reference voltage on
are held at logic 0. Diodes D1 and Pin 13.
D2 do not conduct, so capacitors
C1 and C2 charge to the values of the in- tors, pin 12 becomes an input, and the parator compares the voltage on Pin 12
put voltages V1 and V2, respectively. To pin associated with each channel switch- with the reference voltage. Listing 1,
sample the voltage stored in the capaci- es high while the microcontrollers com- which is available on the Web version of
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5V
advisable to put a large amount of external memories near the FPGAs. The
memory consumes a lot of area and increases the difficulty of the pc-board layout. Consider Xilinx (www.xilinx.com)
FPGAs. Xilinx offers daisy-chaining
techniques to program multiple FPGAs
from a single source. However, when
you want to change only one FPGAs
design
ideas
put, VOUT, can directly drive external meters, strip-chart recorders, and A/D-converter inputs.
The R2-R3 voltage divider sets the selected fault-current trip point for IC1s
first internal comparator at 0.6V. Setting
the trip point for a 50-mA fault, for instance, establishes the following relationship between R1 and R2: R2/(R1R2)
0.6V/(R1100IFAULT), so R115.67R2.
When faults occur, the COUT1 output assumes a high-impedance state and is
pulled high by R3. The noninverting cascaded-transistor pair Q2-Q3 provides an
interface to the high loop voltage and
preserves a proper logic polarity for controlling the gate of Q1. Q1 is held in the off
state until pushbutton PB1 or another reset signal resets IC1s first comparator. (To
disable this comparators latched output,
tie the Reset# pin to ground.) Zener
diode ZD1 protects Q1s gate-source junction from overvoltage.
IC2 and its associated circuitry can recover any digital information imposed on
the 4- to 20-mA loop current by moduwww.edn.com
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2
TO FIELD TRANSMITTER
R1
24V DC
4 TO 20mA LOOP
lation. The Highway-Addressable
Q1
2.2k
102k
ZD1
RFD10P03L
Remote Transduc5.1V
5V
er Protocol, for in5V
_
stance, typically
5V
+
uses FSK (fre2.6k
10k
IC2
5V
MAX4322
0.1 F
quency-shift key10k
10k
10k
ing) of 1200 to
IC1
10
10k
10k
R2
R3
RS
RS 9
2400 Hz to moduMAX4375
154k
10k
1
2
+VCC
VOUT
late the loop cur6
3
RESET#
CIN1
rent between the
Q2
7
4
COUT2
CIN2
0.5mA levels.
2N3904
8
5
COUT1
GND
(For this circuit,
the modulatQ3
PB1
Figure 2
2N3904
FAULT RESET
ed signal at
LOOP RETURN
VOUT (Pin 2 of IC1)
DIGITAL-SIGNAL OUTPUT
is 0.1V.) VOUT
from IC1 is capacTO PROCESS-INDICATOR PANEL OR ADC
itively coupled to
This
circuit
provides fault protection and digital-signal recovery for a 4- to 20-mA current loop.
IC2 and amplified
by that device to
recover such digital signals. IC1 includes version in IC2s digital-signal output. covered digital signal as a clean rectana second comparator with inverting in- Though not essential, this comparator gular waveform for driving external cirput, which you can use to cancel the in- output (COUT2) can also present the re- cuitry.
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OUTP
OUTN
SEL SEL
SEL
INP
SEL
INN
Figure 1
ble the effective throughput of the overall system. It is essential to overall performance that you use a high-quality,
high-speed switch in the multiplexing of
the DACs outputs. The current-mode
DACs in this Design Idea allow for current-steering implementation of the output switch. Current steering uses two differential-transistor pairs cross-coupled in
the form of a four-quadrant multiplier
(Figure 1). In this topology, the saturation voltages of the transistors are minimal, voltage swings are small, and switching speeds are high.
The 2.5-GHz AD8343 mixer contains
a complete four-quadrant-multiplier
structure that you can use as a highspeed, current-mode switch. The bias
Figure 2
50
DATA BUS A
D0-D9
IOUT
IOUT
IC1
AD9731
10-BIT,
170M-SAMPLE/SEC
DAC
REF_IN
CLK
CLK
50
RSET
INP
INN
IC3
90LV027A
LOP
CLK
10
OUTP
IC5
AD8343
2.5-GHz MIXER
OUTN
LON
CA_OUT
CA_IN
REF_OUT
1.96k
5V
OUT
50
DATA BUS B
D0-D9
IOUT
IOUT
IC2
AD9731
10-BIT,
170M-SAMPLE/SEC
DAC
REF_IN
CLK
CLK
50
RSET
INP
INN
IC4
90LV027A
CLK
CA_OUT
CA_IN
REF_OUT
LOP
10
OUTP
IC6
AD8343
2.5-GHz MIXER
OUTN
LON
1.96k
Ping-ponging the outputs of two DACs effectively doubles the throughput rate.
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design
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outputs. With only a minimal drive signal at the base connections, the emitters
appear as a virtual ac ground. The reduced voltage swing at these nodes minimizes the effect of any parasitic capacitances. This Design Idea uses two
AD8343 mixers as high-speed switches
to multiplex the differential output currents derived from two AD9731 DACs
(Figure 2). On the output side of the
mixers, the termination resistors allow
for a dc path to the supply, provide for
the current-to-voltage conversion, and
present a single-ended back-termination impedance of 50. This configuration allows the circuit to drive a remotely located, 100, differential load
via two 50 coaxial cables. The low-level clock signals at the LO inputs come
from high-speed LVDS buffers terminated in resistances of 10. The approximate 3.5-mA p-p drivers produce roughly 70-mV p-p drive at
Figure 3
the LO inputs. Figure 3 shows
The circuit in Figure 2 produces outputs with
that the circuit provides output rise and
less-than-200-psec rise and fall times.
fall times faster than 200 psec.
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AGND
VDD
DGND
MCLK
CAP/2.5V
ONBOARD
REFERENCE
REGULATOR
FULL-SCALE
CONTROL
AVDD/
DVDD
2.5V
FREQUENCY0 REGISTER
MULTIPLEXER
28-BIT PHASE
ACCUMULATOR
FREQUENCY1 REGISTER
COMPARATOR
12
10-BIT
DAC
SIN
ROM
MSB
MULTIPLEXER
PHASE0 REG
PHASE1 REG
Figure 2
VOUT
DIVIDE
BY 2
MULTIPLEXER
CONTROL REGISTER
200
MULTIPLEXER
SERIAL INTERFACE
AND CONTROL LOGIC
AD9833
FSYNC SCLK SDATA
This DDS chip generates signals with 0.1-Hz resolution from a 25-MHz clock.
VOUT
GAIN= 1
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C1
10 F
Figure 2
R1
R2
15.8k
15.8k
VOUT
V
0.1 F
1
2
VIN
C2
0.1 F
GAIN
CONTROL
VOUT1VIN
VOUT2VIN
VOUT5VIN
VOUT10VIN
VOUT20VIN
VOUT50VIN
VOUT100VIN
3
4
GN2
0
0
0
1
1
1
1
IC2
LT1884
7
15.8k
6
5
GN1
0
1
1
0
0
1
1
R4
0.1 F
0.1 F
1
1 F
IC1
LTC6910-1
V
0.1 F
GN0
1
0
1
0
1
0
1
R3
3
0.1 F
4
15.8k
IC3
LTC6910-1
6
5
BANDWIDTH
CONTROL
BANDWIDTH1 TO 10 Hz
BANDWIDTH1 TO 20 Hz
BANDWIDTH1 TO 50 Hz
BANDWIDTH1 TO 100 Hz
BANDWIDTH1 TO 200 Hz
BANDWIDTH1 TO 500 Hz
BANDWIDTH1Hz TO 1 kHz
BW2
0
0
0
1
1
1
1
BW1 BW0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
This detailed implementation of the circuit in Figure 1 operates with dual power supplies.
design
ideas
Figure 1
VIN
D1
9 TO 18V DC
1
10 F
25V
4.99M
10 F
25V
33
1/4W
10 F
25V
T1
12
D3
0.022 F
500V
D4
0.022 F
500V
4.99M
0.022 F
500V
D2
D5
R4
100
5W
1 kVOUT
11
220 pF
200V
68.1k
C3
C1
0.022 F
500V
10
4
0.022 F
500V
0.01 F
1500V
0.01 F
1500V
100
1
RUN
SENSE
10
9
5
2
3
1 nF
33k
12.4k
12.4k
R1
220k 5
ITH
VIN
IC1
LTC1871
FB
INTVCC
FREQ
GATE
MODE
GND
9
8
Q1
Si7456DP
8
6
7
Q2
VN2222
6.8 nF
4.7 F
R2
0.02
R3
1.5
This circuit delivers 1 kV from a low-voltage input and can produce continuous arcing.
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ISOLUTED VOLTMETER
voltmeter returns to Cell 1 and
MICROCONTROLLER
ABSOLUTE CONVERTER BLOCK
restarts the process.
SOLID-STATE-RELAY MATRIX
CELL
Table 1 shows the alternatHSR412
ADDRESS
SSR(N)
A
ing polarity of A and B wires as
_
ADC
the cells are measured. To
+
measure the voltage of an in2V +
MEMORY
V1
B
POWER SUPPLY
crocontroller controls the seHCPL2631
HCPL0600
quence of measurement
events. To measure a cell, the
microcontroller sends out a
2
8
DATA
CAN BUS
discrete 8-bit digital address
corresponding to the cell being
measured. This address goes to
151
11 TIMES
a decoding block composed of
74HC154
2V +
11 74HC154 multiplexers. The
V148
DECODING BLOCK
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R3
IC2A
430
2 MAX966
monitors the delta (difference) between
Vcc
the filters input and output. When the
Vcc
C5
delta exceeds 50 mV, the filter increases
R5
0.1 F
R2
10k
430
its slew rate by increasing the cutoff freR4
7
6
+
Q5
8
quency by an order of magnitude. The
C3
510k
5
2N3904
1 nF
IC2B
switched-capacitor filter, IC1, normally opR1
2 MAX966
erates as a self-clocked device. Capacitors
33k
C1 and C2 set the cutoff frequency at 0.1
Q1
Q2
Hz, and other circuitry forms a dynamic
2N3904
2N3904
window comparator. Transistor
Figure 1
pairs Q1-Q2 and Q3-Q4 form a
complementary current mirror whose This lowpass filter maintains a fast step response by dynamically adjusting its cutoff frequency.
output flows through R2 and R3, creating
a delta of 50 mV. Connecting the output upper threshold at VOUT50 mV and the 312-Hz cutoff frequency that reduces
sensitivity to momentary glitches. The filvoltage to the center tap of the two resis- lower threshold at VOUT50 mV.
tors centers the delta on the output voltage.
R4 and C3 provide lowpass-filtering to tered input drives the window comparaYou therefore set the window comparators the original input signal, producing a tors input. If that input is outside the
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Circuit provides
efficient fan-speed control ..........................69
Simple circuit forms
multichannel temperature monitor ..........70
PWM controller drives LEDs
from high-voltage lines ................................72
Circuit forms satellite-dish
command decoder ........................................72
Use a microcontroller
to design a boost converter ........................74
Publish your Design Idea in EDN. See the
Whats Up section at www.edn.com.
12V
1
2
3
4
0.1 F
39 F
16V
OSCON
1 F
1
2
3
L1
0.1 F
0.1 F
1
2
3
4
5
6
7
8
CVH
PGND
AIN
SHDN
IC1
IN
LX
CVL MAX1685 LX
AGND
BOOT
REF
STBY
FB
ILIM
CC
SYNC
BEAD
33 H
DT3316
16
15
14
13
12
11
10
9
0.1 F
+ 180 F
OSCON
16V
1
2
3
BEAD
0.1 F
MBRS130
1
2
3
0.01 F
15 pF
Figure 1
D1
1N4148
0.1 F
R3
15k
12V
C1
100 F
BEAD
R1
27k
6V
ALUMINUM
ELECTROLYTIC
R2
47k
1
2
3
RT1
10k
NTC
BEAD
0.1 F
To control fan speed, thermistor RT1 adjusts the output voltage of this dc/dc converter.
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1.5 msec and bit values as shown in Figure 1, the timing diagram of bit modulation on the coaxial cable. The signals
ac portion is a 22-Hz burst whose amplitude ranges from 300 to 600 mV. A
voltage-doubler circuit detects the 22Hz portion, producing a pulse stream in
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design
ideas
You can design a simple boost converter with the following conditions:
VIN9V, VOUT18V, RLOAD72 , F1/
T62.5 kHz,
70%, and VDROP50
mV, where F is the switching frequency,
is the efficiency, and VDROP is the output ripple voltage. You can calculate the
on-time, current, ramp-down time, and
the total period in terms of inductance:
design
ideas
TO POWER
driver. This control cirtime is approximately 5.9
PSMC
DAC
ADC
SWITCH
VOLTAGE
FIRMWARE
+
VV
CONTROL
cuit combines analog
sec. The output voltage is
current control and
18V into a 72 load (Figfirmware voltage control.
ure 5). The efficiency is apA microcontroller contains all the elements necessary for boost-converter
The interesting part is the
proximately 90%. These
control.
firmware, which is directboost-converter design and
ly in the voltage-feedback path of the about the system, through a serial port or control ideas are just a few of the many
control loop. Through firmware, you can some other means, by routing the data to possible ones using a PIC16C782 dealter the dynamics of the control loop by a terminal or computer display. Even bet- vice.
changing the functions within the pro- ter, the firmware allows the design to
Figure 4
Figure 5
Figure 1.
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POWER SUPPLY
GND
+
_
V1
40V DC
Q0
Q1
1 H
MOTOR
Q3
Q2
OPTION A
Q6
D1
design
ideas
not low enough. By opening the connection labeled Option A, you isolate the IC
ground from the potentially noisier connection at the source of Q6. Q5 is configured and operates in the same fashion as
Q6. Q5 can have higher on-resistance than
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design
ideas
R1
VCC
VCC
22k
VCC
R2
220k
4.7k
220k
3
SQ_IN
P1
10k
3
2
1k
22 nF
47k
0.1 F
CLOCK
74HC86
IC1
LM393
VCC
VCC
1k
VCC
VCC
14 10
CCV RP
DATA_IN
IC2A
C1
1 nF
IC2B
14 10
CCV RP
9
12
D
Q
CLOCK 11
8
CLK
Q
DNG LC
7 13
74HC74
CLOCK
IC4A
14 4
CCV RP
5
2
D
Q
3
6
CLK
Q
DNG LC
7 1
74HC74
VCC
12
CLOCK 11
74HC86
IC2B
Q
8
CLK
Q
DNG LC
7 13
74HC74
3
R3
ERROR
10k
1
Q1
2N222
VCC
VCC
Figure 3
The simple BER tester uses an adjustable phase shifter and a differentiator.
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design
ideas
age currents and trigger-current requirements that it can run the motor on 10 nA
of current if you use a low-leakage energy-storage capacitor. Transistors Q1 and
Q2 form a regenerative pair similar to a
thyristor. The 1N4007 diodes take the
place of pullup and pulldown resistors,
and the diodes bypass the leakage current
of the transistors and LED.
As the C1s charge approaches 1.75V,
the green LED starts to conduct, causing
Q1 to turn on and feed current to the base
of Q2. The amplified base current appears
as a disturbance at the collector of Q2.
The emitter-base drop of output transistor Q4 isolates the collector of Q2 from the
output transistor, and the emitter-basedrop of Q3 and the 10-nF capacitor, C2,
isolate Q2 from the dc bias at the base of
because of the voltage loss in the emitter-collector junctions of Q1 and Q3. The
100 resistor and the reverse charge on
C2 drive Q1 into cutoff and another energy-storage-capacitor charging cycle begins. Substitute a blue LED for the green
one or add diodes in series with the LED
to increase circuit-firing voltage beyond
1.75V. You can use 10-M resistors in
place of 1N4007 diodes to improve noise
immunity if you dont need less-than-1A operation. Capacitors become leaky
if you leave them in storage. You may
need to condition such capacitors by applying a 9V battery to the capacitor for a
few days. Use two solar panels in series
to provide enough voltage for very-lowlight operation.
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design
ideas
1
ssume that a design requires posiD1
10 H
VOUT
tive voltage, but only a negative-volt5V
C1
age power source is available. Using
R4
C2
10 F
1k
47
F
1 PGND
a standard boost-converter IC in the cirLX 10
R2
cuit of Figure 1, you can efficient37.5k
C4
Figure 1
ly generate a positive voltage from
2 SGND
VDD 9
0.1 F
Q2
Q1
a negative source. The boost converter
R3
100k
EL7515
generates an output voltage thats higher
FB 8
3 RT
VIN
C3
than the input voltage. Because the outR5
R1
2 TO 12V
20 nF
10k
40k
put voltage5V in this exampleis
SS
EN
4
7
higher than the negative-input-voltage
ground level, the circuit does not violate
LBO 6
5 LBI
the boost-converter principle. The circuit
in Figure 1 uses the EL7515, a standard
boost converter. The ground pins of the By using its ground terminals as the negative-voltage input, a boost converter can efficiently generconverter IC connect to a negative-volt- ate a positive output voltage.
age input source. Ground becomes the
positive input source. VOUT is as follows: with the nominal input-voltage applied. boost converters internal power FET
VOUTVFB(R2/R1)1.33V (37.5k/ Figure 2 shows the line-regulation re- drain-to-source breakdown voltage
10k)5V. The Q1 and Q2 pnp transis- sults. The maximum output-to-input (VDS). For the EL7515, the maximum VDS
tors form a translator that scales the 5V voltage difference must be within the is 18V. For the 5V output, the minimum
(most negative) input voltage is
output voltage (referred to
5.1
12V. A 1V safety margin comground) to a feedback voltage
5.08
pensates for the D1 diode drop
referred to the negative input.
5.06
and any voltage spikes on the
The transistor pair also elimi5.04
5.02
drain of the power FET. Figure 3
nates temperature-change and
VOUT
5
shows the load-regulation test revoltage-drop effects.As the neg(V) 4.98
sults. The maximum output curative input voltage decreases, Q2
4.96
runs at an increasingly higher
rent is a function of the input-to4.94
4.92
current than Q1, causing addioutput voltage ratio and cur4.9
tional transistor-offset misrent-limit setting of the boost
14
0
8
12
6
4
2
10
match.
converter. As Figure 4 shows, the
VIN (V)
Figure 2
For optimal line regulacircuit yields greater than 80% eftion, you should set Q1 and Q2 The line regulation is within 40 mV over the full range of
ficiency at 200-mA output.
to operate at the same currents negative inputs.
4.98
4.975
4.97
VOUT 4.965
(V)
4.96
4.955
4.95
0
50
100
Figure 3
150
200
250
300
Iout (mA)
350
400
82
81
80
79
78
77
EFFICIENCY
76
(%)
75
74
73
72
71
Figure 4
50
100
150
200
250
300
350
400
IOUT (mA)
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R4*
2k
X GAIN
12V
2
V2
CCW 2.5k CW
IC2B
20
X
OUT
10V
4
0.1 F
6
V1
IN
X
IC2A
R11*
200
R8*
825
X.5
ADJ
R9*
500
470k
R10*
402
R7
R3*
1k
12V
R5*
150k
0.1 F
12V
R1*
4990
3600
R2*
100
C1
1 F
X AND Y 5V
OFFSET
2
1
V3
IC1A 3
CCW
X10
ADJ
2k
IC1B
1 F
Y GAIN
Figure 1
8
5
825*
470k
500
IC3A
3
R10*
402
0.1 F
VR2
13
4990*
LED
3600
12V
CCW 2.5k CW
12V
CW
5V
1k*
CCW
20k
R6
20k
CW
12
14
100*
IN
Y
VR1=VR2=
LM4040 5
12V
VR1
R11*
200
IC3B
1
12V
4
0.1 F
R5*
150k
12V
2k*
20
100 F
16V
Y
OUT
10V
12V
7824 OFF
0
1
0
+
20k
10k
100 F
35V
0.01 F
4
NOTES:
IC1=LM324.
IC2, IC3=LT1364.
FOR 0.1-F BYPASSES
ON LT1364 SUPPLIES, USE
SEVERAL IN PARALLEL.
*=1% TOLERANCE.
6
5
100 F
16V
ON
2N4401
DC
INPUT
24V
0.4A
IC1C
11
2N4403
62
1W
20k
12V
In this circuit, positive feedback makes it possible to obtain wide-range dc offset without compromising bandwidth.
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POSITIVE
VIN
VIN
Figure 2
V+
SHDN
OVP
VL
NEGATIVE
VOUT
IN
VL
VCC
Figure 3
EXT
MAX1846
MAX1847
CC
DH
BST
COMP
LX
CS
MAX1636
DL
FREQ
SKIP
PGND
PGND
SYNC
REF
CSH
FB
GND
GND
REF
CSL
FB
RESET
TO MICROPROCESSOR
GND
small penalty on maximum output current.) Input and output ripple voltages
directly relate to the input and output capacitors ESR (equivalent series resistance), so you should carefully select these
capacitors. Circuit layout is also extremely important, as for all dc/dc converters. You may want to consider the
MAX1636 evaluation kit from Maxim
design
ideas
and shunts the solar array when the battery voltage exceeds 14.8V and thus protects the battery from overcharging. Q2
turns off when the battery voltage drops
below 12.5V and thus enables battery
charging. D2 is a reverse-blocking diode.
It prevents the discharge of the battery
through the solar cells when the cells are
not generating electricity. Amber LED2
indicates that the battery is in full-charge
SOLAR BATTERY
D1 IN4007
R1
100k
2 _
IC1
LM385
2.5V
R9
100k
LED1
RED
R4
10k
C1
10 F
25V
R8
3.3k
R6
1k
R2
100k
VREG
R12
470k
7
Q2
MJE
3055
R13
1k
L1
V1
+ BATTERY
SOLAR
PANEL
12V
10W
12V
7 AHR
L2
T1
LM324
S1B
IC2
BATTERY
R18
180k
+
13 _
IC2C
D3
IN4007
FUSE
1A
12
R20
14 1k
C2
1000 F
25V
R22
100k
D21
D22
A
+ C8
100 F
25V
R28
1k
D4
IN4007
10
R26
1k
15
13
12
R25
6.7k
11
7
6
4
16
5 3 1 2 89
R23
10
R24
100k
Q4
D23 IRFZ44
C7
1 nF
1 kV
RELAY
CONTACTS
V1
D24
D6
IN6007
C10
1000 F
25V
R33
330
C11
1 F
LAMP
CFL
7W/
FOUR
PIN
D5
IN4007
IC3
13
SG3524
C9
10 nF
12V
500 mW
R32
C5
C6
10 F 6.8 F
2kV
2kV
Q3
IRFZ44
C4
0.47 F
E
V1
R21
10
R19
180k
C3
0.47 F
LED3
GREEN
Figure 1
IN5408
D2
LED2
AMBER
VREF
SOLAR BATTERY
R17
180k
IC2B
Q1
BC557
R5
470k
R16
100
6 _
11
R3
26k
R15
180k
R10
2.2k
R7
1 S1A 3.3k
IC2A
3 +
R11
10k
R14
5
5W
R29
820
R30
33k
R31
1k
RELAY
12V
Q5
BC547
R27
1k
NC
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74HC14
2.8V
5
74HC14
0V
2.8V
2
74HC14
OUTPUT
GROUND
11
13
74HC14
10
74HC14
7
3V DC
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VDD
VDD
Data-acquisition system
uses fault protection ......................................69
OUTPUT CLAMPED
AT VDD1.5V
VDDVTN
13.5V
POSITIVE
OVERVOLTAGE
(20V)
NMOS
NMOS
Figure 3
PMOS
VDD
15V
NONSATURATED
VSS
15V
NONSATURATED
VDD
15V
The voltages and MOSFET states appear like this during a positive-overvoltage event.
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ideas
RL
VCLAMP
ADG439F
ADG466
ADC
SENSOR 1
SENSOR 1
DSP
IN AMP
ADC
SENSOR 4
ANALOG OUT
TO ACTUATOR
DAC
IN AMP
REFERENCE
Figure 5
Figure 6
In this circuit, the ADG466 channel protector guards the sensitive inputs of an instrumentation amplifier from a sensor fault.
DSP
ANALOG OUT
TO ACTUATOR
DAC
REFERENCE
100 MHz
1 GHz
10 GHz
POWER
0.801 F
TOTAL
470 nF
1 nF
10 nF
100 nF
220 nF
GROUND
Figure 1
A typical decoupling configuration uses several
multilayer-ceramic capacitors connected in
parallel.
POWER
A
with a vector-network analyzer, you can
identify each capacitors SRF (self-resG1
G2
400 nF
onant frequency). Figure 2 is a plot of
(801 nF TOTAL)
each capacitors SRF, as well as the SRF
B
of the overall parallel connection. Each
RETURN
SRF can cause antiresonance in the parallel decoupling configuration. The
Figure 3
antiresonance occurs when one capacitor is still capacitive, while another A 400-nF X2Y capacitor yields a total decoupling capacitance of 800 nF.
has become inductive.
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ideas
A way to considerably reduce the antiresonance effects is to use a single 400nF X2Y capacitor for decoupling. (Capacitors using X2Y technology are
available, for example, from Johanson
Dielectrics (www.johansondielectrics.
com). You measure the capacitance rating for an X2Y component
Figure
from line to ground; in other words, from an A or a B terminal to
either of the G1 or G2 terminals in Figure 3. So, the total capacitance a 400-nF
X2Y component supplies, connected as
in Figure 3 would be double the capacitance rating, or 800 nF. Figure 4 shows
that a single X2Y capacitor with the
same total capacitance as in Figure 1
provides the same broadband decou-
10
0
10
20
30
VOLTAGE
(dBV) 40
50
60
70
80
10 kHz
10 kHz
1 MHz
10 MHz
100 MHz
1 GHz
10 GHz
BOARD S21
pling as the standard decoupling configuration but without the antiresonance effects. In addition, because X2Y
components come in the same package
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ideas
Celsius-to-digital thermometer
works with remote sensor
Elana Lian and Chau Tran, Analog Devices, Wilmington, MA
ou can use a singlecombination of R1 and R2
develops a 1V drop, and
supply system to preR1
you adjust R2 to provide a
cisely measure the
RF
2k
R3
nominal
current of 353.15
temperature at a remote
50k
50k
R2
A.
Thus,
the current
location with less than
V
DD
1k
through the feedback re1C error over a 0 to
_
DIGITALOUT
IC1
sistor, RF, varies from 80
100C range (Figure 1).
VIN AD7476
DATA
AD8541
to 20 A as the temperThe circuit includes T1, a
OUTPUT
+
low-cost AD590 temperaature varies from 0 to
GND
LONG
ture sensor; IC1, an
100C. The voltage across
R4
WIRES
200k
AD8541 rail-to-rail amthis resistor varies from
plifier; four resistors; a
4 to 1V. The 4V offset
trimming potentiometer;
causes the output voltage
T1
+
and an ADC. You can
of the amplifier to vary
AD590
omit the ADC if you need
from 0 to 5V.
an analog output. You
To guarantee the accuFigure 1
could replace the trimracy of 1C throughout
This system precisely measures temperature at a remote
ming potentiometer with location, with less than 1C error over a 0 to 100C range.
the range, you need to peran AD8400 or AD5273
form a calibration procedigital potentiometer for easier calibra- low-power, rail-to-rail operational am- dure. At a known temperature, such as
tion. The feedback resistor, RF, should be plifier. It has a high common-mode volt- 25C, adjust trimming potentiometer R2
a precision resistor to minimize the scale- age range and extremely low bias cur- to obtain the desired voltage at the outfactor error, but the accuracy of the re- rents. You can calibrate out its 1-mV put of the amplifier, 1.250V, or the demaining resistors is not critical. You can typical offset, the resistor, and AD590 er- sired code at the output of the ADC,
choose the grade of the AD590 sensor to rors. The output swing of the amplifier 400H. Once you perform the calibration,
achieve the required accuracy.
is 25 mV to 4.965V with a single 5V pow- you can calculate the temperature in CelThe AD590 provides an output current er supply, limiting the output by about sius at any measured point inside the
range by multiplying the output voltage
proportional to absolute temperature (1 0.5C on either end.
A/K). In this application, the circuit offThis circuit can derive its power from by 20. Because the sensor has a current
sets and scales the output to provide a a single 5V power supply. The output of output, it is immune to voltage-noise
full-scale range of 0 to 5V with a scale fac- the AD590 varies from 273.15 to 373.15 pickup and voltage drops in the signal
tor of 50 mV/C over the chosen tem- A as the temperature varies from 0 to leads; you can thus use it at a remote loperature range of 0Cthe freezing 100C. The positive input of the AD8541 cation. You should use a twisted-pair or
point of waterto 100C, the boiling has an offset of 4V to provide sufficient shielded cable.
point of water. The AD8541 is a low-cost, headroom for the AD590. The series
design
ideas
VCC
C4
R4
D3
D6
R5
10k
ZD1
4.7V
D4
ZD3
15V
1
C1
1 F
14
14
Q2
12
13
11
Q5
2369
D1
Q3
R16
10
7 4093
R2
4.7k
VOUT
Q1
8
3
R6
8.2k
2222
D2
5
6
C3
C7
D5
C5
33 F
C2
100 F
R3
R1
22k
2907
R15
4.7k
100
Q4
2369
R13
OC1
1k
C6
47 pF
R9
1k
R17
R7
R8
4N35
R12
470k
R10
470
C9
1 nF
C10
R11
ZD2
TL431
C8
R14
Figure 1
Using a simple CMOS IC, this flyback power-supply circuit exhibits extremely low noise.
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design
ideas
charge slowly, further reducing switching noise. The circuit around Q4 is optional; you can use it in most power supplies. It kills the current glitch when Q3
turns on. It is more effective than the
usual RC circuit, and it allows a low duty
cycle at low loads. Note that many of the
component values in Figure 1 are undesignated; you should determine these
values to fit the application.
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design
ideas
S
1A
LM317, configured as a
DVM on a millivolt range.
Q1
constant-current source,
The DVM reads a voltage
BD636
S1B
delivers an output voltage
that is proportional to the
IC1
VIN
V
LM317 OUT
equal to the inresistance under test. If you
Figure 1
VADJ
put if the output
calibrate the circuit as sugP1
P2
resistance is too high. Begested, then the reading is
100
10
cause I wanted to use a
10/V on the 100-mA
9V
R1
R2
bench supply or a 9V batrange and 100/V on the
+
+
BATTERY
68
6.8
3V
tery, the voltage would fry
10-mA range.
OR BENCH
BATTERY
SUPPLY
any 3.3V logic on the
To track down pc-board
board. Ideally, I wanted
short circuits, attach the
voltage to be limited to
unit with test points A and
A
1.5V. So, I came up with the
B across the suspected
configuration in Figure 1.
shorted signals. Attach one
B
IC1 controls the base of
DVM probe to test point A
the npn Darlington transis- Make your own milliohmmeter, using a voltage-regulator IC and some resistors.
and use the other to
tor, Q1. The IC regulates the
probe the circuit. Convoltage across the selected resistor to form tween test points A and B and measuring stant voltage along a trace indicates that
the constant-current source. The current the voltage across the resistor using a no current is flowing and that the trace is
source delivers either 10 or 100 mA, de- DVM (digital voltmeter). I used 5 and not the source of the short circuit. Look
pending on which emitter resistor is in the 10 and set one S2 position for 10 mA for high readings on the trace with the
circuit. The purpose of S1 is to give longer and the other for 100 mA. To measure a low reading and low readings on the trace
battery life. You can calibrate the current small resistance, you attach test points A with the high reading, to locate the
source by strapping a resistive load be- and B across the resistance. You set the source of the short circuit.
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3V
5.5
IN
5.1
changes with output current. You can
5VIN
greatly improve the cross-load regulation
10VIN
by adding a 10- to 20-mA preload at each
5.3
NEGATIVE 4.9
NEGATIVE
5V
output. The preload ensures that the
5V
OUTPUT
OUTPUT
(V)
dc/dc converter operates in continuous(V)
3VIN
5.1
4.7
conduction mode, in which the inductor
5VIN
current is stable enough to provide con10VIN
stant current. Figure 3 shows the 5V
4.9
4.5
0
200
400
600
800
output voltage regulation under different
0
200
400
600
800
POSITIVE
5V
OUTPUT
CURRENT
(mA)
(a)
NEGATIVE 5V OUTPUT CURRENT (mA)
load conditions at the positive (Figure
(b)
3a) and negative (Figure 3b) outFigure 3
puts. In this case, to improve crossload regulation, both the outputs connect These curves show the regulation of the 5V supply as a function of the 5V output current (a), and
the regulation of the same output as a function of the 5V output current (b).
to a 20-mA preload.
L1
6.8 H
D1
1N4148
D2
1N4148
BATTERY
PACK
C1
10 F
R1
R2
13
1
SW1 VOUT1
14
2
SW2 VOUT2
6
15
VBAT VOUT3
8
SYNC
12
FB
IC
C2
10 F
OUTPUT TO
PROCESSOR
C3
220 F
TPS61032
LBO 10
7 LBI
3
9
PGND1
EN
4
PGND2
11 GND PGND3 5
S1
D3
1N4148
TO PROCESSOR I/O PIN
R3
1k
Figure 1
R4
1M
C4
0.01 F
R5
1M
This circuit configuration provides a momentary power switch with processor supervision.
design
ideas
12V
J1
IN
1
2
Figure 4
peaks at 3 MHz.
and the input to IC7 goes low, thus turning off the MOSFET. Figures 2 and 3
show the control voltage, the voltage
across the transformer secondary, and the
gate voltage of the MOSFET.
The dimensions of the transformer
Figure 3
Figure 5
5V
J3
OUT
GND
C2
100 nF
C1
47 F
CON1
Figure 1
7805
IC1
Figure 2
GND PWR
D5
MUR420
D2
1N4148
CON2
12V
5V
IC2
5
8 V
CC OUT
4
1
GND NC
CLOCK 5V
3
4
5
6
2
10
7
9
16
VCC
A
B
C IC
3
D
JUMPERS
QA
QB
QC
QD
RCC
14
13
12
11
15
10
8
6
4
2
10
8
6
4
2
CLK
ENT
ENP
74LS161A
LOAD
GND CLR
8
1
9
7
5
3
1
9
7
5
3
1
E
3 A
IC4A
F
CD4011A
5
4 2
8 IC5B
J2
1
2
CON2
T1
IC6
CD4041A
C4
0.1 F
IC5A
3 4
D1
1N4148
5
C3
680 pF
CD4011A
C6
C5
330 pF
R1
6.8k
2 TRG
4 RST IC7
3
5
OUT
6 TH
7
IC7
1 IC555
3
MC34151
CON2
6
1 F
2
D3
1N4148
2
1
J4
2
1
Q1
C9
1 nF
IC8
4
5
IRF630
MC34151
3
D4
1N5819
GND PWR
A modulation scheme makes it possible to obtain isolated gate drive for a power MOSFET over a wide duty-cycle range.
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ideas
D1
alignment for the beam sensor.
grate digital control. When
LINE 1
You achieve optimum alignment
logic lines are low, the signal
by centering the light beam in rediodes do not conduct. This
lationship to the active areas of
condition allows the photodieach photodetector. The light
odes to control the circuit. A
R1
PD2
PD1
4.7k
_
beam needs to illuminate half
high level on Line 2 causes
POWER
the photosensitive area of each
current to flow to the sumOP AMP
diode. When sizing the hole,
ming junction and swing the
+
consider the distance beamplifier negative. A high levFigure 3
tween the location of the
el on Line 1 raises the sumR2
D2
light beam and the photodiodes.
ming junction voltage above
R3
4.7k
4.7k
LINE 2
If the beam is too large, the senground and swings the amplisors do not produce any change
fier positive. By selecting a
for a range of positions. Too
resistance value that allows
small a beam produces a nonlin- This circuit imparts digital-interface control to the circuit in Figure 1.
a logic-level supply high
ear transfer function along the
enough to provide at least
center line between the photosensitive light source with higher intensity.
twice the maximum current from each
Figure 3 illustrates how you can use a photodiode, the circuit maintains system
areas. This nonlinearity can create difficulty in selecting the value of CF for nonbipolar signal without digital-to- control regardless of the photodiode
dampening the circuit and requires a analog conversion for systems that inte- signals.
5VIN
8VIN
12VIN
15VIN
400
300
MAXIMUM
VOUT2 LOAD
CURRENT 200
(mA)
100
0
0
VOUT1
12V
VIN
5 TO 15V
L1
CDRH4D28-100
D1
B0530
CCOUP1
VIN
2.2 F
X5R
25V CERAMIC
IC1
LT1961EMS8E
SHDN
90.9k
COUT1
15 nF
L2
CDRH4D28-330
VC
GND
GND
10 F
X5R
16V CERAMIC
10k
6.8k
100 pF
Figure 1
1 F
X5R
25V CERAMIC
CCOUP2
D2
B0530
COUT2
10 F
X5R
16V CERAMIC
L3
CDRH4D28-330
200
300
400
500
VSW
FB
SYNC
100
Figure 2
1 F
X5R
16V CERAMIC
CIN
500
VOUT2
12V
a single boost regulator using a dual-polarity SEPIC (single-ended, primary-inductance-converter) architecture. The
circuit saves space and offers good regulation and current-handling capability.
The boost regulator, IC1, usually figures
in step-up-converter configurations, but
the low-side power switch in IC1 allows
the use of the IC in both SEPIC and negative-SEPIC circuits.
The combination of the two topologies
creates a dual-polarity SEPIC, an excellent source for multiple-rail bias power.
The circuit provides well-regulated
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ideas
12.5
VOUT1 AT 50 mA
VOUT1 AT 100 mA
VOUT1 AT 210 mA
12.3
12.3
12.2
12.2
VOUT2 12.1
(V)
12
VOUT2 12.1
(V)
12
11.9
VOUT2 AT 50 mA
VOUT2 AT 100 mA
VOUT2 AT 210 mA
11.8
11.7
11.6
11.5
85
12.4
12.4
11.9
11.8
11.7
100
200
300
400
Figure 4
75
EFFICIENCY
70
(%)
5VIN VOUT2 AT 140 mA
5VIN VOUT2 AT 50 mA
5VIN VOUT2 AT 215 mA
5VIN VOUT2 AT 50 mA
65
60
comes from VOUT1, VOUT2 maintains excellent regulation (figures 4 and 5). The
VOUT1 LOAD CURRENT (mA)
circuit maintains the regulation as long
as each load draws a minimum of 5-mA
Figure 3
current. The SEPIC topology accommodates input voltages both above and beEfficiency of the circuit in Figure 1 is more than
70% for most of the range of load-current values. low the output voltage. The use of three
55
100
200
300
400
Figure 5
Regulation of the VOUT2 voltage is within 200
mV over almost all of the range of VOUT2 load
currents.
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EI-25-2E6
CORE
1000V
+
110V AC
100k
5W
0.1 F
220 F
400V
T1
70
TURNS
D1
30k
1W
FR137
BR1
+
T3
105
TURNS +
FR137
22 F
25V
T4
SIX
TURNS
470k
1W
47 F
450V
470k
1W
47 F
450V
470k
1W
47 F
450V
470k
1W
22 F
25V
0.1 F
Q1
IRF840
130k
1M
30
1
IC1
UC3844
6
FR137
1k
30O pF
2
4
1k
1M
VREF
3
FB
47 F
450V
T5
FIVE
TURNS
0.1 F
10O pF
T2
105
TURNS +
33k
5
1W
PC817
VR1
500k
200
15k
Figure 1
6.8 nF
R5
3k
0.1 F
2.2 nF
A PWM-controller IC
forms the heart of a
low-cost, regulated,
1-kV-dc supply.
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10k
IC2
TL431
VR2
10k
10k
design
ideas
prevent core saturation, the gap is approximately 1 mm. The primary winding
has 70 turns of 28-gauge wire. Both the
secondary windings have 105 turns of 34gauge wire. The primary and secondary
auxiliary windings have five and six turns,
respectively, of 34-gauge wire. The dc output voltage of the circuit in Figure 1 is 1
kV (fixed).You can adjust the output voltage in a 50V range by adjusting VR1. Both
load and line regulation are less than 1%,
and power efficiency is 80% at full load.
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design
ideas
3
IC2 controllers share a soft-start capaci0.2 mSEC
tor, C14. This example uses two buck con0.50V
verters with integrated synchronous2
0.2 mSEC
rectification FETs. From a 5V
0.50V
input-voltage rail, IC1 generates the 3.3V
I/O voltage. Buck converter IC2 generates the 1.5V output voltage.
The soft-start pin, available on both
controller ICs, serves two purposes. You
can use it to enable the controller cir- 0.2 mSEC
cuitry if requiredan implementation 1 10 mV 50
10 MSAMPLES/SEC
mV DC
you could realize by tying an open-col- 23 50
50 mV DC
2 DC 2.00V
STOPPED
4
0.1V
DC
lector or open-drain gate to the SS Pin.
If the transistor or FET is active, it
Figure 2
ties the SS Pin to ground potential,
forcing both controllers to stay off. Once This graphic shows measurement results for
you release the SS Pin, both ICs start to the ratiometric implementation.
charge C14 with their internal 5-A current sources. In total, 10-A current flows timeC14(1.2V/10 A). As the output acinto C14. Once C14 reaches the threshold tivates, a brief ramp-up at the internal
voltage of 1.2V, both controllers start to soft-start ramp may occur before the exoperate. You can easily calculate the de- ternal soft-start rate takes control. The
lay versus the capacitors value: Delay output then rises at a rate proportional
x
10
x
10
x
10
VIN 5V
L1
C1
470 F
R1
76.8k
C2
10 F
C5
100 nF
C13
56 pF
RT
D1
C6
47 nF
BOOT
C12
1.8 nF
TPS54310
VBIAS
IC1
VSENSE
SYNC
R9
1k
I/O 3.3V, 3A
PH
VIN
SS
C7
47 F
C8
47 F
R7
105
R8
27.4k
R2
3.83k
C10
6.8 nF
COMP
R3
40.2k
R15
10.22k
GND
C9
470 pF
R6
13.7k
Q1
R5
330k
C11
47 F
L2
R4
330k
R10
71.5k
C19
47 nF
PGOOD
VBIAS
C15
100 nF
CORE 1.5V, 6A
PH
BOOT
TPS54610
RT
IC2 SYNC
Figure 1
This circuit provides
ratiometric (delete red
path and components) or
simultaneous power-up
sequencing.
VIN
C20
47 F R
13
33.2
C21
47 F
R14
10k
VSENSE
R11
SS
C18
5.6 nF
C17
18 nF
COMP
R12
14.7k
GND
C14
39 nF
C16
1.5 nF
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design
ideas
to the soft-start capacitor. You can program the soft-start time via C14. The next
equation represents the soft-start time
calculation. The actual soft-start time is
likely to be less than the calculated approximation because of the brief rampup at the internal rate. Soft-start
timeC14(0.7V/10 A). If you set IC1 for
2
5 mSEC
0.50V
3
5 mSEC
0.50V
5ms
1
2
3
4
10 mV 50
50 mV DC
50 mV DC
0.1V DC
500 kSAMPLES/SEC
2 DC 1.02V
STOPPED
Figure 3
These curves, distinctly different from those in
Figure 2, show simultaneous-sequencing
results.
design
ideas
Q2
BD140
VIN
9V DC
BATTERY
VOUT
R3
22k
IC1A
CD4023A
1
2
8
R2
2.2k
3
4
5
IC1B
CD4023A
11
12
13
S1
1
R7
2.2k
IC1C
CD4023A
D1
10
RT
1M
R1
390k
R4
100k
8
VCC
R5
100k
2
4
5
6
7
ON/OFF
MOMENTARY
C1
100 nF
Figure 1
CT
330 F
C2
1 nF
C3
10 nF
C4
10 nF
C5
10 nF
This battery-saving circuit is handy for applications requiring a limited operating time.
TO
APPLICATION
R9
100k
C6
1 F
TRIGGER
OUTPUT
RESET
IC2
CONTROL
THRESHOLD
DISCHARGE
GND
1
R6
10k
LED
Q1
BC337
555
ON
OFF
OFF
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microcontroller you select has a builtin A/D converter, response time can decrease by a couple of orders of magnitude with the elimination of the input-filtering network. Op-amp selec-
tion is important if you use a singlesupply topology. An operational amplifier that can maintain stability close to
its negative, or ground, rail is an important asset.
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design
ideas
M1
FDS7788
RS
0.006
12VIN
R1
100
D1
5.1V
C2
100 nF
12VOUT
R3
1k
Q1B
R2
100
Q1A
FFB2227A
360 mV
Figure 5
Figure 4
IN
ON
This hot-swap
controller has
fast limiting of
short-circuitcurrent peaks.
CSPD
SENSE
GATE
MAX4272ESA
GND
NC
STAT
POR
CTIM
C1
22 nF
but at diminished amplitudes. The simple circuit in Figure 1 makes the switching converter operate over multiple frequencies rather than one, thereby
reducing the time average at any one frequency. This scheme effectively lowers
the peak emissions.
The circuit in Figure 1 is a self-starting
oscillator with an oscillation frequency of
approximately 500 Hz. When you apply
power, C3 begins to charge up from 0V,
and the output of the TL331 comparator
is in a high-impedance state because its
noninverting input sees a higher voltage
than that of the inverting input. As C3
charges, its voltage crosses the voltage reference of the R1-R6 divider, and the com-
design
ideas
5V BIAS
C1
0.1 F
R3
10k
5
4
TL331DBV
R1
10k
R2
49.9k
1
IC1
C2
1 F
RT
13.7k
R4
24.9k
IC1
UCC3813
1
2
COMP
REF
FB
VCC
8
7
3
6
Capacitor C2 ac-couples the ramp
2
R5
CS
OUT
4
5
6.04k
voltage of C3 into the UCC3813s oscilRC
GND
lator pin. The injected signal adds to the
CT
C3
R6
330 pF
4.99k
0.1 F
charging current of CT during its positive portion (ac signal), thus increasing
the controllers operating frequency.
During the injected signals
Figure 1
negative portion, some of CTs
A low-frequency oscillator ramp, injected into the RC pin, modulates the supplys switchcharging current disappears, slowing ing frequency.
the controllers operating frequency.
Figure 2 shows the effects of the inject- the frequency-sweep rate.
the circuit below the power converters
The differential EMI-current measure- low-frequency limits, or saturation of
ed signal on the charging of CT. R4 controls the magnitude of the current that ment of Figure 3 (1 dBV1 dBA) magnetics may occur. This circuit demonis injected. Reducing R4s value increas- shows the before-and-after effects of strates a low-cost, small-area approach to
es the range, or spread, of the operat- adding the frequency-shifting oscillator. reducing conducted-EMI emissions.
ing frequency around its nominal fixed This design easily achieves a 10frequency. The injected signals oscilla- dBA reduction with a 12-kHz
tion frequency, which C3 sets, controls sweep window. A wider window further reduces EMI, but
1
1 SEC
the modulator frequency may
0.50V
be noticeable in the converters
10115 SWPS
output ripple voltage. It is also
desirable to make the injected
ramp voltage as linear in shape
as possible to prevent the
switching converter from
1 SEC BWL
spending excess time at its
1 50 mV DC
2 50 mV DC
switching-frequency limits. The
200 mSAMPLES/SEC
3 0.1V DC
STOPPED
nonlinearity can result in an
1 DC 1.39V
4 0.5V DC
EMI response with two
Figure 2
Figure 3
distinct frequencies. You
The external oscillator varies
The EMI of the flyback converter
must take care not to operate differs with and without external modulation.
the charging of the timing capacitor.
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design
ideas
of 65V. In this case, VIN14V (nominal),
so you need VOUT to be 24V (nominal).
First, calculate a value for R2, thus establishing the reference current. If you select
a reference current of 1 mA, you obtain
ditions. The circuit maintains a 10V difference between VIN and VOUT, but you
can easily change it to provide other voltages. The PWM circuit in Figure 1 is the
CS5171 from On Semiconductor (www.
onsemi.com), but you can use the idea
with any boost circuit. The current-mirror circuit, comprising the dual-pnp
transistor, Q1, and the associated resistors, establishes a current that depends on
the voltage difference between VIN and
VOUT. The dual-pnp transistor has a VCEO
VIN
IN
+
C1
MAIN
C3
SWIN
SDIG
REF
C5
MAX1552
C8
COR1
C4
ON
SDIG
ENSD
OFF
1.8V
20 mA
COR2
ENC2
OFF
voltage, VCONT:
C6
ON
COR2
LED driver (Figure 3). The circuit comprises simply the PWM source, capacitor
C, and resistors RD and RW. For CMOS
circuits, you calculate the open-circuit
output voltage as VCONTDVDD, where
VCONT is the control circuits output voltage, D is the PWM duty cycle, and VDD is
the logic-supply voltage. The control circuits output impedance is the sum
3.3V
300 mA
of the resistor values
RD and RW: RCONT
RDRW. For the cir3.3V
200 mA
cuit of Figure 1, the
output
voltage,
1.5V
VOUT, is a function
200 mA
of the PWM average
SW
LCD
ON
ENLCD
RESET
OUTPUT
LOW-BATTERY
OUTPUT
LCD
20V
1 mA
D1
MAIN
R3
RSENSE
C9
L1
OFF
C7
LFB
LBO
GND
R1
ADJ
C2
DIGITAL
ADJUST
3
CTRL
R2
Figure 2
RD
Figure 1
This simple circuit provides positive-output voltage LCD drive.
VOUT
DLOW
GND
RFB
CCOMP
RW
0
ON/OFF
4
CONNECTION FOR
PWM-CONTROLLED
LCD BIAS
VDD
DHI
MAX749
FB
FROM
PROCESSOR
PWM OUTPUT
CS 8
V
LX
R4
RS
0.1 F
CONNECTION FOR
PWM-CONTROLLED
LCD BIAS
VDD
RW
FROM
PROCESSOR
PWM OUTPUT
0
RD
design
ideas
1 F
1 F
C1F C1N
C2P
C2N
VIN
2.7 TO 5.5V
OUT
1/1.5
REGULATING CHARGE PUMP
4.7 F
1 F
MAXIM
MAX1570
LED1
EN1
ON/OFF
AND
DIMMING
EN2
REFERENCE
AND
CONTROL
SET
LED2
LOW-DROPOUT
CURRENT
REGULATORS
LED3
LED4
LED5
RSET
GND
PGND
CONNECTION FOR
PWM-CONTROLLED
LCD BIAS
VDD
RW
FROM
PROCESSOR
PWM OUTPUT
0
RD
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design
ideas
C4
100 pF
R2
22k
C3
22 F
+
D4
BYV28-50
Q1
2N2907A
R3
1M
R4
22
D5
UF5406
Q2
IRFP450
D6
BYV28-50
OUTPUT
D7
1N4148
PWM
R5
22
Q3
IRFP450
D8
UF5406
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design
ideas
12V
base-emitter junction of Q1.
inverter with 150% overload caIn the turn-on of Q2, the folpacity. If you change the MOSlowing scenario occurs: When
FET, the value of C4 has to change
1k
the control input, PWM,
according to the total gate charge
2N2222A
Figure 2
goes low, Q3 quickly turns
plus the output capacitance of Q3,
off, thanks to D7. A displacement
which is much lower and, in fact,
2.2 nF 300
negligible. Q1 amplifies the cacurrent, C4dV/dt, flows
OUTPUT
through C4 to the base of Q1. Q1
pacitor current, so C4 is propor1N4148
charges the output capacitance
tional to QG2hFE1. Make C4s valINPUT
of Q3 and the gate capacitance of
ue no higher than necessary,
2.2k
2N2222A
Q2, and Q2 turns on. C3 supplies
because the base current in Q1
560
would be too high. To obtain all
the collector current. If the pethe speed advantages of the cirriod is long, Q1 keeps conducting and compensating the leakcuit, the PWM signal should be
age of Q3. If D6 were a Schottky This buffer enhances speed at the PWM input of Figure
able to quickly drive Q3. If necesdiode, which is leaky, you would 1s circuit.
sary, you can use a buffer circuit
have to reduce the value of R1. A
(Figure 2). You can drive the cirshort cross-conduction period exists be- current spikes. The inductor needs a cuit with a single CMOS gate. The circuit
tween the two MOSFETs, a phenomenon snubber comprising D1, R1, and C2. Note in Figure 1 is probably the simplest highthat is more apparent when Q3 turns off that the inductor value is conservative voltage inverter you can design. It has
and Q2 turns on. A small inductor, L1, in and can be smaller.
served in thousands of three-phase moseries with the main supply limits the
The values are for a 370W, three-phase tor drives from 0.37 to 0.75 kW.
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floating gate when the circuit is connected to the AD7790 differential-input sigma-delta ADC. The gate voltage connects
directly to the ADCs reference. The only
signal-conditioning circuitry required
between VS or VG and the ADCs input is
a simple RC filter. The 0.1% error in re-
VCC
time to stabilize before you remove the
reset. The threshold voltage of the
CAT811 microprocessor reset circuit,
VCC
IC2, sets the lower limit of the voltage
CAT811
R
RST
1
range, VLOW. This threshold can be 2.32
MR RST
to 4.63V using standard products. CusCAT431
tom threshold devices with thresholds as
GND
low as 1.8V are also available. The 1.24V
IC2
CAT431L shunt regulator, IC1, and two
100k
R2
IC1
resistors, R1 and R2, set the upper limit,
VHIGH: VHIGHVREF(1R1/R2), where
VREF is the internal reference voltage of
GND
IC1 (VREF1.24V). The maximum
Figure 1
VHIGH that you can set is 5.5V, and
This simple circuit uses a microprocessor superthe maximum supply voltage is 9V.
This design uses the CAT811 super- visor and a shunt regulator to form an overvisor with a threshold voltage of 4.63V voltage/undervoltage-protection circuit.
Figure 2
Figure 3
As the supply voltage rises into range, the reset pin in Figure 1
becomes active low.
As the supply voltage falls into range, the reset pin in Figure 1
becomes active low.
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design
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Figure 4
Figure 5
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design
ideas
30
currents alters their brightness level. R5
sets the maximum LED current:
25
R52150.6/ILED(DESIRED), where ILED is
20
the current through one LED.
ILED
IC1 is a digital potentiometer with a log- (mA) 15
arithmic taper and an analog-voltage
10
wiper. Each wiper tap corresponds to 1 dB
5
of attenuation between H1 and W1 (pins
0
11 and 9). The IC contains two poten0
64
16
32
48
tiometers controlled by a 16-bit code via a
CODE
three-wire serial interface. To set the
Figure 2
LED current, drive RST high and
clock 16 bits into the D terminal of IC1, LED current versus input code changes for the
starting with the LSB. Each pulse at CLK circuit in Figure 1.
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design
ideas
12V
12V
HIGH-IMPEDANCE
BUFFER
12V
Q1
2N5485
D
R3
560
R2
1.2M
D1
1N4148
R7
1.2k
12V
R10
12V 47k
3 _
IC1
LM306
7
1
R11
10M
D2
D3
SD101C SD101C
C1 4
0.1 F
C3
0.1 F
12V
4
5
IC2A
TL084
6 _
R12
11
150
R13
10k
10
C6
3.3 F
R18
1.2k
Figure 1
12V
DC
OUTPUT
R17
100
12V
R15
50k
R21
1.2M
R19
10k
14
12
+
IC2D
TL084
_ 13
C10
0.1 F
C7
0.01 F
C8
2000 pF
R20
1k
C9
0.1 F
R16
2.7k
GAIN
ADJUST
Q2
2N3904
IC2B
TL084
9 _
R14
560k
C5
0.1 F
3
+
IC2C
TL084
_ 2
C4
0.1 F
OFFSET
ADJUST
R9
5k
R8
10k
8
2
R4
560
S
R1
10M
12V
C2
0.1 F
R6
R5
220k 1.2k
AC
INPUT
improves its switching speed and prevents random oscillation when its input
voltage is in its linear range.
This circuit works by essentially creating its own reference for the negative input of the comparator. If the voltage on
the positive input of the comparator is
greater than the voltage at the negative input, the comparators output goes high
and charges capacitor C3 until the voltage
on the capacitor is a few millivolts greater
than the voltage on the positive input.
Then, the comparator stops charging C3
until the cycle repeats. This action ensures that the voltage on holding capacitor C3 is nearly equal to the peak voltage
at the input to the comparator. Schottky
diodes D2 and D3 couple the output to the
holding capacitor, C3. The feedback from
the output of IC2A to the junction of D2
and D3 keeps D3 biased to 0V when it is
off, thereby preventing reverse leakage
through D3 (Reference 2). The feedback
design
ideas
25
2
1.8
2.1
2
50
0.6
0.4
0.4
0.8
100
0.2
0
0.1
0.5
sary. If a precision ac source is not available, you can use an accurate dc source
and a high-impedance voltmeter for calibrating the circuit. Apply 500-mV dc to
the input and adjust R9 for 499 mV at Pin
10 of IC2. Then, apply 4V dc to the input
and adjust R15 for 3.980V output (Pin 8
of IC2). The maximum peak input voltage is approximately 5V, because the
maximum input-voltage specification
for the LM306 is 7V. The accuracy of
the circuit decreases when the input peak
is higher than 4V. Remember to use a
blocking capacitor in series with the input if the signal to be measured includes
a dc offset that can cause the peak input
1000
0
0.1
0.3
0.5
10K
1
0.8
1.0
0.8
100K
0.8
0.7
1.4
0.8
1M
2M
0.5 3.2
1.3 3
0.6 2
0.5 1.8
3M
5.4
5.2
3.8
3.5
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S1
0-FH PULSES
5V
4.7k
R2
4.7k
R3
4.7k
R8
4.7k
R5
4.7k
R7
4.7k
R4
4.7k
R6
4.7k
R9
R2
4.7k
FREQUENCY
INPUT
16 10 6 5 4 3
VCC T D8 D4 D2 D1
2
CLK
P
7
Figure 1
1
CLR
16 10
VCC T
IC3A
IC1
74161
CAR
15
7404
1
LD
9
GND
8
P
7
1
7432
IC4
2
GATE
CLK
design
ideas
this circuit to produce even more pulses or spaces by simply cascading more
counter chips where needed. Also, you
can replace switches S1 and S2 by an 8bit write-output register, making the
pulse and space counts software-controlled, or you could apply the gate signal to the control input of a CMOS
switch to burst analog signals, such as
sine waves at its input.
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Figure 2
2k
SDA
LT1719
74HC125
169
V+
7.5k
V
SHDN
HCPL2300
5V
2k
(0.4V)
(0.4V)
1k
ISOLATED
GROUND
ISOLATED
GROUND
ISOLATED SDA
LT1719
11.5k
11.5k
ISOLATED 5V
5V
Figure 4
V+
7.5k
V
SHDN
169
74HC125
HCPL2300
1k
ISOLATED
GROUND
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design
ideas
imulating the output-offset current of a current mirror is straightforward.You simply have to apply an
input current, measure the output current, and calculate the difference. This
output-offset current, however, is not
equal to the input-offset current, especially when the circuit is not a 1-to-1 mirror. Simulating the input-offset current
with high accuracy is more complicated.
Suppose youre dealing with a 1-to-1 mirror and you want to know what input
current is needed to obtain an output
current of 10 A. Ideally, the input current would be 10 A, assuming that the
input offset current is zero. However, because of the finite beta of bipolar transistors, finite output impedances, mis-
NUMBER OF OCCURRENCES
design
ideas
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design
ideas
comes almost as large as the core, yielding two implications: Because the surrounding vacuum or air contributes as
much as the core itself to the inductance,
you can double the core area the formula uses with respect to the physical value, and, even when saturation does occur, the effect is much less brutal than in
a closed magnetic circuit. Second, the
simplified inductance formula is no
longer valid.
To conclude, the user-friendly versions
of the formulas, expressed in more convenient units are: N0.01(LI)/(BA), with
L in microhenries, I in amperes, B in tesla, and A in square centimeters.
And the user-friendly expression for
the air gap is
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Build a transformerless
12V-to-180V dc/dc converter
Francis Rodes, ENSEIRB/IXL, Talence, France
ome transducers for portable or
CD40106B
D1
D2
automotive applications need accuOUTPUT STAGE
rately regulated, high-voltage bias
and draw little current. To produce such
high voltages from a low battery voltage,
designers typically use switch-mode
Q2
C1
VC1
dc/dc convertersgenerally, flyback conVDD
verters. These converters exhibit high ef12V
COUT
VOUT
ficiency at medium or high output power. However, for the low output power for
biasing some transducers, the fixed
VIN
Q1
VOUT1
amount of power the power-switch
Figure 1
driver and the regulator circuitry require can have a detrimental effect on efficiency. Furthermore, the associated
transformer is rarely available off the
shelf, so it requires a custom-design ef- This four-IC circuit uses no transformers and converts 12V to 180V, using off-the-shelf components.
fort. This effort can account for 70% of
the entire design time.
The two complementary MOSFETs, circuit in Figure 2 acts as a voltage-douThe circuit in Figure 1 overcomes the Q1 and Q2, mounted in a push-pull con- bler cell.
If you cascade N voltage-doubler cells
transformer-related problem, thanks to a figuration, represent the output stage of
transformerless, switched-capacitor top- one CD40106 Schmitt-trigger inverter. in the chainlike structure of Figure 1, an
ology that requires only off-the-shelf The input signal,VIN, drives the push-pull extension of the voltage-doubler princicomponents. You can describe the oper- stage, producing a 0 to 12V square wave ple yields VOUT(N1)(VDDVD). From
ating principles of the circuit by first con- at 150 kHz. If you assume that VIN is 12V this equation, you can determine the
sidering the behavior of a single during the first half-period, then Q1 is on, number, N, of inverters you need to proswitched-capacitor cell and then extend- and Q2 is off. Consequently, D1 is for- duce a given high output voltage:
ing the concept to an N-cell voltage mul- ward-biased, and C1 charges positively to
tiplier. Figure 2 represents the equivalent VC1VDDVD, where VD is D1s forwardcircuit of the first switched-capacitor cell. voltage drop (0.7V). Meanwhile, D2 is
forward-biased, and COUT charges to
To produce 180V output voltage from
VOUTVDD2VD. During the second a 12V lead-acid battery, which can flucBuild a transformerless 12V-to-180V
half-period, the states reverse: VIN is 0V, tuate from 11 to 13.5V, an application of
dc/dc converter ..............................................83
Q1 is off, and Q2 is on, thus connecting the the equation with worst-case VDD of 11V
Build a simple one-chip
negative terminal of C1 to the supply volt- yields
phototimer ......................................................86
age. This action forces the positive terSolenoid trip circuit works
minal of C1 to elevate itself to a voltage
at batterys end of life ..................................88
higher than the supply voltage, VDD. D1
now becomes reverse-biased and allows
So, your design requires three
Servo loop improves
C2 to charge up again through D2. If you CD40106 hex Schmitt-trigger inverters,
linear-regulator efficiency ............................90
assume that COUTs value is considerably as Figure 1 shows. An inspection of the
Boole helps simplify wiring
lower
than the value of C1, then you can equation VOUT(N1)(VDDVD) reand save money ............................................92
calculate that VOUT attains the value veals that the 11 to 13.5V fluctuation of
Publish your Design Idea in EDN. See the
Whats Up section at www.edn.com.
VOUTVOUT1VC12(VDDVD). Thus, the lead-acid battery produces a proporassuming VDDVD, you can see that the tional 195 to 243V output-voltage fluc-
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design
ideas
VBAT
12V
IBAT
C21
1 F
IC4 LP2951
INPUT
FEEDBACK
OUTPUT
+
SENSE
ERROR
AMPLIFIER
60 mV
C22
3.3 F
8
VTAP
ERROR-DETECTION
COMPARATOR
NC SHUTDOWN
NC
NC
ERROR
NC
1.23V REFERENCE
4
GND
D1
R1
33k
D2
D3
D4
D5
D6
C1
C2
C3
C4
C5
C6
IC1A
IC1B
IC1C
IC1D
IC1E
IC1F
D7
D8
D9
D10
D11
D12
C20
100 pF
C7
C8
C9
IC2A
IC2B
IC2C
D13
D14
C13
Figure 2
D15
C14
C10
IC2D
D16
C15
C11
C12
IC2E
IC2F
D17
C16
D18
C17
D19
C18
C19
39 nF
250V
IC3A
IC3B
IC3C
IC3D
IC3E
IC3F
VOUT
180V
R2
10M
IOUT
RL
(LOAD)
H3
10k
P3
100k
NOTES:
C1 TO C18: 33 TO 100 nF (63V).
D1 TO D19: 1N4148 OR EQUIVALENT.
IC1 TO IC3: CD 40106B.
IC4: LP2951 (NATIONAL SEMICONDUCTOR).
This circuit illustrates the operating principle of the basic voltage-doubler cell.
design
ideas
TABLE 2OUTPUT REGULATION AND EFFICIENCY AT VBAT12V
VOUT (V)
180.3
180.3
180.3
180.3
IOUT (mA)
0
200
400
800
1000
VOUT (V)
180.3
180.6
180.7
180.2
179
IC4s error amplifier via the resistive divider, R2, R3, and P3. IC1A, the first multiplier cell, produces the square waveform
that the 18-cell, switched-capacitor voltage multiplier needs. Using the feedback
network (R1, C1), this Schmitt-trigger inverter constitutes a free-running oscillator that produces a 150-kHz square
waveform at its output. Tables 1 and 2
show the measured electrical characteristics of the regulated 12-to-180V dc/dc
IBAT (mA)
3.4
7.6
11.7
19.8
25
Efficiency (%)
NA
40
52
61
60
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design
ideas
prevented the supply voltage from sagging so dramatically, allowing the device
to continue functioning much further
into the batterys life. However, the electrolytic was bulky and expensive, and presented an awkward packaging problem.
The circuit in Figure1 solves the problem by incorporating feedback in such a
way that any drop in supply voltage only
turns on the drive circuit harder. In testing, this circuit functioned even when the
nominally 6V battery sags as low as 2V.
Q1 is a 3A, high-beta, low-saturationvoltage pnp transistor that drives the solenoid. To energize the solenoid, Q1 has
to turn on hard to minimize voltage drop
and get the most from the batterys life.
The circuit achieves the full turn-on by
using three sections of an LP339 quad
comparator in parallel. The LP339 is similar to the venerable LM339 but with lower power consumption, making it more
suitable for battery-powered applications. Interestingly enough, it also has
higher output drive. The three parallel
devices provide approximately 200 mA to
R1
R3
C1
1 F
4.7M
R2
270k
Q1
R4
100k
220k
S1
FZT788
+ C
2
10 F
IC2
3
V+
7 +
INPUT
FROM
MOTION
DETECTOR
D1
BAV99
D2
BAV99
12
5 +
IC1A
3 LP339
9 +
8
V
11
Figure 1
This motion-detector circuit
works with 6V battery voltages that sag as low as 2V.
R5
220k
10
D3
R6
BAV99
680k
1
IC1B
LP339
D4
1N4935
V+
OUT
V
TLE2426
6V
SOLENOID
1
+ C
3
10 F
14
IC1C
LP3
V
+
6V
BATTERY
13
IC1D
LP3
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design
ideas
til it is higher than the negative input. Either case results in the output of IC1As
going high. This action in turn causes the
IC1B, IC1C, and IC1D outputs to turn on,
turning on Q1 and energizing the solenoid. R4 provides positive feedback. If Q1
even starts to turn on, the partial turn-on
causes IC1B, IC1C, and IC1D to turn on
more, precipitating a latch-up to ensure
that Q1 turns on all the way. Thus, all possible battery energy is delivered to the solenoid. C1 provides further positive feedback when the supply sags. D3 protects
the LP339s inputs from being driven
more than a diode drop below ground
when the power-supply sag is severe.
(2)
Equation 2 yields the relationship
VAVOUTVDROPOUTkVFB. You can set
the dropout voltage according to the linear-regulator requirements. If you select
IC1
LM2576T-ADJ
C1
100 F
50V
C2
100 pF
IC2
LT1085
L1
220 H
4
1
IN
FB
2
5
ON/OFF OUT
3
GND
VIN
VA
D2
3.3V
C3
2200 F
50V
D1
SR508
R8
6.8k
C4
100 F
50V
C5
100 nF
5V
4
Figure 1
This inexpensive power supply uses a
preregulator to boost efficiency.
6
IC3
NE5534
R5
33V
3 IN
R4
15k
1%
C6
OUT 2
ADJ
R1
1
100
+
50V
25 F
VOUT
+
R6
15k
1%
C7
150 F
50V
C8
100 nF
R2
2.5k
3
2
R3
10k
1%
R7
510
D3
12V
5V
10k
1%
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design
ideas
Y = AB
X = A+B
Y = AB
Y = AB
Figure 1
X = A+AB
X = A+B
X = A+AB
X = A+B
Figure 2
Figure 3
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maximum VCE rating of 240V. The device in Figure 1 is rated at 300V. VOUT
now equals IOUTR2. (The actual output
current at Q2s collector is slightly less,
because of Q2s base current.) At
0
SWITCHEDCAPACITORFILTER IC
SWITCHEDCAPACITORFILTER IC
20
40
60
GAIN
(dB)
80
BIQUAD
BIQUAD
100
120
0
10
10
0
00
00
00
,0
,0
0,
00
10
0
10
1,
FREQUENCY (Hz)
00
10
0
00
00
00
,0
,0
0,
00
10
0
10
1,
FREQUENCY (Hz)
00
10
0
10
(b)
Noise (a) and low bandwidth (b) plague switched-capacitor filters. The biquad filter
N over the range 20 Hz to 200 kHz.
of Figure 1 maintains less than 1% THD
C3 15V
1 F
Figure 1
C5
1 F
SCLK
CSH
DIN
C7 15V
1 F
C6
1 F
10
6
VCC VDD
7
H
1
SCLK
8
3
CS IC W
3
2
9
DIN
L
C11 VSS
1 F 5
15V
VIN
15V
R1
1k
C1
1000 pF
GND
4 MAX5438
R3
1k
15V C12
1 F
2
3 +
1
7
IC4
4
6
8
MAX437
5V
6
10
VDD VCC
7
1
H
SCLK
3
8 W
IC1 CS
2
9
DIN
L
GND VSS
4
5
5V
15V
SCLK
CSO
DIN
C2
1000 pF
15V
6
8
MAX437
IC5
+ C20
47 F
16V
15V
C16
1 F
3 +
1
C13
1 F
MAX5438
C10
1 F
R6
10k
15V
R5
10k
GND VSS
4
5
SCLK
CSF
DIN
15V
15V
C14
1 F
15V
+ C19
47 F
16V
+ C18
47 F
16V
MAX5438
C9
1 F
15V R
4
330k
1k
C8
1 F
C4
1 F
6
10
VDD VCC
1
H
SCLK
3
8
W IC2 CS
2
9
DIN
L
R2
5V
5V
IC6
6
8
MAX437
C15
1 F
15V
VOUT
C17
1 F
Digital potentiometers adjust the corner frequency, Q, and gain for this biquad analog filter.
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design
ideas
R2
C1
quency 0 in radians per second by adjusting digital potentiometer IC2 via the
SPI interface. In the same fashion, set Q
by adjusting IC1 and gain by adjusting IC3.
Note that adjusting Q does not affect
the corner-frequency setting, and a gain
adjustment does not affect the settings of
Q or the corner frequency. The three
equations below demonstrate this orthogonal tuning for the biquad filter:
R1
INPUT
R3
C2
R6
R4
R5
+
+
BP
LP
R10
R7
R8
NOTES:
AP=ALLPASS.
BP=BANDPASS.
BS=BANDSTOP.
HP=HIGHPASS.
LP=LOWPASS.
R9
BS
AP
HP
Figure 3
The standard biquad filter circuit produces lowpass and bandpass responses,
and the addition of a fourth op amp produces a highpass response. Removing R10 and adjusting
various component values produce a notch or bandstop response or an allpass response.
where RIC1, RIC2, and RIC3 are the input resistances of IC1, IC2, and IC3, respectively. The circuit in Figure 1 is substantially
more complex than the switched-capacitor approach usually integrated into an
IC, but the switching noise and low bandwidth of a switched-capacitor filter are
unacceptable in many applications (Figure 2). A biquad filter offers better frequency and noise performance in ex-
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design
ideas
VOUT
IC1
78L12
IC2
78L12
D1
IC20
78L12
D2
D20
VOUT
C20
RL
cuit that looks a little like a buck regulator and uses a buck controller but is actually a voltage-mode, synchronous flyback circuit. The application it targets
needs 3.3V at 2A with an efficiency requirement of greater than 85% and an
input-voltage range of 36 to 60V. This
one appeared the most promising of several evaluated technologies because of efficiency and cost advantages over buck
and asynchronous-flyback approaches.
The LM2743 controller derives its
power after start-up from the MMBTA06
Figure 1
1N4148
10
4
MMBTA06
1k
1N4148
1 F
100 nF
NS=1
5
49.9k
PA0791
LP
NP=3
50 H
100k
6.2V
1 F
1k
3010
V PGD
9 10
NS=1
6 7
ISEN
PWGD
5
V5
SGND
PGND
LG
1
BOOT
RSNP
100
LM2743MTC
ON=1.08V
EAO
SS
FB
FREQ
10
11
Si4850
EN
12
PGND
13
RSNS
20
LOUT
HG
14
330 nH
1813
CSNS
470 pF
0.1 F
Si4848
150k
120 pF
CSNP
100 pF
10 F
6V
VOUT
3.3V, 2A
300k
10k
470 F
4V
1k
0.1 F
3k
4.53k
This synchronous flyback circuit provides high efficiency with wide input/output ratios.
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design
ideas
5
0.90
cost unit that provides 50 H of primary
inductance and a 3-to-1 turns ratio in a
13L15W11H-mm footprint. Its 34
0.80
to-1 turns ratio prevents the primary
switch from seeing full output current,
3
0.70
v60
resulting in less switching loss than that
v48
x
x
v30
of a buck regulator. The small LC filter at
WATTS
EFFICIENCY
x
x LOSS60
x
x
the output allows a single 10-F ceramx LOSS48
2
0.60
LOSS30
x
x
ic capacitor to handle the high rms ripple current, and a low-cost aluminum
x
x
1
0.50
capacitor also removes ripple and buffers
x
x
x
load transients.
x
x
Figure 2 plots measured data at three
0
0.40
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
input voltages and several output curIOUT (A)
rents for the circuit in Figure 1. EfF
i
g
u
r
e
2
ficiency is displayed on the left for
The circuit in Figure 1 provides more than 85% efficiency
the three uppermost curves, and the three over a wide range of output currents.
lower curves show total loss in watts
measured by the scale on the right. VOUT is important. You obtain best perform- nous flyback circuit applies to a wider
ripple measured 6 mV p-p at no load, ris- ance with four or more layers, separate power range; you can easily extend it to
ing to 20 mV p-p at 4A. The rapid fall in power and ground planes, and short and multiple outputs by adding secondary
efficiency at 3.5A comes from current wide gate-drive connections. Although windings. The additional outputs can use
limiting. As with any switcher and espe- the circuit of Figure 1 targets use in a 7W, either diode rectifiers or additional FETs
cially for flyback designs, pc-board layout single-output requirement, this synchro- driven from the low-gate driver.
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15V
Figure 1
15V
R1
10k
15V
R4
3.9k
R3
3.6k
LM324
VIN
VOUT
R2
10k
Q1
Q2
VOUT (mV)
120
voltage down to the
millivolt level. In
100
Figure 1, Q1, Q2, and
R3 form a 4-mA cur80
rent source that
VOUT (mV)
60
drains the output of
the LM324. R4 is the
40
load, demanding a
sink current of 4
20
mA. This design
0
uses a 2N2222
0
transistor for its
low saturation
voltage. The outFigure 3
put characteristic becomes the
saturation characteristic of the added
transistors, Q1 and Q2. Using this current source, the output voltage is linear down to 22 mV above ground.
Figures 2 and 3 show the output
characteristics. The lowest usable
output voltage depends on the load
(sink) current. When the load current
is 0.5 mA (R430 k), the output
1600
1600
1400
1400
1200
1200
1000
1000
800
600
600
400
400
200
200
0
0
200
400
600
800
1000
1200
1400
20
40
60
80
100
120
VIN (mV)
With 0.5-mA load current, the output voltage is linear down to 4 mV.
1600
VIN (mV)
Figure 2
R4=3.9k.
R4=30k.
500
1000
1500
2000
VIN (mV)
Figure 4
This graphic shows the LM324 transfer function without the
added current source.
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design
ideas
Figure 3
(a)
This photo shows duty cycles of 55.1% (a) and 65.3% (b).
(b)
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ideas
OUT
IN
1M
NO1
NC1
usually prefer or require a regulated
+
IN+
IC
charge pump for cost-sensitive designs
1
MAX981
REFERENCE
that must be intrinsically safe. Off-theCOM1
GND
shelf regulated charge pumps with outC1
IN1
V
10 F
put-current capabilities of at least 10
+
IN2
R5
COM2
mA have typical minimum quiescent
R4
1M
VBATT
VOUT
1M
currents of 50 to 100 A. If that level
of quiescent current is unacceptable,
you can reduce the overall average by
NC2
N02
adding circuitry that remotely moni+ C
2
IC2
12 F
tors the regulated voltage and toggles
MAX4685
the charge pump into and out of
Figure 1
shutdown. That approach, however, may not achieve the desirable qui- This charge-pump circuit uses analog switches to achieve ultralow quiescent current.
escent-current level of less than 10 A.
The advent of low-on-resistance analog
switches and ultralow-current com- energy to a storage capacitor tied to age reference, and a comparator. The
parators and references makes possible VOUT. The transfer capacitor then comparator serves as a voltage monitor
a charge-pump circuit whose maximum charges again, and the cycle repeats. and an oscillator. When the circuit is in
quiescent current is approximately 7 A With ideal analog switches exhibiting regulation, the comparator output is
zero loss, the VOUT level equals two times low, which closes the NC (normally
(Figure 1).
Charge pumps use an ac-coupling VBATT. As expected, however, the analog closed) switches and allows C1 to charge
technique to transfer energy from a switches finite on-resistance produces to VBATT. When the voltage at VOUT dips
transfer capacitor to a storage capacitor. an output level that drops in proportion below the output-regulation threshThe transfer capacitor first charges via to the load current. The basic regulated old3.3V in this casethe comparator
analog switches to the level of VBATT, and charge pump in Figure 1 includes an os- output goes high. The NO (normally
then other analog switches transfer the cillator, several analog switches, a volt- open) switches close, transferring C1s
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8 Check
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LM385
1.235V
10 nF
www.edn.com
100 nF
3.3V
10 F
CLOAD
0520
V1.814
33 F
CLOAD
12 A
2N4401
10 nF
3.3V
150 mA
0520
1/2
LPV358
4
12 A
100k
100 pF
45.3k
1.8V
150 mA
1 F
This configuration boosts the output current of Figure 1s circuit to more than 200 mA.
drive, and not reverse polarity as you apply power. Each op amp has an npn transistor buffering its output to provide
greater than 100 mA. The regulator loops
are stable with these components and
August 19, 2004 | edn 69
design
ideas
51.1
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design
ideas
5V
sic active-channel indication.
The operating principle of this circuit
is based on current steering. A current
sink comprising an n-channel JFET, the
DUAL
SINGLE
TO CHANNEL
BF256C, provides approximately 5-mA
SECTIONS
current draw, which is approximately the
1k
470
hold current of any one of the small-signal SCRs (silicon-controlled rectifiers).
When you select a channel by momentarily depressing the corresponding
switch, the associated SCR turns on,
2N3904 OR
lighting the LED connected to
EQUIVALENT
Figure 2
its cathode and providing a
logic one on the CHANx line. The SCR
automatically latches the selected line until you depress another channel switch. A current mirror replaces the JFET in Figure 1
When you actuate any other channel and allows the choice of single or dual channels.
switch, the corresponding SCR latches,
releasing the previous channel. This latch the use the CHANx line to select an anabehavior is the result of the inability of log switch, a mechanical relay, or anoththe current sink to draw enough current er device. Scalability is straightforward:
to sustain more than one SCR at a time. Additional channel sections require only
The circuit needs blocking diodes to the momentary switch, a 1.5-k resistor,
isolate the cathodes of the SCRs. If you an SCR, and a diode. Because this
use an LED, as in Figure 1, it also doubles method uses a current-based scheme, the
as an active-channel indicator. You can use of long lines is not an issue. Channel
(continued on pg 76)
5V
R2
47k
IC1
PS2701
4
R1
10M
LINEV
R4
2 10
D2
IN4148
D1
IN4148
R5
3.3M
Q2
2N3906
C1
22 nF
FILM
Q1
2N3906
C2
1 nF
R6
10M
R7
10M
Q3
2N3904
R8
10M
RING
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design
ideas
5V
R2
words, it presents approximately 10IC1
47k
M leakage resistance across the line.
PS2701
The basic relaxation oscillator has the
4
3
LINEVP
LED of an optoisolator in the discharge
path of the main capacitor. It delivers a
R1
10M
pulse train, the frequency of which varies
5V
1
2
TIP
R3
with the voltage on the phone line. By
47k
IC2
measuring the period between pulses,
PS2701
4
3
the equipments microcontroller can
LINEVM
easily determine the approximate line
voltage. C1 is the timing capacitor. It
R4
10
should be a film-type capacitor rather
2
1
than ceramic for good results. It slowly
D1
D2
charges through R1, a 10-M reIN4148
IN4148
F
i
g
u
r
e
2
sistor. When the voltage across C1
C1
R5
reaches approximately 3V, the remainder
Q2
22 F
3.3M
2N3906
FILM
of the circuit turns on, causing C1 to rapQ4
idly discharge through R4 and the opQ1
NDS331N
toisolators LED. This action causes the
2N3906
C2
optoisolators output transistor to briefly
1 nF
turn on, creating a low-going pulse approximately 200 sec wide (the signal laR6
Q3
10M
beled LINEV). This width is sufficient
2N3904
for even a slow microcontroller to capR8
R7
ture an interrupt. When C1 discharges to
10M
10M
approximately 1.5V, the circuit turns off,
RING
and the cycle repeats.
Q5
Q2 and Q3 form an SCR (silicon-conNDS331N
trolled-rectifier)-like regenerative pair.
D2 and Q2 function basically as a current This circuit works with either the Tip or the Ring polarity and reports the polarity of the line
mirror. Normally, you construct a cur- to the host microcontroller.
rent mirror using two or more identical
transistors. By using a 1N4148 diode proves the operating characteristics of larity and reports the polarity of the line
to the host microcontroller. This circuit
rather than another 2N3906, you reduce the circuit.
This circuit assumes that Tip and Ring is suitable when you need to know not
the gain of the current mirror to well below unity. The 1N4148 functions as have protection against polarity reversal only the magnitude, but also the polarithough it has many times the base-emit- such that Tip is always more positive. The ty of the line voltage. As you can see, it has
ter diode area of the 2N3906. Reducing circuit of Figure 2 works with either po- two outputs, one for each polarity. Q4
and Q5 are low-threshold nthe gain in this fashion
channel MOSFETs, conhelps the regenerative pair
nected in such a way as to
to turn off at the approprialways connect the bottom
ate point, keeping the oscilrail of the relaxation circuit
lator from sticking on. Q1
and the diode-resistor netto the most negative side
work driving its base func- FREQUENCY
of the timing capacitor.
(Hz)
tion as the trigger circuit.
The positive rail of the reWhen the voltage across C1
laxation circuit connects to
gets high enough, Q1 starts
the most positive side of
to turn on and inject curthe timing capacitor using
rent into Q3. Once Q3 starts
diode isolation, taking adto turn on, regeneration
vantage of the fact that
kicks in, and Q3 and Q2 turn
the optoisolator LEDs are
on hard and stay turned on
diodes.
VOLTS
until the capacitor disFigure 3 shows a plot of
Figure 3
charges sufficiently. C2
the frequency-versus-voltprovides additional positive
age response of the circuit
The frequency-versus-voltage response for the circuit of Figure 2 shows the
feedback through Q1; it imof Figure 2. It shows the
spread across a sampling of five units for both polarities of line voltage.
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design
ideas
VREF
0V
plifier that has none of these deficiencies.
_
The design exploits the fact that the output of an instrumentation am12V
Figure 1
plifier is the difference between
the output pin, VOUT, and the reference The differential-output cirpin, VREF. This application adds an in- cuits having unity gain (a) and
verter with a gain of 1 between the two a gain of two (b) suffer from
2.5V
high noise level, excessive offpins.
set
error
and
drift,
and
signifWith an input voltage, V, the output
voltage (VOUTVREF) must also be equal icant gain error and drift.
to V. The reference pins voltage is opposite in polarity to the output pins voltage. Therefore, the output must produce
12V
VOUTVIN/2 and VREFVIN/2 to satis1V
+
fy (VOUTVREF)V. Applying a 2.5V sig+
VOUT
A
nal to the noninverting terminal of the
AD8221
0V
op amp sets the common-mode output
VREF
_
R5
level. The op amp establishes 2.5V at
10k
Node B. Accordingly, if you apply 1V to
B
12V
the input, 3V appears at Node A,
Figure 2
_
and 2V appears at Node C.
R6
10k
Thus, the output is 0.5V higher than and This differential-output
0.5V lower than 2.5V. Errors from instrumentation amplifier
VOUTVREF are a function only of the in- preserves the gain and adds
12V
C
strumentation amplifier. Errors such as no offset, drift, or noise to
offset, noise, and gain error that stem the output signal.
R2
1k
R1
1k
OUTPUT
VOLTAGE
12V
OP27
2V
12V
3.5V
R4
1k
R3
1k
OUTPUT
VOLTAGE
12V
_
OP27
1.5V
12V
3V
3V
2.5V
OUTPUT
VOLTAGE
OP27
12V
2V
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design
ideas
Figure 3
Figure 4
The spectral analysis of the differential-output signal shows that input to the instrumentation amplifier
is 2V p-p, 1 kHz.
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DC
VS
AC
RS
Figure 1
VS
DC
220
RF
220
240
240
VIN
2 VOCM
4 _
10
240
VIN+
25
7
10k
0.01 F
240
11
IC1
AD8351
RG
28
25
3 +
5
64.9
10k
12
IC3
AD6645
VIN CML
3
220
10M
220
DC
0.01 F
10k
DC
10k
_ 2
1
Figure 2
_ 6
IC2B
OP262
5
5k
IC2A
OP262
+ 3
5k
connected between the source and a negative supply of equal value remove dc bias
currents from the source.
The circuit of Figure 2 expands upon
this simple concept by replacing the supply voltages VS with precise VDC levels that track one another. In addition,
this design implements differential signaling by doubling the number of levelshifting resistors. You produce the VDC
levels by subtracting the 2.4V ADC reference signal (CML pin) from the common-mode level of the amplifier, which
you form by summing the two amplifier
outputs through equal-value resistors.
The circuit amplifies, filters, and inverts
the difference to create the VDC levels.
The dc feedback-loop gain of approximately 1040 allows the amplifier to track
the output common-mode level to within (2.4V/1040)2.3 mV of the ADCs
design
ideas
FRONT-END
GAIN
(dB)
HARMONIC
DISTORTION
(dBFS)
THIRD HARMONIC AT 6 dB
THIRD HARMONIC AT 12 dB
SECOND HARMONIC AT 6 dB
SECOND HARMONIC AT 12 dB
Figure 3
FREQUENCY (MHz)
Figure 4
This graphic shows the frequency response of the circuit in Figure 2 for
various values of gain.
FREQUENCY (MHz)
RF
()
1540
698
316
Front-end gain
(dB)
12
6
0
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design
ideas
C1
0.47 F
F1
P1
S1
PLUG
SPST
10A
sec to turn on the load for the remainR3
120V AC
R1
10M
der of each 60-Hz half-cycle, so higher
820
0.5W
power accrues by turning on earlier in the
PHASE
D1
half-cycle. R3, at the timing pin of the con5V DC
troller chip, detects line phase. Controller
FEEDBACK
1N4148
pins CS3 to CS0 set the closed-loop conIC1
VSET
figuration for an application.You can eas18
1
FBK
HEN
D2
17
2
R2
REF
LEN
ily modify the lighting-control circuit for
16
3
SPT
STA
R5
15
4
thermal control (Figure 2). Closed-loop
10k
BIP
TIM
1N5232B
50
14
5
GND
VDD
5.6V
timing is 134 sec for optimized tempera300W
13
6
PS0
CS3
HEATER
12
7
C2
C3
ture response, using controller pins CS3
PS1
CS2
11
8
220 F 0.1 F
PS2
CS1
to CS0. The circuit initially drives the
10
9
PWM CS0
CLZD010
heater at high power levels until
Q1
Figure 2
R4
the temperature nears its final
200
L4008L6
value and then reduces the power to avoid
CLOSED-LOOP
LOGIC
overshoot. The CLZD010 controller is
NEUTRAL
CONTROLLER
TRIAC
available from Flextek Electronics (www.
flex-tek.com).
A slight modification adapts Figure 1s circuit to for heating control.
1
2
3
IC2
1
VS
OUT
2
LM34
GND
3
TEMPERATURE
SENSOR
Constant-current, constant-voltage
converter drives white LEDs
Keith Szolusha, Linear Technology Corp, Milpitas, CA
VIN
R3
EDs usually take their drive from a
3.3 TO 4.2V
0.1
D2
constant dc-current source to main1%
tain constant luminescence. Most
dc/dc converters, however, deliver a conL1
LXHL-BW02
SD25-100
stant voltage by comparing a feedback
D1 PMEG2010EA
10 H
voltage to an internal reference via an internal error amplifier. The easiest way to
ON/OFF
turn a simple dc/dc converter into a con8
7 6
stant-current source is to use a sense reVIN
SW SW
9
C1
sistor to convert the output current to a
3
ISP
SHDN
1 F
voltage and use that voltage as the feed6.3V
2
IC1
R2
ISN
CERAMIC
back. The problem is that 500 mA of outLT1618
866k
4
put current with a 1.2V dropthe typiIADJ
FB 1
C2
R5
250/
cal reference voltagein the sense
4.7 F
VC
GND
1M
500 mA*
10V
resistor incurs relatively high power loss5
10
R1
CERAMIC
R4
C3
es and, thus, a drop in efficiency.
124k
2.2M
0.1 F
Figure 1
One approach is to use an external op amp to amplify the voltage drop
* 500-mA FLASH ONLY.
across a low-value resistor to the given
reference voltage. This method saves con- The LT1618 white-LED driver supplies 250-mA constant current and 500-mA flash from a
verter efficiency but significantly in- lithium-ion battery.
creases the cost and complexity of a simple converter by using additional Figure 1 shows the LT1618 driving a 1W, can pulse it up to 500 mA for a camera
components and board space. A better white Lumileds (www.lumileds.com) flash. R4 is set for a 250-mA torch or dimming operation. The IADJ (current-adapproach is to use the LT1618 constant- LXHL-BW02 Luxeon LED.
current, constant-voltage converter,
You need no external op amps for this justment) pin provides the ability to dim
which combines a traditional voltage- compact approach. The LXHL-BW02 the LED during normal operation by
feedback loop and a unique current-feed- has a forward voltage of 3.1 to 3.5V for varying the resistor setting or injecting a
back loop to operate as a constant-volt- 250 mA of current. Although the maxi- PWM signal. Access to both the positive
age, constant-current dc/dc converter. mum dc rating of the LED is 350 mA, you and the negative inputs of the special in-
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design
ideas
avoids the need for an additional inductor. This design uses one small, low-cost
inductor, matching the all-ceramic capacitors and low-profile IC. Tying the
load back to VIN increases the inductor
current by summing both the input and
the output currents. The internal switch
losses double, and the overall efficiency
of the approach is approximately 70%
over the input-voltage range. Even at this
efficiency, it is difficult to match the compactness and low cost of this approach.
STATE 1
PORT A=$01
DELAY=2 SEC
DARK=0
DARK=1
DARK=1
DARK=0
STATE 3
PORT A=$03
DELAY=2 SEC
DARK=1
DARK=0
STATE 2
PORT A=$12
DELAY=4
MINUTES
Figure 1
5V
ACTIVE
120V AC
1
MC68HC908QT2
PA0
R2
20k
LED0
LAMP
PA1
2 ADC
PA5
LED1
2
PA4
R1
430
Q1
L2004F31
1
NEUTRAL
VT80N1
Figure 2
design
ideas
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design
ideas
The circuit in Figure 1 uses IC1, the integrated offline Viper22A switching regulator in a constant-current configuration
to drive two to eight 1W LEDs. The circuit operates by monitoring the voltage
drop across the sense resistor, R6, and uses
this voltage as feedback to regulate the
current through R6 and the LEDs. An operational amplifier in the TSM103, IC2,
monitors the voltage drop across RSENSE
and compares it with the 0.175V reference, which resistor divider R5-R7 sets,
and closes the loop to maintain a 0.175V
F1
J1
2
1
R1
68
5%
1W
4
FUSE
C11
0.047 F
D1
600V, 1A
400V
DF06MGI
C1
10 F
400V
CRAMER
CVP11-046
1
+ 3
L1
COMP0STAR
45 mH
C3
47 pF
1 kV
180T
2
R2
100
5%
1/2W
1
2
D2
STTH102
R3
6.2k
5%
1/4W
C5
4.7 nF
R4
100
5%
1/4W
1
IC3
H11A817A
2
3
C6
0.33 F
C
50V
4
+
22 F
50V
R9
2.2k
1 1/2W 2
2
R11
1k
1
IC2
TSM103
1
R6
0.5
1/2W
6 W1
1
2
Figure 1
J2
1
2
5
56T
1
2
IC1
VIPER22A
4
DRAIN VDD
DRAIN
DRAIN
DRAIN
F 3
SOURCE B
SOURCE
0.35A (7V-27.5V)
+ C7
220 F
50V
8
R8
10
5%
1/4W
8
7
6
5
D3
STTH102
1 38T
2
10
D4
PKC-136
C2
10 F
400V
VCC 8
7
OUT1
C8
0.1 F
VE1 OUT2
VREF
VE2
GND
VE2+
R7
10k
R10
1k
1/4W
6
5
R5
750
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design
ideas
(a)
(b)
93 mm
(c)
46 mm
Figure 2
These photos show the completed board (a) and the top (b) and bottom (c) layouts.
uses a turns ratio of primary to secondary output voltage for the maximum
number of LEDs. Using these criteria, as
the number of LEDs decreases, so does
the reflected voltage. If you base the
transformer on two LEDs, then the reflected voltage quadruples with eight
LEDs and may exceed the rating of the
Viper. The turns ratio between secondary to the VDD winding is set for an output voltage of two LEDs to the minimum
VDD voltage of 9V. As you add LEDs, VDD
increases proportionally until it reaches
the overvoltage-shutdown point of 42V
nominal.
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design
ideas
ence, senses the voltage on the supercapacitor. R3 provides 0.5V hysteresis to the
comparator. When the voltage is lower
than 1.7V, the comparators output is low
and thus turns on the p-channel MOSFET, Q1. The battery charges the supercapacitor. Once the voltage on the supercapacitor reaches 2.2V, the comparator
switches high to shut off Q1. You could
use this low-to-high transition at Point A
as a battery-charge-complete indicator or
to trigger another device, such as a microcontrollers interrupt line.
1/2 FDC6312P
1/2 FDC6312P
Q1
Q2
R1
10M
R4
10M
R3
60M
+
1
BT1
3V
5
IC1 VCC
MAX917
2
VEE
4
3
IN+
REF
C1
0.1 F
OUT
C2
1.5F
2.5V
LOAD
R2
15M
Figure 1
To eliminate the need for larger batteries, the circuit in Figure 1 solves the
problem by gradually building up energy
in a supercapacitor. The device releases
the energy when it is needed. Because the
supercapacitor has low internal impedance, the momentary current can easily
exceed several amperes.
Because a coin-type lithium battery
delivers 3V and the supercapacitors rated voltage is 2.5V, the circuit uses a voltage-controlled switch to cut off the battery once the voltage on the supercapacitor reaches 2.2V. This design uses
a 1.5F, 2.5V supercapacitor from PowerStor (www.powerstor.com), model A1030-2R5155. IC1, a micropower voltage
comparator with built-in 1.245V referwww.edn.com
design
Edited by Bill Travis
ideas
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itive cycle of the resonance to the average clamping voltage and because slow
diodes often exhibit a slightly poorer forward-recovery characteristic than do
their fast counterparts. This characteristic results in a step of several volts at the
beginning of the conduction.
Nonlinearity of the
transconductance of Q1
results in this distorted waveform.
Figure 3
C1
INPUT 10 F
R1
100k
R3
2k
OUTPUT
Q1
BC847C
R2
36k
R4
510
C2
1000 F
R5
510
C3
1000 F
D1
D1N4148
Figure 1
The addition of a simple diode in the emitter circuit yields the symmetric waveform of Figure 4.
ter current. Consequently, the instantaneous voltage-gain coefficient of the conventional common-emitter amplifier is
proportional to the instantaneous
emitter current. As a result, the negative half-cycle of the output signal gets
more amplification than does the posi-
Figure 4
design
ideas
3
2
1
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design
ideas
sult, by dimensioning the R5 and C3 elements, you can insert a delay to enable
the supply to cope with transient loads.
P40
P41
P42
P43
P44
P45
VPP
XT1
XT2
VDD2
VSS0
X1
X2
RESET
P46
P47
P00
P01
P02
P03
strap-down inertial-navigation
1
V
P50
1
5V
system uses silicon sensors to measBIAS
2
P51
V
3
P52
V
4
P53
ure displacement without entailing
V
5
P20
GROUND
2
V
6
P21
the bulk and expense of moving parts or
COM0
7
P22
CXL04M3
COM1
8
P23
X
AXIS
GPS receivers. For example, a three-axis
AN10
COM2
9
P24
3
THREE-AXIS
COM3
P25
PD78F9418A
accelerometer and three angular-rate
S0
11
P26
ACCELEROMETER
S1
12
P27
Y
AXIS
48
sensors can determine the position and
S2
13
AV
AN11
47
4
AN10
S3
14
46
AN11
S4
15
velocity of a vehicle such as a robot or ra45
AN12
S5
16
Z AXIS
44
AN13
S6
17
dio-controlled aircraft. This hardware
AN12
5
43
AN14
S7
18
42
AN15
S8
19
configuration requires that you read and
AN16
S9
20
integrate the sensor outputs and then
combine and process them to obtain sta- (a)
R5
bilized location values. Figure 1 shows
(c)
2.7k
one such complete system. An inexpensive 8-bit microcontroller can handle the
R6
sensor reading and integration tasks, and
1
8
2.7k
VIN
perform simple lowpass filtering of the
V+
2
7
accelerometers output to remove conVIN+ INA118 VOUT
R7
3
6
AN13
version noise. The microcontroller can
1
8
2.7k
V
V
REF
VIN
V+
even run a basic position and velocity al4
5
2
7
gorithm; alternatively, you can pass the
VIN+ INA118 VOUT
AN14
3
6
1
8
preprocessed data to a DSP system. The
VREF
V
VIN
V+
4
5
NEC (www.necelam.com) PD782
7
F9418A microcontroller has seven ADC
VIN+ INA118 VOUT
X AXIS
3
6
VOUT
5V
inputs, so it can handle the six inputs
1
2
VREF
V
4
5
from the sensors.
V
VREF
GND
CG-16D
3
4
Because a Crossbow (www.cross
Y AXIS
VOUT
5V
bow.com) CXL04M3 accelerometer deANGULAR RATE
1
2
2
SENSOR
livers 0.5V/g (9.8m/sec ), it can directly
VGND
VREF
CG-16D
3
4
feed three of the microcontrollers ADC
Z AXIS
VOUT
5V
ANGULAR RATE
inputs. Each NEC/Tokin CG-16D angu1
2
(b)
SENSOR
lar-rate sensor generates only 1.1
VGND
VREF
CG-16D
3
4
mV//sec, so it requires the aid of an inANGULAR RATE
strumentation amplifier. The BurrAn accelerometer (a), three silicon sensors (b), and
Figure 1
SENSOR
Brown (www.ti.com) INA118 fills
a microcontroller (c) fit together to form a complete
the bill. The microcontroller has enough inertial-navigation system.
I/O lines to drive three Varitronix
(www.varitronix.com) VIM-503 41/2- culates the average value of the ac- the time squared, halve that quantity, and
digit LCDs that display the x, y, and z lo- celerometers outputs over 1000 samples then add the result and the bias value to
cation relative to the starting point. One and uses this information to calculate the previous x position. You find velociof the fundamental tasks in this applica- bias-error adjustments for each axis. You ty by multiplying the bias-corrected xtion is to initialize the sensors and A/D apply each bias value by adding it to the axis reading by the time and then adding
converters to minimize bias error. Listing readings for that axis. Using the x axis as it to the previous x velocity. You can
1 at the Web version of this Design Idea an example, you determine the vehicles download the microcontroller code from
at www.edn.com shows the code to cali- movement from its starting point by in- the Web version of this Design Idea at
brate the accelerometer. The routine cal- tegrating: Multiply the x-axis reading by www.edn.com.
DD1
LCD0
LCD1
LCD2
SS1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
V
5V DD
AVREF
40
SS
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AN15
design
ideas
1G SAMPLE/SEC
VIN
POUT
1 F
CIN
R1 C1
330
FLYING
CAPACITOR
2V PP
CHOLD
X(2)
CHARGE
PUMP
CURRENT
SOURCES
LED1
IS
SD
BRIGHT
LED2
MICROCONTROLLER
INPUT
5.36V PP
R3
Figure 1
CK0
CK1
PORT11
COP8SBR
PORT12
PB1
1V
PB2
DM7404 INVERTERS
M 500 nSEC
BW
2.12 V
Figure 2
design
ideas
NETWORK-ANALYZER
NETWORK-ANALYZER
the most common for measby a factor of two by R3
"A" INPUT
"R" INPUT
and R4 and goes to the
uring the gain and phase of a
8V
feedback output. (The
power supply, it has signifiR1
50 resistor balances the
cant limitations. First, to
POWER1k
MIC922BC5
SUPPLY
+
network analyzers source
measure low-frequency gain
OUTPUT
FEEDBACK
impedance.) This action
and phase, the transformer
_
essentially breaks the loop
needs high inductance. FreR2
1k
and injects the ac signal
quencies lower than 100 Hz,
R3
1k 8V
on top of the dc output
therefore, require a large and
voltage and sends it to the
expensive transformer.
R4
Figure 2
1k
feedback terminal. By
Also, the transformer
NETWORK-ANALYZER
monitoring the feedback
must be able to inject high Op-amp injection is a
50
SOURCE
terminal (R) and output
frequencies. Transformers good alternative to transterminal (A), the analyzer
with these wide frequency former-based injection
measures gain and phase.
ranges generally are custom- and has no minimum-freThis method has no minmade and usually cost sever- quency limitation.
imum frequency. Make
al hundred dollars. By using
an op amp, you can avoid the cost and output to the noninverting input by half. sure that the bandwidth of the op amp
frequency limitations of an injection The network analyzer is generally a 50 is much greater than the expected bandtransformer. Figure 2 demonstrates the source. R1 and R2 also divide the ac signal width of the power supplys control loop.
use of an op amp in a summing- ampli- from the network analyzer by half. These An op amp with at least 100-MHz bandfier configuration for signal injection. R1 two signals sum together at half their width is more than adequate for most
and R2 reduce the dc voltage from the original input. The output then gains up linear and switching power supplies.
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IC2
14.756 MHz
18
R3
200k V4
R1
1M
R2
3.92k V1
11
10
IC1
XTAL2
TX0
RX0
IC1
C9
0.01 F
IC1 1
HC04
8
PWM1
PWM0
8
7
6
5
4
CEX4
CEX3
CEX2
CEX1
CEX0
IC1 9
12
HC04
R7
1M
IC1 5
5V (REFERENCE)
14
Figure 1
Two PWM outputs from a
microcontroller combine to
form a monotonic 16-bit DAC.
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VCC
C1B
0.1 F
GND
IC1
HCO4
7
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
INTO PSEN
HC04
40
20
31
28
27
26
25
24
23
22
21
16
17
ALE 30
12
13
IC1
C8
HC04
0.0056
R4
F V
3.92k
2
R 6 V3
1M
A15
A14
A13
A12
A11
A10
A9
A8
R0
HC04
R5
200k
EA
WR
11
0.1 F
RST
HC04
10
VDD2
VSS
19
C5
27 pF
VDAC
0 TO 5V
(REFERENCE)
XTAL1
Y1
5V
69RH051 A
C4
27 pF
32
33
34
35
36
37
38
39
29
design
ideas
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design
ideas
R3
10k
C1
0.1 F
R1
10k
R4
3600
R2
10k
C6
0.02 F
C3
0.015 F
C2
470 pF
(a)
Figure 1
R5
3600
C4
0.01 F
C1
0.1 F
R1
10k
R2
10k
+
C2
470 pF
C5
R6
1800 0.01 F
(b)
The addition of a twin-tee network (b) considerably improves the roll-off rate of the circuit (a).
Consequently, the ac-coupled instrumentation amplifier behaves as a highpass filter with a 3-dB cutoff frequen(continued on pg 92)
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design
ideas
VIN1
R
R
cy from the equation f1/2RFBCFB. At
IC1
first glance, you might think that the out_
put-autozeroing behavior of the ac-couR2
pled instrumentation amplifier is per_
fect. Unfortunately, the output
R1
autozeroing capability of this circuit is
IC3
VOUT
R2
+
CFB
strongly limited. You can determine this
limitation by expressing the output voltRFB
age as a function of the input signals and
_
_
R
R
the integrators output voltage, VZ:
IC4
IC2
VOUT(12R2/R1)(VIN1VIN2)VZAD
VIN2
+
+
VZ
(VIN1VIN2)VZ, where VOUT is the output voltage. In this expression, AD
Figure 1
12R2/R1 is the differential gain in
the passband. At dc, the output voltage is This ac-coupled instrumentation amplifier accommodates only 5-mV maximum input.
0V as long as the integrators output does
not reach its saturation voltage, VZ(MAX). as a function of the input signal and the
Therefore, setting the output voltage at integrators output voltage, VZ, becomes:
0V in the above expression yields the
maximum differential-input dc voltage
that this circuit can handle:
R
100k
IC1
R 1/2 LMC662
+
100k
IC5
R4
100k
R3
1.5k
R2
3.3k
R1
470
R2
3.3k
R
100k
1/2 LMC662
IC3
CMRR
TRIM T
RF
95k
10k
1/2 LT1464
RFB
4.7M
IC4
IC2
VIN2
VOUT
CFB
1 F
VZ
1/2 LMC662
Figure 2
design
ideas
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ideas
)
R2 (k
0
3.5
7
0
6.5
13
VCOM (V)
3.5
4.0
4.5
3.3
4.2
5.1
6.8
design
ideas
that you can use any available logic supply to power the potentiometer providing the VCOM adjustment. The 6- or 8-bit
AD5258/59 nonvolatile digital potentiometer demonstrates this approach. An
I2C serial interface provides control and
VCC
SUPPLIES POWER
TO BOTH THE
14.4V
3.3V
R1
70k
C1
1 F
AD5259
R6
10k
R5
10k
VDD
CONTROLLER
SCL
SDA
R6
10k
IC1
AD8565
R2
10k
R5
10k
VDD
3.5V<VCOM<4.5V
CONTROLLER
SCL
SDA
5V
VLOGIC
GND
IC1
AD8565
R2
10k
3.5V<VCOM<4.5V
GND
R3
25k
Figure 1
A digital potentiometer makes it easy to adjust VCOM to the
desired value.
R1
70k
AD5259
VLOGIC
14.4V
3.3V MICROCONTROLLER
5V
C1
1 F
R3
25k
Figure 2
A separate VLOGIC pin makes it possible to derive the VDD supply from
the potentiometers resistor string.
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design
ideas
EEPROM), the AD5259s VLOGIC pin typically draws 35 mA. It cannot draw this
current level through R1 because the voltage drop would be too large. For this reason, the AD5259 has a separate VLOGIC pin
that can connect to any available logic
supply. In Figure 2, VLOGIC uses the supply voltage from the microcontroller that
is controlling the digital potentiometer.
Now, VLOGIC draws the 35-mA programming current, and VDD draws only microamps of supply current to bias the internal switches in the digital potentiometers internal resistor string. If the panel requires a higher VCOM voltage, you can
add two resistors to place the op amp in
a noninverting gain configuration.
The digital potentiometer has 30%
end-to-end resistance tolerance. Assuming that the tolerances of R1, R3, and VDD
are negligible compared with those of the
potentiometer, you can achieve the range
of output values that Table 1 shows. Assume that the desired value of VCOM is
VDD
VLOGIC
RDAC EEPROM
RDAC1
REGISTER
RDAC1
A1
W1
DGND
B1
SCL
SDA
8
I2 C
SERIAL
INTERFACE
DATA
8
CONTROL
AD0
AD1
COMMAND-DECODE LOGIC
POWERON
RESET
ADDRESS-DECODE LOGIC
CONTROL LOGIC
Figure 3
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VS
8
0.3 mA
MIC4451
INVERTING
0.1 mA
6, 7
OUT
2k
IN
2
MIC4452
NONINVERTING
4
GND
Figure 2
C1
C2
10 F, 15V
10 F, 15V
MIC4451
OUTPUT
TO LOAD
plifies inversion of logic control as needed. Figure 1 shows details of the interface
of the MIC4451 to TTL levels, using a
common-base pnp transistor for level
translation. The emitter current of Q1 is
approximately: IE(VTTLHVBE)/R1
(2.40.65)/R1, where VTTLH is the TTLhigh level, 2.4V. IE should be 400 A in
accordance with TTL specs, so
IE(2.40.65)/R1400 A.
Solving for R1, you obtain R1
1.8V/400 A4.5 k. The VIH (lowest
permissible high input) logic-level
specification of the MIC4451 is 2.4V.
Ignoring base-current errors, ICIE,
so R2IC2.4V. Note that the MIC4451s input voltage, VIH, is specified
with respect to the ground pin of
the part. To determine R2:R22.4V/
Build a negative-voltage
power-side switch ........................................105
Circuit offers series protection
against power-line transients....................106
Build a simple, soft-action
muting switch ..............................................108
High-voltage amplifier
uses simplified circuit ..................................110
Simple circuit provides
power sequencing........................................112
(a)
Figure 3
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(b)
Turn-on (a) and turn-off (b) characteristics of the circuit in Figure 1 are for a
12V supply.
design
ideas
: 4 mV
AT: 1 mV
: 3.18 mSEC
AT: 1.62 mSEC
D1
5.6V
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design
ideas
V
OUT
tiates a rapid sequence: Q3 turns
detector. The power switch and
2V/DIV
series-connected power rectifier,
on, which turns on Q4, which
turns off Q1 by quickly dischargD1, protect the load
Figure 2
against high-voltage
ing its gate capacitance.
VIN
50V/DIV
transients and continuous overYou can demonstrate the cirvoltage as high as 500V of either
cuits performance by applying a
polarity.
150V transient to the supply voltIn the circuit, which powers
age while the circuit output is deVGATE
loads as heavy as 1A from a nomlivering 1A at 12V (Figure 2). The
20V/DIV
inal 12V power line, a high-sideinternal impedance of the transwitch driver, IC1, biases the powsient source is 1, and the rise
er switch fully on. You can
time of the applied voltage is 1
increase the maximum load cursec. The circuit draws 20 A
rent by changing D1 and Q1. To
during normal operation, includguard against low supply voltage, A 150V transient applied to VIN of the Figure 1 circuit has little
ing 3 A by the undervoltageIC1 includes an undervoltage- effect on VOUT.
lockout, voltage-sensing divider
lockout feature that allows operand 17 A by IC1. If your design
ation only when the line voltage is greater power switch to ground, turning it off needs high-temperature operation, note
than 10V. To protect against overvoltage, hard. Rising overvoltage first turns on that the gate-current output of IC1 is relthe circuit includes a three-transistor, no- zener diode D2, which protects the IC by atively limited. Your design calculations
bias-current, 50-nsec-operation over- clamping the voltage across it to approx- for high temperature should also pay
voltage detector that triggers when the imately 18V. Zener current flows through close attention to leakage currents that
input voltage reaches approximately 20V. the 2.2-k resistor, producing a base the other circuit components conAt that time, Q4 crowbars the gate of the voltage that turns on Q2. That action ini- tribute.
D1
1N4148
MUTE
R1
3.9k
RED
D2
12V
GREEN
1
2
S1 3
12V
R2
20k
TP1
Q1
2N3819
R3
82k
R4
2.2M
D
G
SIGNAL TO BE MUTED
(10- TO 100-k IMPEDANCE)
C1
100 nF
D3
1N4148
Figure 1
NOTE:
SET VOLTAGE AT TP1 TO TWICE Q1's VGS(OFF),
SO THAT 0.50VGS(OFF) = 0.7RC=150 mSEC.
This simple circuit provides soft muting for line-level audio circuits.
ample. Q1 can then finish muting. Making Q1 a more tightly defined PN4392 can
soften this requirement and allow muting of lower impedance signals. R3 unloads S1 from R2, so that D3 does not
shorten the earlier transition times. S1s
normally closed contact, resistor R1, and
dual-LED D2 add an indicator light. D1
raises the red LEDs on-state threshold to
indicate green when muting is off. Replacing D1 with a short circuit causes the
red LED to light. This scheme makes a
more expensive DPDT (double-pole,
double-throw) switch unnecessary, provides uninterrupted light as S1 switches,
and reduces the LED-current change for
less noise (references 1 and 2).
References
1. Linkwitz, SJ, Loudspeaker System
Design, Wireless World, Volume 84, June
1978, pg 67.
2. Self, D, Inside Mixers, Wireless
World, Volume 97, April 1991, pg 280,
www.dself.dsl.pipex.com/ampins/mixer/
mixerdes.htm.
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design
ideas
Figure 3
Figure 2
The sinusoidal
input is 8V p-p (top trace), and output
is 1800V p-p (bottom trace).
1000V
R25
10k
R26
3M
Q1
R24
Q11 82k
R27
3M
Q2
R28
3M
Q3
R29
3M
Q4
R15
3M
R14
3M
12V
R2
20k
R1
10k
C2
0.1 F
R5
3M
R10 Q12
10k
R6
7.5k
R11
10k
12V
R4
2M
CP07
+
12V
3
R3
20k
7
+
LF356
2
6
12V
12V
FUNCTION
GENERATOR
R7
510k
R23
82k
12V
R9
510k
R12
10k
R8
C1
5k 0.022 F
R22
10k
R37
3M
R30
3M
R21
10k
R38
3M
R31
4M
D1
1N961
R20
82k
R16
3M
This ac high-voltage
amplifier can deliver
more than 1800V p-p.
Q6
R17
3M
R18
82k
R19
10k
R32
4M
Q7
R33
4M
Q8
R34
4M
Q9
OUTPUT
MONITOR
R39
10k
R35 Q
10
4M
1000V
R36
10M
Q5
R13
10k
Figure 1
R40
1k
design
ideas
SEQUENCING CIRCUIT
2.5V
5V BIAS
C2
0.1 F
Figure 1
3 +
IC1
OPA336N
1
OUT
2
R5
100k
J1
1
2
3.3V
SENSE
GND
C8
0.1 F
R6
51.1k
3 +
IC3
OPA336N
1
OUT
VIN
R1
100k
IC2
TPS5120DBT
R4
51.1k
0.85V
REFERENCE
VOLTAGE
1.8V
5V BIAS
C11
0.1 F
R7
100k
1
2
3
C7
4
1000 pF
5
6
7
8
9
C12
10
1000 pF 11
12
13
14
15
30
INV1
LH1
29
FB1
OUT1_U
28
SOFTSTART1
LL1
27
PWM/SKIP
OUT1_D
26
CT
OUTGND1
25
5V_STBY
TRIP1
24
GND
VCC
23
REF
TRIP2
22
STBY1
VREF5
21
STBY2
REG5V_IN
20
FLT
OUTGND2
19
POWERGOOD
OUT2_D
18
SOFTSTART2
LL2
17
FB2
OUT2_U
16
INV2
LH2
2.5V
+
VIN
2
J2
2.5V
SENSE
GND
1
2
R11
100k
R12
88.7k
R10
88.7k
1.8V
VIN
An amplifier circuit forces the converters output voltages to track during start-up.
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VIN
+
CBULK
VIN
LPRIM
VAUX
CBULK
LPRIM
VOUT
VOUT
+
LAUX
RVCC
LOUT
RFWD
LAUX
LOUT
D2
+
CVCC
D1
RDMG
CRES
CRES
8
RCOMP
NCP1207
CS
RCOMP
RCS
RSENSE
(a)
CDMG
Figure 1
The standard approach (a) for overpower protection is unacceptable when you need low standby power; an approach
using a fraction of the input voltage (b) comes to the rescue.
RCS
RSENSE
(b)
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design
ideas
COMPENSATION
OFFSET=OV
1 CURRENT=
SENSE PIN VOLTAGE
1 CURRENT=
SENSE PIN VOLTAGE
2 SENSE=
RESISTOR VOLTAGE
2 SENSE=
RESISTOR VOLTAGE
3 COMPENSATION
VOLTAGE
3 COMPENSATION
VOLTAGE
4 DRAIN
VOLTAGE
4 DRAIN
VOLTAGE
Figure 3
Figure 4
design
ideas
DD
he demand for power in color cellphone handsets is constantly increasCS +
ing. New applications steadily emerge,
1 F
VDD
making it imperative to reduce power
consumption in the design. ExamiVIN1
Figure 3
nation of usage data shows that more
VDD
VDD
than 50% of the power consumed is in
R
VOUT1
providing backlighting for the color
BIAS
PU
100k
screen. People use the phones for playing
+
50k
TO LM2794/95
20k
BRGT PIN
games and MP-3s and a multitude of othSHUTDOWN
BYPASS
er heavy-duty, multimedia functions. FigCB +
+
VOUT2
50k
ure 1 shows the classic way to use a back1 F
VIN
CIN
1 F
POUT
CHOLD
1 F
D1
C1
1 F
C2
1 F
C1+
D2
C1
C2+
C1
1 F
C2
1 F
LED2
3V
D4
LED3
0V
BRGT
GND
POUT
CHOLD
1 F
D1
LED1
D3
C2
SD
VIN
CIN
1 F
C1+
D2
C1
C2+
LED1
D3
C2
BRGT
LED2
D4
LED3
SD
ISET
LM2794/95
Figure 1
LED4
RSET
GND
ISET
LM2794/95
LED4
RSET
Figure 2
design
ideas
/19
/20
/20
/21
/20
ADVANCE
RETARD
NOTE: ADVANCE/RETARD PULSES TAKE EFFECT ON THE NEXT CYCLE, NOT THE CURRENT CYCLE.
FCLK
CLOCK
SINGLE ONE
ROTATES FOREVER
MODULATED
CLOCK OUTPUT
FOUT
RETARD
Figure 1
/20
/21
DIVIDESELECT
SWITCH
ADVANCE
(RESET)
LOAD WITH
SINGLE ONE,
ALL OTHERS
ZEROS
SWITCHCONTROL
LOGIC
This scheme allows you to change the rate of the spreading-code clock
in spread-spectrum applications.
design
ideas
INPUT
SYS_CLK
VCC
VCC
CLRN
RESET_
MODULATOR
INPUT
A B
CLRN CLK
SHIFT
REGISTER
QA QB QC QD QE QF QG QH
74164
PRN
A B CLRN CLK
FIVE-CELL
74164
QA QB QC QD QE
74165
QHN QH
DFF
VCC
VCC
AND2
OR3
CLK_OUT
AND2
AND2
OUTPUT
AND2
1Q
1QN
2Q
2QN
7474
1PRN
1D
1CLRN
1CLK
2PRN
2D
2CLRN
2CLK
D FLIP-FLOPS
VCC
1Q
1QN
2Q
2QN
7474
1PRN
1D
1CLRN
1CLK
2PRN
2D
2CLRN
2CLK
D FLIP-FLOPS
VCC
1Q
1QN
2Q
2QN
7474
1PRN
1D
1CLRN
1CLK
2PRN
2D
2CLRN
2CLK
INPUT
ADV_IN
NAND2
INPUT
RET_IN
D FLIP-FLOPS
7404
Figure 2
Alteras software allows you to enter standard logic-gate symbols to create a programmed CPLD.
(continued on pg 112)
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design
ideas
FOUT
these flip-flops clear if Adate a programming file for
PHASE
vance/Retard pulses arrive sithe device. Although this demultaneously, an illegal input
sign uses a CPLD, a discrete
condition.
version using digital-logic
The second set of flip-flops
ICs, as the schematic shows,
captures the rising edges of the
should also work. The FCLK
input connects to all the shift
Advance/Retard inputs. Subseregisters clock inputs. A Re-
STEP=2/N
quent rising edges are ignored
set function initializes the
for a complete cycle of FOUT.
This set of flip-flops holds the
registers with a single one
SLOPE=0
state of the selection switch for
and the rest zeros. Using a
SLOPE=0
2NTMOD
the next cycle of FOUT. After
single flip-flop, FCLK samples
SLOPE
2NTMOD
the asynchronous reset signal
every cycle of FOUT, these flipTIME
flops
reset to the divide-by-20
to ensure synchronous oper.......
state. The output of the third
ation. Three sets of flipset of flip-flops controls the
flops prepare the AdFigure 3
The stair-step portions of this graphic show where
AND/OR switch logic, which
vance/Retard signal for
selects the divide ratio for the
use by the selection switch. phase is added to or subtracted from FOUT.
current cycle. As the single logFrom the right-hand side of
Figure 2, the first set of flip-flops on the them for the next cycle of FOUT. We ic one shifts to the right, it first latches the
Advance and Retard inputs ensures that assumed that these signals would be selected switch position into the last set
these signals are synchronous with the fi- asynchronous with the input clock, FCLK. of flip-flops. This selection could be di(continued on pg 116)
nal output frequency, FOUT, and stores The NAND gate ensures that both of
TMOD 2TMOD 3TMOD 4TMOD
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point until the next cycle of FOUT. We programmed the modulator into an Altera
EPM7128-10 (10-nsec) device, and used
an input-clock frequency, FCLK, of 20
MHz. When the divide-select switch is in
the divide-by-20 state, it is easy to compute the frequency output; its just the input clock divided by 20. For an N-bit system, it would be the input clock divided
by N. But how do you derive a general
formula for FOUT if Advance/Retard pulses arrive at a rate of FMOD? Whenever an
Advance or Return pulse is processed, a
fixed amount of time is added or subtracted to the time between FOUT pulses.
You need an expression for the equivalent amount of added or subtracted
phasein other words, the phase step.
One complete cycle of FOUT with no
Advance/Retard modulation takes
N/FCLK seconds. This interval is just the
period of the output with no modulation. If you add or subtract one clock period, how much phase does this represent
with respect to FOUTN/FCLK? In terms of
the fraction of time that adding or subtracting one clock period from the nominal output cycle, you can write: Fraction
of one output cycle per Advance/Retard
pulse(clock period)/(nominal-output
period)(1/FCLK)(FCLK/N) cycles1/N
cycles.
Converting to radians and defining
this step as the phase step or
STEP,
2/N radians. Therefore, every
STEP
time an Advance or Retard pulse is
processed, the phase of the output
changes by 2/N radians. You can now
use the fact that frequency is the time derivative of phase to derive the formula for
FOUT. Figure 3 shows a time plot of phase
of the output FOUT for the three possible
commands: Advance, Static (divide-byN), and Retard. In Figure 3, at first phase
is added, no change occurs in phase, and
then phase is subtracted. The frequency
is not changed where the slope is zero,
and is equal to FCLK/N. At the stair-step
portions of the plot, you can approximate the slope as 2/NTMOD. You can
interpret this figure as the change in the
output frequency (in radians). To convert
to cycles, divide by 2, which gives the
change in output frequency as FMOD/N
for Advance or Retard pulses arriving at
a rate of FMOD.
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LM3914
Figure 1
VDD
A microcontroller, a temperature
sensor with an A/D converter, and a
few other components form a smart
room-light-intensity controller.
VDD
6
5
VDD
IC1
ADT7516
GND
VOUTA 2
VOUTB 1
LED1
LED2
LED3
LED4
LED5
GND LED6
LED7
LED8
LED9
LED10
VDD
LED BAR
ARRAY
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
INPUT
DIMMER CIRCUITRY
MAINS SUPPLY
MOC3020
VOUTC 16
VDD
R2
13k
DIAL
R3
10k
7
E
2N3908
Q1
EXTERNAL
TEMPERATURE
C
SENSOR
R1
1M
D+/AIN1/AIN1+
PIC16C67
D/AIN2/AIN2
14
LDAC/AIN3
AIN4
15V
3
3
7
+
IC2
2 _ OP07
D1
PHOTODIODE
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INTERRUPT
DOUT /ADD
SOA/DIN
VREFIN
400V
TR1AC
VOUTD 15
CS
9
LAMP
SCL/SCLK
PORT B6
LCD
PORT D
10
11
12
13
16TWOCHARACTER
LCD
PORT B4
PORT B8
PORT B7
PORT B2
PORT B1
PORT B0
15V
design
ideas
troller uses the potentiometer and photodiode values, which the ADT7516 digitizes, to maintain equilibrium between
the light intensity and the required light
setting. If the photodiode reading is less
than the potentiometer setting, the controller increases the dimmer DAC value;
it decreases the dimmer DAC value if the
reading is greater.
One of the features of the ADT7516 is
its round-robin mode, in which it constantly monitors all of its measurement
channels. The master need not initialize
300
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ideas
stage. Figure 3 shows the nonoverlapping drive to the gates of the output
stage. Figure 4 shows the instantaneous
peak output current of the AD8565 in
Figure 1 in response to a pulse from the
test circuit.
10V
VOUT2
5V
CH 2=100 nA/DIV
SEL>>
0V
10V
V(R36:1)
VOUT1
CH 1=5V/DIV
5V
0V
0s
0.1
0.2
0.3
0.4
V(R37:1)
0.5
0.6
0.7
0.8
0.9
TIME (SEC)
Figure 3
TIME (2 SEC/DIV)
Figure 4
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design
ideas
A=5V/01V
B=5V/01V
C=5V/01V
D=5V/01V
10nSEC/DIV
Figure 2
1V/DIV
1/4 LT1721
INPUT
2nSEC/DIV
510
R0.8/nSEC
IC1
50
VARIABLE
DELAY
8 pF
1/4 LT1721
COMPARATOR
IC2
0.1 F
TO 2.5V
2.5V
DIFFERENTIAL
DELAY
GENERATOR
1k
5V
1/4 LT1721
IC3
620
FIXED
DELAY
G1
74AHCO8
AND
GATE
OUTPUT
1k
Figure 1
Figure 3
1V/DIV
8 pF
200pSEC/DIV
This pulse generator has 0- to 10-nsec width and 520-psec transitions. IC1 unloads termination and drives the differential delay network. The IC2-IC3 complementary outputs represent
delay difference as edge timing skew. G1, which is high during IC2-IC3s positive overlap,
presents circuit output.
Figure 4
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design
ideas
1V/DIV
1V/DIV
500 pSEC/DIV
200 pSEC/DIV
The partial-amplitude
pulse, 3.3V high, measures 700 psec wide with a 1.25-nsec base. The
trace granularity is an artifact of the 3.9-GHzsampling-oscilloscope operation.
Figure 5
A transition detail in
the 3.9-GHz bandpass
with rise time of 90 psec shows 520-psec rise
time; fall time is similar. The granularity
derives from sampling-oscilloscope operation.
Figure 6
V0
V0
VREF+
....
RREF3
RREF2
RREF1
....
RT3
RT2
RT1
VREF+
RREF
BUFFER
G=0.94
V1
RT
V2
12-BIT ADC
VREF
V2
Figure 2
Remove most gain and offset errors using two measurements
and a ratio calculation.
VREF
Figure 3
Extend the idea to handle multiple sensors and signal paths, using
multiplexing through a single buffer and A/D converter.
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design
ideas
With the development of more powerful microcontrollers and on-chip ratiometric ADCs, a resistor-divider block
architecture (Figure 2) provides a less expensive approach:
offset error, which can be the largest contributor of error to the overall accuracy.
Using more expensive and precise components reduces the offset error of any op
amps in the measurement path.
Figure 2 shows how to significantly remove gain and offset errors, in which
subtracting two measured voltages removes any offset errors in the measurement system:
The ratio of these two difference values removes any measurement-path gain
error, leaving the reference resistance to
determine the measurement error. This
result is valid as long as the measured signal is never outside the range of the A/D
converter. To guarantee this condition,
set the sense buffer gain to slightly less
than unity.
You can also measure multiple resistors, in which all the sense paths multi-
plex to a single buffer and A/D converter, and the eight analog pins let you
measure as many as six transducers (Figure 3). Alternatively, you could connect
each of four sense paths to its own buffer
and converter.
Listing 1 at the Web version of this Design Idea at www.edn.com shows how
you implement the circuit of Figure 2 using a programmable analog system-onchip controller. It uses the ADCINC12
user module, programmable-gain-adjustment user module, and two analog
output buffers. Placing the analog block
of the ADCINC12 just below the buffer
and setting the clock for the ADCINC12
to 167 kHz for a sample rate of 10 samples/sec remove any 50- or 60-Hz interference from the signal. Increase the sample rate if the application requires a faster
conversion. The control software is in C;
the program calculates the resistance
reading and leaves it in a global memory
location.
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at 50 mA. Because you operate the MOSFET at or near threshold, its on-resistance
spec doesnt apply, and the output impedance of this circuit is far higher than
you would expect from the on-resistance.
However, in general, the lower the on-resistance, the lower the output impedance
at a specific current near threshold.
This circuit may require that R2 and C1
stop the oscillation in the MOSFET. Add
a filter capacitor to the output to minimize the effect of load transients. Connecting a large filter capacitor from the
gate to the source with short leads eliminates the need for R2. You can use other
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VIN
R1
GATE-TO-SOURCE THRESHOLD VOLTAGE
VOUT
S
IRF521
VGS (V)
ROUT (k)
R2
100
C1
0.1 F
OUTPUT IMPEDANCE
ID (A)
A MOSFET configured to
Figure 1
replace a zener diode of a
shunt regulator
provides lower impedance
edn041111di35301
DIANE
than a diode-based implementation.
Figure 2
ative-temperature coefficient of the gateto-source voltage. This circuit has significant change in output voltage over a
wide temperature range; it is suitable for
only limited temperature ranges.
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design
ideas
power supply and 430 mA of input current, the circuit delivers 10 mA at 100V
for a 100V output, yielding an efficiency
of approximately 50%. Feeding L1 from a
separate 12V power supply improves efficiency.
If you design your own inductor for L1,
aim for a nominal inductance of 330 H
at 2A and a dc winding resistance of less
than 0.5. For optimum operation, use
a fast-recovery diode for D3 and a logiclevel N-channel MOSFET with a breakdown voltage of 200V or greater and an
on-resistance of less than 0.3 for Q1,.
Note that zener-diode manufacturers
specify breakdown voltages at specific
test currents. Also, when you subject
them to high reverse voltages, signal
diodes exhibit zener behavior.
Gain-programmable circuit
offers performance and flexibility
Luo Bencheng, Key Laboratory of Mental Health, Institute of Psychology,
Chinese Academy of Sciences
ou can use a standard precision instrumentation amplifier, such as the
INA118 or AD623, as a gain-programmable amplifier with high accuracy and wide gain range. However, the gain
range of such parts is fixed at certain values, limiting their flexibility. To solve the
problem, a usual way is to use a gain-adjustable circuit controlled by a microcomputer (Figure 1).
IC2 is a programmable 1-of-8 analogy
multiplexer that connects to eight
weighting resistors, R1 to R8, to improve
the gain range of the circuit based on IC2,
a general-purpose precision amplifier.
The overall gain of the circuit depends on
the value of the selected weighting resistor, as follows:
R1
pins Z0 to Z2 of IC2
A
GAIN
with a microcontroller
R2
SELECT
to provide self-adB
(VIA MICROR3
CONTROLLER)
justable gain according
C
R4
to the selected weightK
ing resistor. UnfortuR5
IC2
nately, the performR6
ance and quality of the
circuit cannot provide
R7
good performance and
R8
V
high quality due to the
on-resistance of IC2,
R0
which you also cannot
_
VIN
IC1
control, especially as
VOUT
OP27
the tempera+
Figure 1
ture changes.
R
The modified gainV
adjustable amplifier
circuit in Figure 2 uses
the same IC1 but A basic gain-programmable amplifier circuit uses digital outputs
changes IC2 to a pro- from a microcontroller to set gain.
grammable 2-of-8 difference-input analog multiplexer, which to RG8, to improve the gain range of the
connects to four balancing resistors, R01 circuit. By controlling the port-select pins
to R04, and eight weighting resistors, RG1 Z0 to Z1 of IC2 with a microcontroller, the
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design
ideas
V
R01
K1
VIN
R02
IC01
R03
V
R04
+
V
where RGA is one of the selected weighting resistors, RG1 to RG4, and RGB is one
_
of the selected weighting resistors, RG6
RG1
to RG8.
V
RG2
V
Analog multiplexer IC2 is on the inK2
put side of amplifier IC1. Resistors R01 to
R
G3
_
R04 balance the signal-input channel to
IC02
RG4
decrease the level-shifting because of
+
C A
the on-resistance of multiplexer IC2 and
minimize the effect of that resistance.
GAIN
RG5 RG6 RG7 RG8
V
SELECT
Additionally, two operational amplifiers, IC01 and IC02, act as followFigure 2
ers to improve the overall driver
performance and common-mode-rejection capacity of the circuit.
The modified circuit provides more flexibility, along with high performance.
VOUT
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C9
100 nF
AC IN
R1
1.2k
IC1
VIPER22A
R4
22
D1
1N4007
L1
470 H
D7
6.8V
+ C
3
10 F
C4
22 nF
Figure 1
This offline
SMPS controller
delivers dual
output voltages.
VDD
FB
D3
STTH106
D2
STTH106
DRAIN
+
CONTROL
C5
0.47 F
D4
STTH106
SOURCE
VOUT1
12V DC
1
C1
100 nF
56 TURNS
+ C
2
22 F
L2
420 H TOTAL PINS 1 TO 3
C7
220 F
D5
STTH102
VOUT2
5V DC
D6
4.3V
49 TURNS
3
AC IN
Q1
C6
+ 4.7 F
R2
22
R3
68
C8
+ 470 F
R5
4.7k
COMMON
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design
ideas
9
iezoelectric tubular positioners
20k
that drive manipulators in scanning
D2
VCC
1N4148
tunneling microscopes require
high-voltage, low-current drive circuits.
The circuit in Figure 1 can drive high-reMJE340
Q4
Q3
sistance, low-capacitance piezoD1
Q1
F
i
g
u
r
e
1
MJE350
1N4148
MJE350
electric loads at a 3-dB band12V
width of 6 kHz. It offers a low-cost
R4
R8
R3
10k
alternative to commercial drivers. Tran1k
4
1M
2 _
MJE350
VIN
OUTPUT
sistors Q3 and Q4 form a current mirror,
1
IC1
6
R5
Q5
with R3 setting Q4s collector current as
LF411 OUT
10k
MJE350
R6
3
5
the following equation determines:
+
10k
Q2
7
Q6
IC3IC4 [ VCC(VCC)VBE(Q4)]/R3.
R7
MJE340
VCC
Operational amplifier IC1 provides base
12V
40k
VCC
drive to Q5, which in turn drives Q6. With
RETURNS
no signal applied to IC1s input, the col- This complementary-symmetry
VCC
lector currents of Q6 and Q3 balance, and amplifier features low component count.
the output taken from the junction of
emitter followers Q1 and Q2 rests at 0V.
Applying an input signal to IC1 drives
its output toward the positive or the negative 12V supply rail. Allowing IC1s output to saturate would introduce sufficient
slew-rate delay to cause oscillations. Although specifying a relatively fast operational amplifier, an LF411, improves the
(a)
TIME (nSEC)
amplifiers bandwidth and slew rate, antiparallel diodes D1 and D2 improve stability by restricting IC1s output excursion to one diode forward-voltage drop.
You can adjust R7 to minimize output
dc offset voltage and slew rate. As a rule
of thumb, select resistor R7 to be twice the
value of R9. The ratio of R9 to R8 sets the
amplifiers gain. Figure 2 shows the input
and output waveforms using optimal val(b)
TIME (nSEC)
ues for R7 and R9. Note that the
ratings
for
Q
and
Q
limit
V
VCEO
Figure 2
The input waveform show input voltage applied as a pulse of 2 to 2V (a). The
1
2
CC
and VCC to 300V or less.
output waveform shows an amplifier gain of 20 and minimized output offset (b).
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TWISTED PAIRS
470
4.7k
4.7k
12V
DC
22 TO 24 AWG UNSHIELDED
TWISTED PAIRS
4.7k
4.7k
4.7k
4.7k
H11A8170
(TYPICAL)
470
470
4.7k
1N4148
4.7k
J1
Figure 1
A low-cost
master/slave
bus provides
as many as
six isolated
nodes.
RX
DTR
(+)
J1
RX
TX
RJ-11
4 0 0 1
5 0 0 2
6 0 0 3
47 F
16V
J1
RJ-11
RS-232
SLAVE
1N4148
4.7k
47 F
16V
J1
GND
RJ-11
47 F
16V
5V
RJ-11
4 0 0 1
5 0 0 2
6 0 0 3
BRGY
JUMPERS 3 TO 6
FOR INVERTED
SLAVE
RX
TX
GND
4 0 0 1
5 0 0 2
6 0 0 3
BRGY
JUMPERS 2 TO 5
FOR RS-232
+5V
TX
GND
4.7k
1N4148
4.7k
RX
4 0 0 1
5 0 0 2
6 0 0 3
BRGY
RS-232
MASTER
DTR
(+)
470
4.7k
1N4148
4.7k
47 F
16V
GND
470
4.7k
BRGY
INVERTED
SLAVE
JUMPERS 1 TO 4
FOR TTL AND
ALTERNATIVE WIRING
TTL
SLAVE
DB3 5
DB4 6
IC1
LM4040-4.1
PIN
NUMBERS
DB0 2
R1
150
C1
10 nF
3
R2
150
R3
150
C2
2.2 F
8
2
R4
provides 4.096V of
150
IC2
1
FROM PC'S
3
3
stable power to IC1
DB1
LTC6903
PRINTER
R
5
and IC2. For optimal
PORT
150
6
4
DB2 4
performance, minimize the lead lengths
5
of bypass capacitors
IC3
CLOCK
C1 and C2 with respect
NC7SZ125
CONNECTOR
s
power
to IC2
2
4
Figure 1
and ground con1
nections. High-speed
3
25
buffer IC3 isolates IC2s
output and prevents
frequency pulling due
PC-programmable wide-range clock source features minimal
to load variations.
component count.
Listing 1 on the Web
version of this Design Idea at OCT and DAC. The program derives
www.edn.com translates a user-supplied the closest values for OCT and
input into a 16 bit, SPI-compatible data DAC by solving the equation:
stream that programs IC1s output fre- f(2OCT)2078/(2(DAC)/1024). At
quency. The LTC6903s output frequen- initial application of power, IC2s output
cy depends on two control coefficients, frequency defaults to 1.039 kHz.
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design
ideas
IS
RON
C5
conduction modethat is, the inductor
22 F
FB
current always remains positive. The outVOUT
VCC
SS PGND AGND
put voltage, VOUT, is equal to DVIN,
R2
R4
1k
where D is the duty-cycle ratio of the
C2
C3
0.5
1 F
0.01 F
buck switch, Q1, and VIN is the input volt12V
age. The duty cycle, D, is equal to
F
i
g
u
r
e
3
TON/TS, where TON is the on-time
Based on National Semiconductors LM5010, this buck-boost regulator operates over a wide inputof Q1 and TS is the switching-frequency
voltage range.
period.
You can reconfigure a buck regulator
into a buck-boost circuit to convert a regulator IC that converts a 10 to 50V where K represents a constant, R3 sets the
positive voltage into a negative voltage positive supply voltage into 12V. Al- buck switchs on-time interval, VIN is the
(Figure 2). The basic component config- though many applications use a fixed input voltage, and VOUT is the magnitude
urations of both circuits are similar, and switching frequency and modulate the of the output voltage. Substitute
the inductor and the rectifier diode are output pulse width, this design features TON1/FS and then solve for FS to yield:
transposed. Because the main switch, Q1, a constant-on-time approach in which
remains in the same location for both the ICs internal output transistor turns
configurations, you can use an IC buck on for an interval thats inversely proporregulator for either topology. Switching tional to the difference between the ciron Q1 applies input voltage VIN across cuits input and output voltage.
Providing that current through L1 repower inductor L1, and current in the inInside IC1, a regulation comparator mains continuous, VOUT remains regulatductor ramps up while Q1 remains on. monitors the output voltage from voltage ed. Because R3 and K are constants, switchWhen Q1 switches off, inductor current divider R1 and R2 and a 2.5V internal ref- ing frequency FS remains constant. This
continues to flow through C1, the load re- erence, and, if the output voltage falls be- relationship holds true provided that the
sistance and D1, producing a negative low the desired value, the comparator current through the inductor remains
output voltage. During Q1s next on-time switches on IC1s output transistor for an continuous.At lighter loading, the current
interval, the output capacitor supplies interval that an on-timer determines:
in the inductor becomes discontinuous
current to the load.
that is, the inductor current drops to zero
Figure 3 shows a low-cost buck-boost
for a portion of the switching cycle. At the
converter based on the LM5010 buckonset of discontinuous operation, the
VIN
VIN
IL
D*TS
D*TS
TS
IQ1
IQ1
D1
D1
VOUT
VOUT
L1
ID1
Q1
TS
Q1
C1
L1
IL
C1
ID1
Figure 1
In the basic buck-regulator circuit, current flows continuously
through inductor L1.
Figure 2
The buck-boost regulator circuit produces a negative output voltage.
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ideas
400 kHz, delivering 12V at approximately 0.5A for 10V input and approximately 1A of output current for 50V input.
Resistor R4 ensures that the minimum
amount of output-ripple voltage necessary for regulationapproximately 25
mVis available.
Fixed-frequency operation without an
oscillator offers a low-cost, easily implemented regulator with no loop-compen-
IC2
KINGBRIGHT
eters that indicate analog levAAF5060PBESEEVG
els via a moving-pointer meter, a
R1
D1
56 4
3
numeric display, or a column of
LEDs typically occupy considerable panGREEN LED
el area and require more than a casual
R2
D2
150 5
glance to read. An indicator lamp or LED
2
6
7
ANALOG
GP0/AN0
GP1/AN1/VREF
takes little space but indicates only an on
INPUT
5
RED LED
4
GP2/TOCKI/AN2/INT
or off condition. However, an unobtruR3
GP3/MCLR/VPP
3
D3
GP4/OSC2/AN3/CLKOUT
68 6
1
sive LED that changes color as a
1
2
Figure 1
VCC
GP5/OSC1/CIN
function of a measured value
BLUE LED
would enable an observer to easily assess
IC1
PIC12F675
5V
the measurement.
The circuit in Figure 1 comprises IC1, Using a minimal number of components, this voltage-to-color converter uses a single rainbow LED
a Microchip PIC12F675 microcontroller to monitor an analog voltage level.
driving IC2, a Kingbright AAF5060PBESEEVG rainbow indicator that contains three ultrabright LED chips (red,
green, and blue) within one package.
Modulating each LEDs duty cycle produces all of the perceivable colors of the
visible spectrum, including white light.
STEPS
Listing 1 at the Web version of this DePER
sign Idea at www.edn.com contains a PIC
14-STEP
FRAME
program for the PicBasic Pro compiler,
which is available from MicroEngineering Labs Inc (www.melabs.com). This
program converts a 0 to 5V input applied
to Pin 3 of IC1 to an 8-bit digital value
that corresponds to a perceived color
containing certain amounts of
Figure 2
red, blue, and green.
A/D COUNTS
Under control of a PWM routine, each
LED flashes for an interval proportional You can alter the color versus input-voltage palette by modifying the firmware.
to its corresponding content of red, green,
or blue. During each PWM frame, an ed, the eyes slow response integrates their (shades of blue, purple, and aqua) denote
LED die receives power for as many as 14 output to create the illusion of a change an input in the 0 to 2.5V range, and hot
steps per frame as the color map of Fig- in intensity proportional to the duty cy- colors (shades of red, orange, yellow, and
ure 2 shows. (You can view the color map cle. The RGB-encoding function in List- white) denote an input in the 2.5 to 5V
at the Web version of this Design Idea at ing 1 assumes that the analog input to IC1 range. You can create different palettes by
www.edn.com.) Although not all LEDs has a zero-signal offset of 2.5V, which changing the primary-color proportions
are necessarily simultaneously illuminat- switches all LEDs off. Cool colors stored in the RGB encoding table.
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TOROIDAL CORE
PLAN
CONNECTOR
(1)
ELEVATION
where Z1 is the impedance of the primary
winding, Z2 is the impedance of the secondary winding N1 is the number of primary turns, and N2 is the number of secondary turns.
Figure 3
Under normal operation with
current flowing in the primary winding, The primary winding (battery cable) passes through transformer T1s center.
the secondary impedance comprises the
low primary-side impedance plus T1s teration of T1s design, but if that data is Also, select a core material that doesnt
leakage reactance. When no current unavailable, you can use Equation 3 to saturate at full primary current.
flows in the primary winding, the num- calculate the inductance.
Note that the cores central area must
ber of turns in the secondary and the
provide clearance for the battery cable
(3)
toroidal core AL (inductance per turn)
(primary winding) and secondary winddetermine the secondary winding L2s
ing. This application uses a Philips 3C85
inductance and number of turns per where e, the effective permeability, equals toroidal ferrite core (part no. TN 16/9.6/
Equation 2:
the magnetic constant, 4107Hm1, I 6.3-3C85) with a secondary winding comis the path length, and A is the cross-sec- prising five turns of 0.2-mm2 insulated
(2)
copper wire. (Philips, however, has distional area in millimeters squared.
Select a core that presents a high val- continued the 3C85 ferrite core. Ferroxwhere N2 is the number of turns around ue of inductance to ensure that the dif- cubes type 3C90 ferrite may serve as a rethe toroidal core.
ference between an open and a closed placement. Specifications are available at
Ferrite-core manufacturers publish in- primary circuit causes a large change in www.ferroxcube.com.) Figure 3 shows the
ductance-per-turndata that simplifies al- relative secondary-winding impedance. completed transformer.
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design
ideas
TPS62300 series of ICs, for example, converts a battery voltage of 2.7 to 6.5V into
a constant current, which you program
using an external resistor and voltage on
its ISET pin. The current that normally
drives the LED instead powers the loop
(Figure 1).
V+
V+
2
IN
VREF
3
OUT
IC2
R1
51.1k
R2
29.4k
V+
0.1 F
0.1 F
3
IC3
4 _
V+
4
5
IC1
R3
150k
RISET
6.49k
5
VISET
2
R4
100k
C8
0.015 F
IC4
TPS60230RGT
1
I
2 SET
3
4
5
6
7
16
EN2
15
EN1
14
GND
13
VIN
12
C2
11
C1
D1
PGND
8 V
OUT
1 F
GND
10
C1+
9
C2+
0.47 F
0.47 F
17
Figure 1
In this circuit, the LED driver drives the 4- to 20-mA current loop proportionate to a sensed temperature of 10C at 4 mA and 50C at 20 mA.
1 F
TWISTED PAIR
RECEIVER
100
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design
ideas
This softwareprogrammable
current source
applies current to
the load in 256
equal increments.
IC1
DIGITAL
POTENTIOMETER
IN+
LOAD
RS
ISHUNT
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