Documente Academic
Documente Profesional
Documente Cultură
ISSN 2278-7763
106
E & TC Department, Acropolis Institute of Research & Technology, RGPV University, Bhopal
1
shardul.anand@gmail.com
INTRODUCTION
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The trend in the recent past shows the RISC processors clearly
outsmarting the earlier CISC processor architectures. The
reasons have been the advantages, such as its simple, flexible
and fixed instruction format and hardwired control logic,
which paves for higher clock speed, by eliminating the need
for microprogramming. The combined advantages of high
speed, low power, area efficient and operation-specific design
possibilities have made the RISC processor ubiquitous. The
main feature of the RISC processor is its ability to support
single cycle operation, meaning that the instruction is fetched
from the instruction memory at the maximum speed of the
memory. RISC processors in general, are designed to achieve
this by pipelining, where there is a possibility of stalling of
clock cycles due to wrong instruction fetch when jump type
instructions are encountered. This reduces the efficiency of
the processors. This paper describes a RISC architecture in
which, single cycle operation is obtained without using a
pipelined design. It averts possible stalling of clock cycles in
effect. The development of CMOS technology provides very
high density and high performance integrated circuits. The
performance provided by the existing devices has created a
never-ending greed for increasingly better performing devices.
This predicts the use of a whole RISC processor as a basic
device by the year 2020.
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Result
The RISC processor described above is designed using
Verilog HDL mixed language and is simulated using Xilinx
ise 14.2. The proper functioning of the processor is validated.
The simulation result shows that the processor is capable of
implementing the given instruction in single clock cycle,
thereby satisfying the basic requirements of the RISC
processor. In order to evaluate the system performance, usage
of synthesis software were used to map the proposed
processor on a target library
Conclusion
The design of a single cycle 16-Bit non-pipelined RISC
processor for its application towards convolution application
has been presented. Novel adder and multiplier structures
have been employed in the RISC architecture. The processor
has been designed for executing the instruction set comprising
of 27 instructions in total. It is shown expandable up to 32
instructions, based on the user requirements. The processor
design promises its use towards any signal processing
applications.
.
Acknowledgment
We place our gratitude on record to the Department of
Electronics and Communication Engineering, Acropolis
Institute of Research & Technology, Indore for the support
rendered to us in carrying out this work.
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