IEEE 2014 VLSI PROJECTS

1 High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1

Using Common Sharing Distributed Arithmetic (IEEE 2014).
2 Improved 8-Point Approximate DCT for Image and Video Compression Requiring
Only 14 Additions (IEEE 2014).
3 Area-Delay Efficient Binary Adders in QCA (IEEE 2014).
4 Areas Delayed Power Efficient Carry-Select Adder (IEEE 2014).
5 Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells (IEEE
2014).
6 Simplifying clock gating logic by matching Factored forms (IEEE 2014).
7 Data encoding techniques for reducing energy Consumption in network-on-chip
(IEEE 2014).
8 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low AdaptationDelay (IEEE 2014).
9 Application-Independent Testing of 3-D Field Programmable Gate Array
Interconnect Faults (IEEE 2014).
10 Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 1, 2n 1, 2n}
(IEEE 2014).
11 Efficient Integer DCT Architectures for HEVC (IEEE 2014).
12 Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for
Efficient FIR Filter Implementation (IEEE 2014).
13 Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata (IEEE
2014).
14 Reverse Converter Design via Parallel-Prefix Adders: Novel Components,
Methodology, and Implementations (IEEE 2014).
15 Low-Complexity Low-Latency Architecture for Matching of Data Encoded With
Hard Systematic Error-Correcting Codes (IEEE 2014).
16 Multifunction Residue Architectures for Cryptography (IEEE 2014).
17 Defense Against Primary User Emulation Attacks in Cognitive Radio Networks
Using Advanced Encryption Standard (IEEE 2014).
18 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic (IEEE 2014).

19 Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive

Algorithm (IEEE 2014).
20 Eliminating Synchronization Latency Using Sequenced Latching (IEEE 2014).
21 Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With
Low Adder-Count (IEEE 2014).
22 Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
(IEEE 2014).
23 Efficient FPGA and ASIC Realizations of DA-Based Reconfigurable FIR Digital Filter
(IEEE 2014).
24 Non binary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping
Algorithm (IEEE 2014).
25 Efficient Algorithm and Architecture for Elliptic Curve Cryptography for Extremely
Constrained Secure Applications (IEEE 2014).
26 An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply
Operator (IEEE 2014).
27 Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent
Activation Function (IEEE 2014).
28 Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool (IEEE
2014).
29 Parallel AES Encryption Engines for Many-Core Processor Arrays (IEEE 2014).
30 Design of Testable Reversible Sequential Circuits (IEEE 2014).
31 Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
(IEEE 2014).
32 A Novel Modulo Adder for 2n-2k- 1Residue Number System (IEEE 2014).
33 Improvement of the Security of ZigBee by a New Chaotic Algorithm (IEEE 2014).
34 CORDIC Based Fast Radix-2 DCT Algorithm (IEEE 2014).
35 Split Radix Algorithm for Length 6mDFT (IEEE 2014).
36 Low-Complexity Multiplier for GF(2m) Based on All-One Polynomials (IEEE 2014).
37 Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on
Distributed Arithmetic (IEEE 2014).
38 Multicarrier Systems Based on Multistage Layered IFFT Structure (IEEE 2014).

39 Design of an Error Detection and Data Recovery Architecture for Motion

Estimation Testing Applications (IEEE 2014).
40 Period Extension and Randomness Enhancement Using High-Throughput
Reseeding-Mixing PRNG (IEEE 2014).
41 Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions
Based on Fast FIR Algorithm (IEEE 2014).
42 Measurement and Evaluation of Power Analysis Attacks on Asynchronous S-Box
(IEEE 2014).
43 Low-Power and Area-Efficient Carry Select Adder (IEEE 2014).
45 Software/Hardware Parallel Long-Period Random Number Generation Framework
Based on the WELL Method (IEEE 2014).
44 A Low-Power Single-Phase Clock Multiband Flexible Divider (IEEE 2014).