4541.

775
TopicsonCompilers

Introduction
to
CGRA

Spring2011

IntroductiontoCGRA

ReconfigurableArchitectures

reconfigurablehardware(reconfigware)

implementspecifichardwarestructuresdynamicallyandondemand

highperformanceatlowpower

outperformgeneralpurposeprocessorsinmanyapplications
byprovidingspacial,parallelandspecializedcomputation
veryinterestingformobile&embeddedsystems

typicalorganization

logicblocksina2Darray

routingresources

IntroductiontoCGRA

ReconfigurableArchitectures

reconfigurablehardware(reconfigware)

bestknownreconfigurablearchitectures:FPGAs

configurationblock:bitlevel

dataroutingthemajorchallenge

reconfigurationisslow

automaticmappingofsequentialCprogramsverydifficult

usuallypartofaSoCdesign

(imagesource:CompilingforReconfigurableComputing:ASurvey,CSUR)

IntroductiontoCGRA

ReconfigurableArchitectures

finegrainedvs.coarsegrainedreconfigurablearchitectures

finegrained

programmableblocksandroutingresourcesatthebitlevel

canbuildanything

12bitfixedpointarithmeticforasignalprocessingapp
14bitbutterflyroutingnetworkforaFFT

coarsegrainedreconfigurablearchitectures(CGRA)

sometimesalsoreferredtoascoarsegrainedreconfigurablearray

programmableblocksandroutingresources>1bit,e.g.,32bit

lessflexiblethanfinegrainedreconfigurablearchitectures

but

easiertoprogram
fastreconfiguration

IntroductiontoCGRA

ReconfigurableArchitectures

finegrainedvs.coarsegrainedreconfigurablearchitectures

finegrained

coarsegrainedreconfigurablearchitectures(CGRA)

(imagesource:CompilingforReconfigurableComputing:ASurvey,CSUR)

IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

CGRA

(source:FineandCoarseGrainReconfigurableComputing,Springer)

programmabilityandflexibility

runmultiplekernelsonthesame
silicondie

supportseveralstandards

upgradability

fasttimetomarket

IntroductiontoCGRA
Coarsegrainedreconfigurablearchitectures

Power
Efficiency
(GOPS/W)

ASIC

100

ASIP

CGRA
10

DSP

0.1

10

Performance
(GOPS)

efficiency

lowpowerconsumption

highperformance

IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

PipeRench(Goldsteinetal.,1999)

naturallymapapplicationstagestoapipelinedreconfigurable
architecture

virtualpipelinestages

physicalpipelinestages

(imagesource:PipeRench:AReconfigurableArchitectureandComputer,IEEE)

IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

PipeRench(Goldsteinetal.,1999)

architecturedescriptionflexible

sourcelanguage:dataflowintermediatelanguage

(imagesource:PipeRench:AReconfigurableArchitectureandComputer,IEEE)

IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

MorphoSys(Singhetal.,2000)

8/16bitFU(reconfigurablecell)array

(imagesource:MorphoSys:AnIntegratedReconfigurableSystemforDataParallelandComputationIntensiveApplications,IEEETC)

IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

MorphoSys(Singhetal.,2000)

detailviewofoneRC(reconfigurablecell)

(imagesource:MorphoSys:AnIntegratedReconfigurableSystemforDataParallelandComputationIntensiveApplications,IEEETC)

IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

MorphoSys(Singhetal.,2000)

configurationofanRC

(imagesource:MorphoSys:AnIntegratedReconfigurableSystemforDataParallelandComputationIntensiveApplications,IEEETC)

IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

MorphoSys(Singhetal.,2000)

systemintegration

(imagesource:MorphoSys:AnIntegratedReconfigurableSystemforDataParallelandComputationIntensiveApplications,IEEETC)

IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

ADRES(Meietal.,2003)

combinedVLIW/CGRAprocessor

(imagesource:ADRES:AnArchitecturewithTightlyCoupledVLIWProcessorandCoarseGrainedReconfigurableMatrix,SpringerLNCS)

IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

ADRES(Meietal.,2003)

reconfigurablecell

(imagesource:ADRES:AnArchitecturewithTightlyCoupledVLIWProcessorandCoarseGrainedReconfigurableMatrix,SpringerLNCS)

IntroductiontoCGRA

Coarsegrainedreconfigurablearchitectures

ADRES(Meietal.,2003)

VLIW/CGAinteraction

(imagesource:ADRES:AnArchitecturewithTightlyCoupledVLIWProcessorandCoarseGrainedReconfigurableMatrix,SpringerLNCS)

IntroductiontoCGRA

CompilingforCGRA

typicallynocontrolflow

innermostloops

ifconversion

moduloscheduling

softwarepipelining

computeIIbasedondataflowgraph

placement&routing

mappingofthedataflowgraphtothearchitecturegraph

severaltechniques

nodecentric:simulatedannealing

edgecentric

IntroductiontoCGRA

FurtherReading:

CompilingforReconfigurableComputing:ASurvey
J.Cardoso,P.Diniz,M.Weinhardt,ACMComputingSurveys
Piperench:AReconfigurableArchitectureandComputer
S.Goldsteinetal.,IEEEComputer
MorphoSys:anintegratedreconfigurablesystemfordataparalleland
computationintensiveapplications
H.Singh,IEEETransactionsonComputers
ADRES:AnArchitecturewithTightlyCoupledVLIWProcessorand
CoarseGrainedReconfigurableMatrix
B.Meietal.,SpringerLNCS