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Standby Current:
- 30 nA @ 1.8V, typical
Operating Current:
- 35 A/MHz, typical
Low-Power Watchdog Timer Current:
- 300 nA @ 1.8V, typical
Preliminary
DS40001715B-page 1
PIC16(L)F1704/8
Digital Peripheral Features (Continued):
I/E
I/E
PIC16(L)F1705
(2)
8192
1024
12
4/1
I/E
PIC16(L)F1707
(3)
2048
256
18
12
2/1
I/E
PIC16(L)F1708
(1)
4096
512
18
12
4/1
I/E
PIC16(L)F1709
(2)
8192
1024
18
12
4/1
I/E
Note 1:
2:
XLP
Debug(1)
PPS
CLC
4/1
MSSP (I2C/SPI)
2/1
EUSART
COG
PWM
CCP
Timers
(8/16-bit)
12
Zero Cross
12
512
Op Amp
256
4096
High-Speed/
Comparators
2048
(1)
8-bit DAC
Data SRAM
(bytes)
(3)
PIC16(L)F1704
Program Memory
Flash (words)
PIC16(L)F1703
Device
I/Os(2)
Debugging Methods: (I) Integrated on Chip; (H) using Debug Header; E using Emulation Header.
One pin is input-only.
Note:
For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
DS40001715B-page 2
Preliminary
PIC16(L)F1704/8
Pin Diagrams
FIGURE 1:
VDD
RA5
RA4
VPP/MCLR/RA3
RC5
RC4
RC3
FIGURE 2:
1
2
3
4
5
6
7
PIC16(L)F1704
14
13
12
11
10
9
8
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
NC
VSS
16
15
14
13
VDD
NC
QFN
1
12 RA0/ICSPDAT
2
11 RA1/ICSPCLK
3 PIC16(L)F1704 10 RA2
4
9 RC0
RC4
RC3
RC2
RC1
5
6
7
8
RA5
RA4
RA3/MCLR/VPP
RC5
Preliminary
DS40001715B-page 3
PIC16(L)F1704/8
FIGURE 3:
20
VSS
19
RA4
18
ICSPCLK/RA1
VPP/MCLR/RA3
17
RA2
RC5
16
RC0
15
RC1
14
RC2
13
RB4
12
RB5
10
11
RB6
RC3
RC6
RC7
RB7
6
7
8
PIC16(L)F1708
RA5
ICSPDAT/RA0
RC4
FIGURE 4:
20
19
18
17
16
RA4
RA5
VDD
VSS
RA0/ICSPDAT
QFN
1
15 RA1/ICSPCLK
2
14 RA2
3 PIC16(L)F1708 13 RC0
4
12 RC1
5
11 RC2
RC7
RB7
RB6
RB5
RB4
6
7
8
9
10
VPP/MCLR/RA3
RC5
RC4
RC3
RC6
DS40001715B-page 4
Preliminary
Op Amp
DAC
Zero Cross
Timers
CCP
COG
MSSP
EUSART
CLC
Interrupt
Pull-up
12
AN0
VREF-
C1IN+
DAC1OUT
IOC
ICSPDAT
12
11
AN1
VREF+
C1IN0C2IN0-
IOC
ICSPCLK
RA2
11
10
AN2
DAC1OUT2
ZCD
T0CKI(1)
COGIN(1)
INT(1)
IOC
RA3
IOC
MCLR
VPP
RA4
AN3
T1G(1)
SOSCO
IOC
CLKOUT
OSC2
RA5
T1CKI(1)
SOSCI
CLCIN3(1)
IOC
CLKIN
OSC1
RC0
10
AN4
C2IN+
OPA1IN+
SCK(1)
SCL(3)
IOC
RC1
AN5
C1IN1C2IN1-
OPA1IN-
SDI(1)
SDA(3)
CLCIN2(1)
IOC
RC2
AN6
C1IN2C2IN2-
OPA1OUT
IOC
RC3
AN7
C1IN3C2IN3-
OPA2OUT
CCP2(1)
SS(1)
CLCIN0(1)
IOC
RC4
OPA2IN-
CK(1)
CLCIN1(1)
IOC
IOC
VDD
VSS
OPA2IN+
VDD
16
VSS
14
13
OUT
Note
(2)
DS40001715B-page 5
1:
2:
3:
CCP1
(1,3)
RX
(3)
C1OUT
CPP1
PWM3OUT
COGA
SDA
CK
CLC1OUT
C2OUT
CPP2
PWM4OUT
COGB
SCL(3)
DT(3)
CLC2OUT
COGC
SDO
TX
CLC3OUT
COGD
SCK
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1704/8
RC5
(1)
Basic
Comparator
13
RA1
PWM
ADC
RA0
Reference
QFN
Preliminary
PDIP/SOIC/SSOP
I/O(2)
TABLE 1:
ADC
Comparator
Op Amp
DAC
Zero Cross
Timers
CCP
PWM
COG
MSSP
EUSART
CLC
Interrupt
Pull-up
19
16
AN0
VREF-
C1IN+
DAC1OUT
IOC
ICSPDAT
RA1
18
15
AN1
VREF+
C1IN0C2IN0-
IOC
ICSPCLK
RA2
17
14
AN2
DAC1OUT2
ZCD
T0CKI(1)
COGIN(1)
INT(1)
IOC
RA3
IOC
MCLR
VPP
RA4
20
AN3
T1G(1)
SOSCO
IOC
CLKOUT
OSC2
RA5
19
T1CKI
SOSCI
CLCIN3(1)
IOC
CLKIN
OSC1
RB4
13
10
AN10
OPA1IN-
SCK(1)
SDA(3)
IOC
RB5
12
AN11
OPA1IN+
RX(1,3)
IOC
IOC
Basic
QFN
RA0
Reference
PDIP/SOIC/
SSOP
Preliminary
I/O(2)
RB6
11
SDI(1)
SCL(3)
RB7
10
CK(1)
IOC
RC0
16
13
AN4
C2IN+
IOC
RC1
15
12
AN5
C1IN1C2IN1-
CLCIN2(1)
IOC
RC2
14
11
AN6
C1IN2C2IN2-
OPA1OUT
IOC
RC3
AN7
C1IN3C2IN3-
OPA2OUT
CCP2(1)
CLCIN0(1)
IOC
RC4
CLCIN1(1)
IOC
RC5
CCP1(1)
IOC
RC6
AN8
OPA2IN-
SS(1)
IOC
RC7
AN9
OPA2IN+
IOC
VDD
18
VDD
VSS
20
17
VSS
C1OUT
CPP1
PWM3OUT
COGA
SDA(3)
CK
CLC1OUT
C2OUT
CPP2
PWM4OUT
COGB
SCL(3)
DT(3)
CLC2OUT
COGC
SDO
TX
CLC3OUT
COGD
SCK
OUT(2)
Note
1:
2:
3:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1704/8
DS40001715B-page 6
TABLE 2:
PIC16(L)F1704/8
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 17
3.0 Memory Organization ................................................................................................................................................................. 19
4.0 Device Configuration .................................................................................................................................................................. 49
5.0 Resets ........................................................................................................................................................................................ 55
6.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 63
7.0 Interrupts .................................................................................................................................................................................... 81
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 95
9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 99
10.0 Flash Program Memory Control ............................................................................................................................................... 105
11.0 I/O Ports ................................................................................................................................................................................... 121
12.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 139
13.0 Interrupt-On-Change ................................................................................................................................................................ 147
14.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 153
15.0 Temperature Indicator Module ................................................................................................................................................. 157
16.0 Comparator Module.................................................................................................................................................................. 159
17.0 Pulse Width Modulation (PWM) ............................................................................................................................................... 169
18.0 Complementary Output Generator (COG) Module................................................................................................................... 175
19.0 Configurable Logic Cell (CLC).................................................................................................................................................. 207
20.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 223
21.0 Operational Amplifier (OPA) Modules ...................................................................................................................................... 237
22.0 8-Bit Digital-to-Analog Converter (DAC1) Module.................................................................................................................... 241
23.0 Zero Cross Detection (ZCD) Module........................................................................................................................................ 245
24.0 Timer0 Module ......................................................................................................................................................................... 249
25.0 Timer1 Module with Gate Control............................................................................................................................................. 253
26.0 Timer2/4/6 Module ................................................................................................................................................................... 265
27.0 Capture/Compare/PWM Modules ............................................................................................................................................ 271
28.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 281
29.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 337
30.0 In-Circuit Serial Programming (ICSP) ............................................................................................................................... 369
31.0 Instruction Set Summary .......................................................................................................................................................... 371
32.0 Electrical Specifications............................................................................................................................................................ 385
33.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 419
34.0 Development Support............................................................................................................................................................... 435
35.0 Packaging Information.............................................................................................................................................................. 439
The Microchip Web Site ..................................................................................................................................................................... 467
Customer Change Notification Service .............................................................................................................................................. 467
Customer Support .............................................................................................................................................................................. 467
Product Identification System ............................................................................................................................................................ 469
Preliminary
DS40001715B-page 7
PIC16(L)F1704/8
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
DS40001715B-page 8
Preliminary
PIC16(L)F1704/8
1.0
DEVICE OVERVIEW
Peripheral
PIC16(L)F1708
DEVICE PERIPHERAL
SUMMARY
PIC16(L)F1704
TABLE 1-1:
Temperature Indicator
CCP2
C1
C2
CLC1
CLC2
CLC3
Comparators
MSSP
Op Amp 1
Op Amp 2
PWM3
PWM4
Timer0
Timer1
Timer2
Timers
Preliminary
DS40001715B-page 9
PIC16(L)F1704/8
FIGURE 1-1:
Program
Flash Memory
RAM
PORTA
PORTB(1)
CLKOUT
Timing
Generation
HFINTOSC/
LFINTOSC
Oscillator
CLKIN
CPU
PORTC
Figure 1-1
MCLR
ZCD
Op Amps
PWM
Timer0
Timer1
Timer2
MSSP
Comparators
COG
Temp.
Indicator
Note
1:
2:
DS40001715B-page 10
ADC
10-Bit
FVR
DAC
CCPs
EUSART
CLCs
PIC16(L)F1708 only.
See applicable chapters for more information on peripherals.
Preliminary
PIC16(L)F1704/8
TABLE 1-2:
Name
RA0/AN0/VREF-/C1IN+/
DAC1OUT/ICSPDAT
RA1/AN1/VREF+/C1IN0-/C2IN0-/
ICSPCLK
RA2/AN2/DAC1OUT2/ZCD/
T0CKI(1)/COGIN(1)/INT(1)
Function
RA0
AN0
RA4/AN3/T1G(1)/SOSCO/
OSC2/CLKOUT
RA5/T1CKI(1)/SOSCI/
CLCIN3(1)/OSC1/CLKIN
RC0/AN4/C2IN+/OPA1IN+/
SCK(1)/SCL(3)
Output
Type
Description
VREF-
AN
C1IN+
AN
AN
DAC1OUT
ICSPDAT
ST
RA1
AN1
AN
VREF+
AN
C1IN0-
AN
C2IN0-
AN
ICSPCLK
ST
RA2
AN2
DAC1OUT2
AN
ZCD
AN
T0CKI
ST
COGIN
ST
INT
RA3/MCLR/VPP
Input
Type
RA3
ST
External interrupt.
MCLR
ST
VPP
HV
Programming voltage.
RA4
AN3
AN
T1G
ST
SOSCO
XTAL
XTAL
OSC2
XTAL
CLKOUT
RA5
T1CKI
ST
SOSCI
XTAL
XTAL
CLCIN3
ST
OSC1
XTAL
CLKIN
ST
RC0
AN4
AN
C2IN+
AN
OPA1IN+
AN
SCK
ST
SCL
I2C
I2C clock.
Preliminary
DS40001715B-page 11
PIC16(L)F1704/8
TABLE 1-2:
Name
Function
RC1/AN5/C1IN1-/C2IN1-/
OPA1IN-/SDI(1)/SDA(3)/
CLCIN2(1)
RC1
(1)
RC5/OPA2IN+/CCP1 /RX
(1)
AN
C2IN1-
AN
OPA1IN-
AN
SDI
CMOS
SDA
I2C
OD
ST
AN6
AN
C1IN2-
AN
C2IN2-
AN
OPA1OUT
AN
RC3
RC4/OPA2IN-/CK(1)/CLCIN1(1)
Description
AN5
RC2
RC3/AN7/C1IN3-/C2IN3-/
OPA2OUT/CCP2(1)/SS(1)/
CLCIN0(1)
Output
Type
C1IN1-
CLCIN2
RC2/AN6/C1IN2-/C2IN2-/
OPA1OUT
Input
Type
AN7
AN
C1IN3-
AN
C2IN3-
AN
AN
OPA2OUT
CCP2
ST
CMOS Capture/Compare/PWM2.
SS
ST
CLCIN0
ST
RC4
OPA2IN-
AN
CK
ST
CLCIN1
ST
RC5
OPA2IN+
AN
CCP1
ST
RX
ST
VDD
VDD
Power
Positive supply.
VSS
VSS
Power
Ground reference.
CMOS Capture/Compare/PWM1.
DS40001715B-page 12
Preliminary
PIC16(L)F1704/8
TABLE 1-2:
Name
OUT(2)
Function
Input
Type
Output
Type
C1OUT
C2OUT
CCP1
CCP2
PWM3OUT
Description
PWM4OUT
COGA
COGB
COGC
COGD
SDA(3)
SDO
SCK
SCL
(3)
I C
OD
OD
TX/CK
DT
CLC1OUT
CLC2OUT
CLC3OUT
Preliminary
DS40001715B-page 13
PIC16(L)F1704/8
TABLE 1-3:
Name
RA0/AN0/VREF-/C1IN+/
DAC1OUT/ICSPDAT
RA1/AN1/VREF+/C1IN0-/C2IN0-/
ICSPCLK
RA2/AN2/DAC1OUT2/ZCD/
T0CKI(1)/COGIN(1)/INT(1)
Function
RA0
AN0
RA4/AN3/T1G(1)/SOSCO/
OSC2/CLKOUT
RA5/T1CKI/SOSCI/
CLCIN3(1)/OSC1/CLKIN
RB4/AN10/OPA1IN-/SCK(1)/
SDA(3)
Output
Type
Description
VREF-
AN
C1IN+
AN
AN
DAC1OUT
ICSPDAT
ST
RA1
AN1
AN
VREF+
AN
C1IN0-
AN
C2IN0-
AN
ICSPCLK
ST
RA2
AN2
DAC1OUT2
AN
ZCD
AN
T0CKI
ST
COGIN
ST
INT
RA3/MCLR/VPP
Input
Type
RA3
ST
External interrupt.
MCLR
ST
VPP
HV
Programming voltage.
RA4
AN3
AN
T1G
ST
SOSCO
XTAL
XTAL
OSC2
XTAL
CLKOUT
RA5
T1CKI
ST
SOSCI
XTAL
XTAL
CLCIN3
ST
OSC1
XTAL
CLKIN
ST
RB4
AN10
AN
OPA1IN-
AN
SCK
ST
SDA
I C
DS40001715B-page 14
Preliminary
PIC16(L)F1704/8
TABLE 1-3:
Name
RB5/AN11/OPA1IN+/RX(1)
Function
RB5
RB7/CK(1)
RC2/AN6/C1IN2-/C2IN2-/
OPA1OUT
AN
ST
RB6
SDI
CMOS
SCL
I2C
OD
I2C clock.
RC0
RC4/CLCIN1
(1)
RC7/AN9/OPA2IN+
VDD
AN
RC1
AN5
AN
C1IN1-
AN
C2IN1-
AN
CLCIN2
ST
RC2
AN6
AN
C1IN2-
AN
C2IN2-
AN
AN
RC3
AN7
AN
C1IN3-
AN
C2IN3-
AN
OPA2OUT
AN
CCP2
ST
CLCIN0
ST
RC4
RC5
CCP1
RC6/AN8/OPA2IN-/SS(1)
ST
C2IN+
CLCIN1
RC5/CCP1(1)
AN4
OPA1OUT
RC3/AN7/C1IN3-/C2IN3-/
OPA2OUT/CCP2(1)/CLCIN0(1)
CK
RC1/AN5/C1IN1-/C2IN1-/
CLCIN2(1)
Description
AN11
RB7
RC0/AN4/C2IN+
Output
Type
OPA1IN+
RX
RB6/SDI(1)/SCL(3)
Input
Type
RC6
CMOS Capture/Compare/PWM2.
CMOS Capture/Compare/PWM1.
AN8
AN
OPA2IN-
AN
SS
ST
RC7
AN9
AN
OPA2IN+
AN
VDD
Power
Positive supply.
Preliminary
DS40001715B-page 15
PIC16(L)F1704/8
TABLE 1-3:
Name
VSS
OUT
(2)
Function
Input
Type
Output
Type
VSS
Power
C1OUT
C2OUT
CCP1
CCP2
PWM3OUT
PWM4OUT
COGA
COGB
COGC
COGD
SDA(3)
SDO
SCK
SCL(3)
I2C
OD
OD
Description
Ground reference.
TX/CK
DT
CLC1OUT
CLC2OUT
CLC3OUT
DS40001715B-page 16
Preliminary
PIC16(L)F1704/8
2.0
FIGURE 2-1:
15
Configuration
15
MUX
Flash
Program
Memory
Program
Bus
16-Level
8 Level Stack
Stack
(13-bit)
(15-bit)
14
Instruction
Instruction Reg
reg
Data Bus
Program Counter
RAM
Program Memory
Read (PMR)
12
RAM Addr
Addr MUX
Direct Addr 7
5
Indirect
Addr
12
12
BSR
FSR Reg
reg
15
FSR0reg
Reg
FSR
FSR1
Reg
FSR reg
15
STATUS Reg
reg
STATUS
8
3
Power-up
Timer
OSC1/CLKIN
OSC2/CLKOUT
Instruction
Decodeand
&
Decode
Control
Timing
Generation
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
MUX
ALU
8
W reg
Internal
Oscillator
Block
VDD
VSS
Preliminary
DS40001715B-page 17
PIC16(L)F1704/8
2.1
2.2
2.3
2.4
Instruction Set
DS40001715B-page 18
Preliminary
PIC16(L)F1704/8
3.0
MEMORY ORGANIZATION
3.1
TABLE 3-1:
PIC16(L)F1704/8
4,096
0FFFh
Preliminary
DS40001715B-page 19
PIC16(L)F1704/8
FIGURE 3-1:
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
3.1.1
3.1.1.1
RETLW Instruction
Stack Level 0
Stack Level 1
Stack Level 15
EXAMPLE 3-1:
constants
BRW
Reset Vector
0000h
Interrupt Vector
0004h
0005h
RETLW
RETLW
RETLW
RETLW
Page 0
On-chip
Program
Memory
07FFh
0800h
Page 1
Rollover to Page 0
0FFFh
1000h
DATA0
DATA1
DATA2
DATA3
RETLW INSTRUCTION
;Add Index in W to
;program counter to
;select data
;Index0 data
;Index1 data
my_function
; LOTS OF CODE
MOVLW
DATA_INDEX
call constants
; THE CONSTANT IS IN W
3.1.1.2
Rollover to Page 1
7FFFh
DS40001715B-page 20
Preliminary
PIC16(L)F1704/8
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
constants
RETLW DATA0
;Index0 data
RETLW DATA1
;Index1 data
RETLW DATA2
RETLW DATA3
my_function
; LOTS OF CODE
MOVLW
LOW constants
MOVWF
FSR1L
MOVLW
HIGH constants
MOVWF
FSR1H
MOVIW
0[FSR1]
;THE PROGRAM MEMORY IS IN W
Preliminary
DS40001715B-page 21
PIC16(L)F1704/8
3.2
3.2.1
12 core registers
20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
TABLE 3-2:
DS40001715B-page 22
CORE REGISTERS
Preliminary
CORE REGISTERS
Addresses
BANKx
x00h or x80h
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
x0Ah or x8Ah
x0Bh or x8Bh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PIC16(L)F1704/8
3.2.1.1
STATUS Register
3.3
REGISTER 3-1:
U-0
U-0
U-0
R-1/q
R-1/q
R/W-0/u
R/W-0/u
R/W-0/u
TO
PD
DC(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand.
Preliminary
DS40001715B-page 23
PIC16(L)F1704/8
3.3.1
FIGURE 3-2:
3.3.2
0Bh
0Ch
Core Registers
(12 bytes)
3.3.3
Memory Region
00h
3.3.2.1
BANKED MEMORY
PARTITIONING
COMMON RAM
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.3.4
DS40001715B-page 24
Preliminary
TABLE 3-3:
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
BANK 2
100h
Core Registers
(Table 3-2)
BANK 3
180h
Core Registers
(Table 3-2)
BANK 4
200h
Core Registers
(Table 3-2)
BANK 5
280h
Core Registers
(Table 3-2)
BANK 6
300h
Core Registers
(Table 3-2)
BANK 7
380h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Preliminary
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
PORTA
PORTC
PIR1
PIR2
PIR3
TMR0
TMR1L
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
TRISA
TRISC
PIE1
PIE2
PIE3
OPTION_REG
PCON
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
LATA
LATC
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
ANSELA
ANSELC
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
WPUA
WPUC
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON
SSP1CON2
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
ODCONA
ODCONC
CCPR1L
CCPR1H
CCP1CON
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
SLRCONA
SLRCONC
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
INLVLA
INLVLC
IOCAP
IOCAN
IOCAF
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
FVRCON
DAC1CON0
DAC1CON1
ZCD1CON
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
VREGCON(1)
RC1REG
TX1REG
SP1BRGL
SP1BRGH
RC1STA
TX1STA
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
SSP1CON3
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
CCPR2L
CCPR2H
CCP2CON
CCPTMRS
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
IOCCP
IOCCN
IOCCF
01Fh
020h
09Fh
0A0h
ADCON2
11Fh
120h
19Fh
1A0h
BAUD1CON
21Fh
220h
29Fh
2A0h
06Fh
070h
General
Purpose
Register
80 Bytes
0EFh
0F0h
Common RAM
70h 7Fh
07Fh
DS40001715B-page 25
Note
16Fh
170h
Accesses
70h 7Fh
0FFh
Legend:
1:
General
Purpose
Register
80 Bytes
1EFh
1F0h
Accesses
70h 7Fh
17Fh
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
26Fh
270h
Accesses
70h 7Fh
1FFh
General
Purpose
Register
80 Bytes
27Fh
36Fh
370h
2EFh
2F0h
Accesses
70h 7Fh
Unimplemented
Read as 0
Accesses
70h 7Fh
2FFh
Unimplemented
Read as 0
3EFh
3F0h
Accesses
70h 7Fh
37Fh
Accesses
70h 7Fh
3FFh
PIC16(L)F1704/8
General
Purpose
Register
80 Bytes
31Fh
39Fh
320h General Purpose 3A0h
Register
32Fh
16 Bytes
330h
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
BANK 2
100h
Core Registers
(Table 3-2)
BANK 3
180h
Core Registers
(Table 3-2)
BANK 4
200h
Core Registers
(Table 3-2)
BANK 5
280h
Core Registers
(Table 3-2)
BANK 6
300h
Core Registers
(Table 3-2)
BANK 7
380h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Preliminary
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
PORTA
PORTB
PORTC
PIR1
PIR2
PIR3
TMR0
TMR1L
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
TRISA
TRISB
TRISC
PIE1
PIE2
PIE3
OPTION_REG
PCON
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
LATA
LATB
LATC
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
ANSELA
ANSELB
ANSELC
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
WPUA
WPUB
WPUC
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON
SSP1CON2
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
ODCONA
ODCONB
ODCONC
CCPR1L
CCPR1H
CCP1CON
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
SLRCONA
SLRCONB
SLRCONC
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
INLVLA
INLVLB
INLVLC
IOCAP
IOCAN
IOCAF
IOCBP
IOCBN
IOCBF
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
FVRCON
DAC1CON0
DAC1CON1
ZCD1CON
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
VREGCON(1)
RC1REG
TX1REG
SP1BRGL
SP1BRGH
RC1STA
TX1STA
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
SSP1CON3
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
CCPR2L
CCPR2H
CCP2CON
CCPTMRS
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
IOCCP
IOCCN
IOCCF
01Fh
020h
09Fh
0A0h
ADCON2
11Fh
120h
19Fh
1A0h
BAUD1CON
21Fh
220h
29Fh
2A0h
General
Purpose
Register
80 Bytes
06Fh
070h
General
Purpose
Register
80 Bytes
0EFh
0F0h
Common RAM
70h 7Fh
07Fh
Note
16Fh
170h
Accesses
70h 7Fh
0FFh
Legend:
1:
General
Purpose
Register
80 Bytes
1EFh
1F0h
Accesses
70h 7Fh
17Fh
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
26Fh
270h
Accesses
70h 7Fh
1FFh
General
Purpose
Register
80 Bytes
27Fh
Unimplemented
Read as 0
36Fh
370h
2EFh
2F0h
Accesses
70h 7Fh
31Fh
39Fh
320h General Purpose 3A0h
Register
32Fh
16 Bytes
330h
Accesses
70h 7Fh
2FFh
Unimplemented
Read as 0
3EFh
3F0h
Accesses
70h 7Fh
37Fh
Accesses
70h 7Fh
3FFh
PIC16(L)F1704/8
DS40001715B-page 26
TABLE 3-4:
TABLE 3-5:
BANK 8
400h
BANK 9
480h
Core Registers
(Table 3-2)
Preliminary
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
TMR4
PR4
T4CON
TMR6
PR6
T6CON
Core Registers
(Table 3-2)
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
Unimplemented
Read as 0
46Fh
470h
DS40001715B-page 27
Unimplemented
Read as 0
86Fh
870h
Unimplemented
Read as 0
8EFh
8F0h
Accesses
70h 7Fh
87Fh
Legend:
Unimplemented
Read as 0
8FFh
9EFh
9F0h
96Fh
970h
Accesses
70h 7Fh
Unimplemented
Read as 0
Accesses
70h 7Fh
97Fh
Unimplemented
Read as 0
Accesses
70h 7Fh
9FFh
Core Registers
(Table 3-2)
B8Bh
B8Ch
Unimplemented
Read as 0
Unimplemented
Read as 0
BEFh
BF0h
B6Fh
B70h
Accesses
70h 7Fh
AFFh
BANK 23
B80h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h 7Fh
A7Fh
BANK 22
B0Bh
B0Ch
AEFh
AF0h
A6Fh
A70h
Accesses
70h 7Fh
7FFh
B00h
Core Registers
(Table 3-2)
Accesses
70h 7Fh
B7Fh
Unimplemented
Read as 0
Accesses
70h 7Fh
BANK 21
A8Bh
A8Ch
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7EFh
7F0h
77Fh
A80h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h 7Fh
BANK 20
A0Bh
A0Ch
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
76Fh
770h
6FFh
A00h
Core Registers
(Table 3-2)
COG1PHR
COG1PHF
COG1BLKR
COG1BLKF
COG1DBR
COG1DBF
COG1CON0
COG1CON1
COG1RIS
COG1RSIM
COG1FIS
COG1FSIM
COG1ASD0
COG1ASD1
COG1STR
BANK 15
780h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h 7Fh
BANK 19
98Bh
98Ch
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
6EFh
6F0h
67Fh
980h
Core Registers
(Table 3-2)
PWM3DCL
PWM3DCH
PWM3CON
PWM4DCL
PWM4DCH
PWM4CON
BANK 14
700h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h 7Fh
BANK 18
90Bh
90Ch
88Bh
88Ch
80Bh
80Ch
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
66Fh
670h
5FFh
900h
Core Registers
(Table 3-2)
BANK 13
680h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h 7Fh
BANK 17
Core Registers
(Table 3-2)
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
5EFh
5F0h
57Fh
880h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h 7Fh
BANK 16
OPA1CON
OPA2CON
56Fh
570h
4FFh
800h
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
BANK 12
600h
Accesses
70h 7Fh
BFFh
PIC16(L)F1704/8
Accesses
70h 7Fh
BANK 11
580h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
4EFh
4F0h
47Fh
BANK 10
500h
BANK 24
C00h
BANK 25
C80h
Core Registers
(Table 3-2)
Preliminary
C0Bh
C0Ch
C0Dh
C0Eh
C0Fh
C10h
C11h
C12h
C13h
C14h
C15h
C16h
C17h
C18h
C19h
C1Ah
C1Bh
C1Ch
C1Dh
C1Eh
C1Fh
C20h
Core Registers
(Table 3-2)
C8Bh
C8Ch
C8Dh
C8Eh
C8Fh
C90h
C91h
C92h
C93h
C94h
C95h
C96h
C97h
C98h
C99h
C9Ah
C9Bh
C9Ch
C9Dh
C9Eh
C9Fh
CA0h
Unimplemented
Read as 0
C6Fh
C70h
Legend:
CEFh
CF0h
D0Bh
D0Ch
D0Dh
D0Eh
D0Fh
D10h
D11h
D12h
D13h
D14h
D15h
D16h
D17h
D18h
D19h
D1Ah
D1Bh
D1Ch
D1Dh
D1Eh
D1Fh
D20h
D6Fh
D70h
D8Bh
D8Ch
D8Dh
D8Eh
D8Fh
D90h
D91h
D92h
D93h
D94h
D95h
D96h
D97h
D98h
D99h
D9Ah
D9Bh
D9Ch
D9Dh
D9Eh
D9Fh
DA0h
Accesses
70h 7Fh
BANK 29
E80h
Core Registers
(Table 3-2)
BANK 30
F00h
Core Registers
(Table 3-2)
BANK 31
F80h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
E0Bh
E0Ch
E0Dh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
See Table 3-7 for
E18h register mapping
E19h
details
E1Ah
E1Bh
E1Ch
E1Dh
E1Eh
E1Fh
E20h
E8Bh
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
See Table 3-7 for
E98h register mapping
E99h
details
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
E9Fh
EA0h
F0Bh
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
See Table 3-7 for
F18h register mapping
F19h
details
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
F8Bh
F8Ch
F8Dh
F8Eh
F8Fh
F90h
F91h
F92h
F93h
F94h
F95h
F96h
F97h
See Table 3-8 for
F98h register mapping
F99h
details
F9Ah
F9Bh
F9Ch
F9Dh
F9Eh
F9Fh
FA0h
E6Fh
E70h
EEFh
EF0h
F6Fh
F70h
FEFh
FF0h
Unimplemented
Read as 0
DEFh
DF0h
D7Fh
BANK 28
E00h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h 7Fh
CFFh
BANK 27
D80h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h 7Fh
CFFh
BANK 26
D00h
Accesses
70h 7Fh
DFFh
Accesses
70h 7Fh
E7Fh
Accesses
70h 7Fh
EFFh
Accesses
70h 7Fh
F7Fh
Accesses
70h 7Fh
FFFh
PIC16(L)F1704/8
DS40001715B-page 28
TABLE 3-6:
PIC16(L)F1704/8
TABLE 3-7:
PPSLOCK
INTPPS
T0CKIPPS
T1CKIPPS
T1GPPS
CCP1PPS
CCP2PPS
COGINPPS
SSPCLKPPS
SSPDATPPS
SSPSSPPS
RXPPS
CKPPS
CLCIN0PPS
CLCIN1PPS
CLCIN2PPS
CLCIN3PPS
Bank 29
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
E9Fh
EA0h
EA1h
EA2h
EA3h
EA4h
EA5h
EA6h
EA7h
EA8h
EA9h
EAAh
EABh
EACh
EADh
EAEh
EAFh
EB0h
EB1h
EB2h
EB3h
EB4h
EB5h
EB6h
EB7h
EB8h
EB9h
EBAh
EBBh
EBCh
EBDh
EBEh
EBFh
EC0h
E6Fh
Bank 30
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
F21h
F22h
F23h
F24h
F25h
F26h
F27h
F28h
F29h
F2Ah
F2Bh
F2Ch
F2Dh
F2Eh
F2Fh
F30h
F31h
F32h
F33h
F34h
F35h
F36h
F37h
F38h
F39h
F3Ah
F3Bh
F3Ch
F3Dh
F3Eh
F3Fh
F40h
CLCDATA
CLC1CON
CLC1POL
CLC1SEL0
CLC1SEL1
CLC1SEL2
CLC1SEL3
CLC1GLS0
CLC1GLS1
CLC1GLS2
CLC1GLS3
CLC2CON
CLC2POL
CLC2SEL0
CLC2SEL1
CLC2SEL2
CLC2SEL3
CLC2GLS0
CLC2GLS1
CLC2GLS2
CLC2GLS3
CLC3CON
CLC3POL
CLC3SEL0
CLC3SEL1
CLC3SEL2
CLC3SEL3
CLC3GLS0
CLC3GLS1
CLC3GLS2
CLC3GLS3
EEFh
Legend:
Note 1:
RA0PPS
RA1PPS
RA2PPS
RA4PPS
RA5PPS
RB4PPS(1)
RB5PPS(1)
RB6PPS(1)
RB7PPS(1)
RC0PPS
RC1PPS
RC2PPS
RC3PPS
RC4PPS
RC5PPS
RC6PPS(1)
RC7PPS(1)
F6Fh
Preliminary
DS40001715B-page 29
PIC16(L)F1704/8
TABLE 3-8:
PIC16(L)F1704/8 MEMORY
MAP, BANK 31
Bank 31
F8Ch
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
Legend:
Unimplemented
Read as 0
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
STKPTR
TOSL
TOSH
= Unimplemented data memory locations,
read as 0,
DS40001715B-page 30
Preliminary
PIC16(L)F1704/8
3.3.5
TABLE 3-9:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
Bank 0-31
x00h or
INDF0
x80h
xxxx xxxx
uuuu uuuu
x01h or
INDF1
x81h
xxxx xxxx
uuuu uuuu
x02h or
PCL
x82h
0000 0000
0000 0000
---1 1000
---q quuu
x03h or
STATUS
x83h
TO
PD
DC
x04h or
FSR0L
x84h
0000 0000
uuuu uuuu
x05h or
FSR0H
x85h
0000 0000
0000 0000
x06h or
FSR1L
x86h
0000 0000
uuuu uuuu
x07h or
FSR1H
x87h
0000 0000
0000 0000
---0 0000
---0 0000
0000 0000
uuuu uuuu
-000 0000
-000 0000
0000 0000
0000 0000
x08h or
BSR
x88h
x09h or
WREG
x89h
x0Bh or
INTCON
x8Bh
GIE
Note
1:
BSR4
BSR3
BSR2
BSR1
BSR0
Working Register
x0Ah or
PCLATH
x8Ah
Legend:
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
Preliminary
DS40001715B-page 31
PIC16(L)F1704/8
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
--uu uuuu
Bank 0
00Ch PORTA
00Dh PORTB(4)
00Eh PORTC
RA5
RA4
RA3
RA2
RA1
RA0
--xx xxxx
RB7
RB6
RB5
RB4
xxxx ----
uuuu ----
RC7(4)
RC6(4)
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
00Fh
Unimplemented
010h
Unimplemented
011h
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
0000 0-00
0000 0-00
012h
PIR2
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
000- 00--
000- 00--
013h
PIR3
COGIF
ZCDIF
CLC3IF
CLC2IF
CLC1IF
--00 -000
--00 -000
014h
Unimplemented
015h
TMR0
016h
017h
018h
T1CON
019h
T1GCON
xxxx xxxx
uuuu uuuu
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
0000 00-0
uuuu uu-u
0000 0x00
uuuu uxuu
TMR1CS<1:0>
TMR1GE
T1GPOL
T1CKPS<1:0>
T1GTM
T1GSPM
T1OSCEN
T1SYNC
T1GGO/
DONE
T1GVAL
TMR1ON
T1GSS<1:0>
01Ah TMR2
Holding Register for the Least Significant Byte of the 16-bit TMR2 Register
xxxx xxxx
uuuu uuuu
01Bh PR2
Holding Register for the Most Significant Byte of the 16-bit TMR2 Register
xxxx xxxx
uuuu uuuu
-000 0000
-000 0000
01Ch T2CON
01Dh
to
01Fh
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
Unimplemented
Bank 1
TRISA5
TRISA4
(2)
TRISA2
TRISA1
TRISA0
--11 1111
--11 1111
08Dh TRISB
TRISB7
TRISB6
TRISB5
TRISB4
1111 ----
1111 ----
08Eh TRISC
TRISC7(4)
TRISC6(4)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
08Ch TRISA
(4)
08Fh
Unimplemented
090h
Unimplemented
091h
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
092h
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
000- 0000
000- 0000
093h
PIE3
COGIE
ZCDIE
CLC3IE
CLC2IE
CLC1IE
--00 -000
--00 -000
094h
095h
OPTION_REG
WPUEN
INTEDG
TMR0CS
TMR0SE
096h
PCON
STKOVF
STKUNF
RWDT
097h
WDTCON
098h
OSCTUNE
099h
OSCCON
SPLLEN
Unimplemented
09Ah OSCSTAT
SOSCR
PSA
1111 1111
1111 1111
BOR
00-1 11qq
qq-q qquu
SWDTEN
--01 0110
--01 0110
PS<2:0>
RMCLR
RI
POR
WDTPS<4:0>
TUN<5:0>
IRCF<3:0>
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
SCS<1:0>
LFIOFR
HFIOFS
--00 0000
--00 0000
0011 1-00
0011 1-00
00q0 --00
qqqq --0q
09Bh ADRESL
xxxx xxxx
uuuu uuuu
09Ch ADRESH
xxxx xxxx
uuuu uuuu
09Dh ADCON0
09Eh ADCON1
ADFM
09Fh ADCON2
Legend:
Note
1:
2:
3:
4:
CHS<4:0>
ADCS<2:0>
TRIGSEL<3:0>
GO/DONE
ADON
ADPREF<1:0>
-000 0000
-000 0000
0000 --00
0000 --00
0000 ----
0000 ----
DS40001715B-page 32
Preliminary
PIC16(L)F1704/8
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 2
10Ch LATA
10Dh LATB(4)
10Eh LATC
LATA5
LATA4
LATA2
LATA1
LATA0
--xx -xxx
--uu -uuu
LATB7
LATB6
LATB5
LATB4
xxxx ----
uuuu ----
LATC7(4)
LATC6(4)
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
xxxx xxxx
uuuu uuuu
10Fh
Unimplemented
110h
Unimplemented
111h
CM1CON0
C1ON
C1OUT
00-0 0100
00-0 0100
112h
CM1CON1
C1INTP
C1INTN
0000 0000
0000 0000
113h
CM2CON0
C2ON
C2OUT
00-0 0100
00-0 0100
114h
CM2CON1
C2INTP
C2INTN
0000 0000
0000 0000
115h
CMOUT
MC2OUT
MC1OUT
---- --00
---- --00
116h
BORCON
SBOREN
BORFS
BORRDY
1x-- ---q
uu-- ---u
117h
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
118h
DAC1CON0
DAC1EN
---
DAC1OE1
DAC1OE2
DAC1PSS<1:0>
119h
DAC1CON1
11Ah
Unimplemented
11Bh
Unimplemented
0-00 --00
0-00 --00
11Ch ZCD1CON
C1POL
C1ZLF
C1SP
C2ZLF
C2SP
C1PCH<2:0>
C2POL
C1HYS
C1SYNC
C1NCH<2:0>
C2PCH<2:0>
C2HYS
C2SYNC
C2NCH<2:0>
ADFVR<1:0>
---
DAC1NSS
DAC1R<7:0>
ZCD1EN
ZCD1OUT
ZCD1POL
ZCD1INTP
ZCD1INTN
0q00 0000
0q00 0000
0-00 00-0
0-00 00-0
0000 0000
0000 0000
11Dh
Unimplemented
11Eh
Unimplemented
11Fh
Unimplemented
Bank 3
18Ch ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
---1 1111
---1 1111
18Dh ANSELB(4)
ANSB5
ANSB4
--11 ----
--11 ----
ANSC7(4)
ANSC6(4)
ANSC5(3)
ANSC4(3)
ANSC3
ANSC2
ANSC1
ANSC0
18Eh ANSELC
1111 1111
1111 1111
18Fh
Unimplemented
190h
Unimplemented
191h
PMADRL
0000 0000
0000 0000
192h
PMADRH
1000 0000
1000 0000
193h
PMDATL
194h
PMDATH
195h
PMCON1
196h
PMCON2
197h
VREGCON(5)
(2)
CFGS
FREE
WRERR
WREN
WR
RD
198h
Unimplemented
199h
RC1REG
19Ah TX1REG
VREGPM
Reserved
xxxx xxxx
uuuu uuuu
--xx xxxx
--uu uuuu
-000 x000
-000 q000
0000 0000
0000 0000
---- --01
---- --01
0000 0000
0000 0000
0000 0000
0000 0000
19Bh SP1BRGL
BRG<7:0>
0000 0000
0000 0000
19Ch SP1BRGH
BRG<15:8>
0000 0000
0000 0000
0000 0000
19Dh RC1STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 0000
19Eh TX1STA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
0000 0010
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
01-0 0-00
01-0 0-00
19Fh BAUD1CON
Legend:
Note
1:
2:
3:
4:
Preliminary
DS40001715B-page 33
PIC16(L)F1704/8
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
--11 1111
Bank 4
20Ch WPUA
20Dh WPUB(4)
20Eh WPUC
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
--11 1111
WPUB7
WPUB6
WPUB5
WPUB4
1111 ----
1111 ----
WPUC7(4)
WPUC6(4)
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
1111 1111
1111 1111
20Fh
Unimplemented
210h
Unimplemented
211h
SSP1BUF
xxxx xxxx
uuuu uuuu
212h
SSP1ADD
0000 0000
0000 0000
213h
SSP1MSK
1111 1111
1111 1111
214h
SSP1STAT
SMP
CKE
D/A
0000 0000
0000 0000
215h
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
0000 0000
0000 0000
216h
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
0000 0000
217h
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
0000 0000
0000 0000
218h
21Fh
ADD<7:0>
MSK<7:0>
S
R/W
UA
BF
SSPM<3:0>
Unimplemented
Bank 5
28Ch ODCONA
28Dh ODCONB(4)
28Eh ODCONC
ODA5
ODA4
ODA2
ODA1
ODA0
--00 -000
--00 -000
ODB7
ODB6
ODB5
ODB4
0000 ----
0000 ----
ODC7(4)
ODC6(4)
ODC5
ODC4
ODC3
ODC2
ODC1
ODC0
0000 0000
0000 0000
28Fh
Unimplemented
290h
Unimplemented
291h
CCPR1L
xxxx xxxx
uuuu uuuu
292h
CCPR1H
293h
CCP1CON
DC1B<1:0>
CCP1M<3:0>
xxxx xxxx
uuuu uuuu
--00 0000
--00 0000
uuuu uuuu
294h
297h
Unimplemented
298h
CCPR2L
xxxx xxxx
299h
CCPR2H
xxxx xxxx
uuuu uuuu
--00 0000
--00 0000
0000 0000
0000 0000
--00 -000
29Ah CCP2CON
29Bh
29Dh
DC2B<1:0>
CCP2M<3:0>
Unimplemented
29Eh CCPTMRS
29Fh
P4TSEL<1:0>
P3TSEL<1:0>
C2TSEL<1:0>
C1TSEL<1:0>
Unimplemented
Bank 6
30Ch SLRCONA
30Dh SLRCONB(4)
30Eh SLRCONC
30Fh
31Fh
Legend:
Note
1:
2:
3:
4:
SLRA5
SLRA4
SLRA2
SLRA1
SLRA0
--00 -000
SLRB7
SLRB6
SLRB5
SLRB4
0000 ----
0000 ----
SLRC7(4)
SLRC6(4)
SLRC5
SLRC4
SLRC3
SLRC2
SLRC1
SLRC0
0000 0000
0000 0000
Unimplemented
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved.
Shaded locations are unimplemented, read as 0.
Unimplemented, read as 1.
PIC16(L)F1704 only.
PIC16(L)F1708 only.
Unimplemented on PIC16LF1704/8.
DS40001715B-page 34
Preliminary
PIC16(L)F1704/8
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 7
38Ch INLVLA
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
--11 1111
--11 1111
INLVLB7
INLVLB6
INLVLB5
INLVLB4
1111 ----
1111 ----
38Eh INLVLC
INLVLC7(4)
INLVLC6(4)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
1111 1111
1111 1111
38Fh
Unimplemented
390h
Unimplemented
391h
IOCAP
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
--00 0000
--00 0000
392h
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
--00 0000
--00 0000
393h
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
--00 0000
--00 0000
394h
IOCBP(4)
IOCBP7
IOCBP6
IOCBP5
IOCBP4
0000 ----
0000 ----
395h
IOCBN(4)
IOCBN7
IOCBN6
IOCBN5
IOCBN4
0000 ----
0000 ----
396h
IOCBF(4)
IOCBF7
IOCBF6
IOCBF5
IOCBF4
0000 ----
0000 ----
397h
IOCCP
IOCCP7(4)
IOCCP6(4)
IOCCP5
IOCCP4
IOCCP3
IOCCP2
IIOCCP1
IOCCP0
0000 0000
0000 0000
398h
IOCCN
IOCCN7(4)
IOCCN6(4)
IOCCN5
IOCCN4
IOCCN3
IOCCN2
IIOCCN1
IOCCN0
0000 0000
0000 0000
399h
IOCCF
IOCCF7(4)
IOCCF6(4)
IOCCF5
IOCCF4
IOCCF3
IOCCF2
IIOCCF1
IOCCF0
0000 0000
0000 0000
Unimplemented
Unimplemented
uuuu uuuu
38Dh INLVLB(4)
39Ah
39Fh
Bank 8
40Ch
414h
415h
TMR4
Holding Register for the Least Significant Byte of the 16-bit TMR4 Register
xxxx xxxx
416h
PR4
Holding Register for the Most Significant Byte of the 16-bit TMR4 Register
xxxx xxxx
uuuu uuuu
417h
T4CON
-000 0000
-000 0000
uuuu uuuu
418h
41Bh
T4OUTPS<3:0>
TMR4ON
T4CKPS<1:0>
Unimplemented
41Ch TMR6
Holding Register for the Least Significant Byte of the 16-bit TMR6 Register
xxxx xxxx
41Dh PR6
Holding Register for the Most Significant Byte of the 16-bit TMR6 Register
xxxx xxxx
uuuu uuuu
-000 0000
-000 0000
Unimplemented
Unimplemented
Unimplemented
00-0 --00
00-0 --00
00-0 --00
00-0 --00
41Eh T6CON
41Fh
T6OUTPS<3:0>
TMR6ON
T6CKPS<1:0>
Bank 9
48Ch
to
49Fh
Bank 10
50Ch
510h
511h
OPA1CON
512h
514h
515h
OPA2CON
516h
51Fh
Legend:
Note
1:
2:
3:
4:
OPA1EN
OPA1SP
OPA1UG
OPA1PCH<1:0>
Unimplemented
OPA2EN
OPA2SP
OPA2UG
OPA2PCH<1:0>
Unimplemented
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved.
Shaded locations are unimplemented, read as 0.
Unimplemented, read as 1.
PIC16(L)F1704 only.
PIC16(L)F1708 only.
Unimplemented on PIC16LF1704/8.
Preliminary
DS40001715B-page 35
PIC16(L)F1704/8
TABLE 3-10:
Addr
Name
Value on all
other
Resets
Unimplemented
Unimplemented
xx-- ----
uu-- ----
xxxx xxxx
uuuu uuuu
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 11
D8Ch
to
DADh
Bank 12
60Ch
to
616h
617h
PWM3DCL
618h
PWM3DCH
619h
PWM3CON
PWM3DC<1:0>
PWM3EN
0-x0 ----
u-uu ----
00-- ----
uu-- ----
0000 0000
uuuu uuuu
0-x0 ----
u-uu ----
Unimplemented
Unimplemented
PWM4DC<1:0>
PWM3OUT PWM3POL
61Bh PWM4DCH
61Dh
61Fh
PWM3DC<9:2>
61Ah PWM4DCL
61Ch PWM4CON
PWM4DC<9:2>
PWM4EN
PWM4OUT PWM4POL
Bank 13
68Ch
to
690h
691h
COG1PHR
--xx xxxx
--uu uuuu
692h
COG1PHF
--xx xxxx
--uu uuuu
693h
COG1BLKR
--xx xxxx
--uu uuuu
694h
COG1BLKF
--xx xxxx
--uu uuuu
695h
COG1DBR
--xx xxxx
--uu uuuu
696h
COG1DBF
--xx xxxx
--uu uuuu
697h
COG1CON0
G1EN
G1LD
00-0 0000
00-0 0000
698h
COG1CON1
G1RDBS
G1FDBS
G1POLA
00-- 0000
00-- 0000
-000 0000
699h
G1CS<1:0>
G1POLD
G1MD<2:0>
G1POLC
G1POLB
G1RIS6
G1RIS5
G1RIS4
G1RIS3
G1RIS2
G1RIS1
G1RIS0
-000 0000
69Ah COG1RSIM
G1RSIM6
G1RSIM5
G1RSIM4
G1RSIM3
G1RSIM2
G1RSIM1
G1RSIM0
-000 0000
-000 0000
69Bh COG1FIS
-000 0000
-000 0000
COG1RIS
G1FIS6
G1FIS5
G1FIS4
G1FIS3
G1FIS2
G1FIS1
G1FIS0
G1FSIM5
G1FSIM4
G1FSIM3
G1FSIM2
G1FSIM1
G1FSIM0
-000 0000
-000 0000
0001 01--
0001 01--
G1AS1E
G1AS0E
---- 0000
---- 0000
G1STRA
0000 0001
0000 0001
69Ch COG1FSIM
G1FSIM6
69Dh COG1ASD0
G1ASE
G1ARSEN
69Eh COG1ASD1
69Fh COG1STR
G1SDATD
G1SDATC
G1ASDBD<1:0>
G1SDATB
G1SDATA
G1ASDAC<1:0>
G1AS3E
G1STRD
G1AS2E
G1STRC
G1STRB
Bank 14-27
x0Ch/
x8Ch
x1Fh/
x9Fh
Legend:
Note
1:
2:
3:
4:
Unimplemented
DS40001715B-page 36
Preliminary
PIC16(L)F1704/8
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
---- ---0
---- ---0
Bank 28
E0Ch
E0Eh
E0Fh
Unimplemented
PPSLOCK
E10h
INTPPS
INTPPS<4:0>
---0 0010
---u uuuu
E11h
T0CKIPPS
T0CKIPPS<4:0>
---0 0010
---u uuuu
E12h
T1CKIPPS
T1CKIPPS<4:0>
---0 0101
---u uuuu
E13h
T1GPPS
T1GPPS<4:0>
---0 0100
---u uuuu
E14h
CCP1PPS
CCP1PPS<4:0>
---1 0101
---u uuuu
E15h
CCP2PPS
CCP2PPS<4:0>
---1 0011
---u uuuu
E16h
E17h
COGINPPS
E18h
E1Fh
PPSLOCKED
Unimplemented
COGINPPS<4:0>
Unimplemented
E20h
SSPCLKPPS
E21h
SSPDATPPS
E22h
SSPSSPPS
E23h
---0 0010
---u uuuu
SSPCLKPPS<4:0>
SSPCLKPPS<4:0>
SSPDATPPS<4:0>
SSPDATPPS<4:0>
SSPSSPPS<4:0>
SSPSSPPS<4:0>
RXPPS<4:0>
RXPPS<4:0>
CKPPS<4:0>
CKPPS<4:0>
Unimplemented
E24h
RXPPS
E25h
CKPPS
E26h
Unimplemented
E27h
Unimplemented
E28h
CLCIN0PPS
CLCIN0PPS<4:0>
---1 0011
---u uuuu
E29h
CLCIN1PPS
CLCIN1PPS<4:0>
---1 0100
---u uuuu
E2Ah
CLCIN2PPS
CLCIN2PPS<4:0>
---1 0001
---u uuuu
CLCIN3PPS
CLCIN3PPS<4:0>
---0 0101
---u uuuu
E2Bh
E2Ch
to
E7Fh
Legend:
Note
1:
2:
3:
4:
Unimplemented
Preliminary
DS40001715B-page 37
PIC16(L)F1704/8
TABLE 3-10:
Addr
Name
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bit 6
Bit 5
RA0PPS<4:0>
---0 0000
---u uuuu
Bank 29
E8Ch
E8Fh
Unimplemented
E90h
RA0PPS
E91h
RA1PPS
RA1PPS<4:0>
---0 0000
---u uuuu
E92h
RA2PPS
RA2PPS<4:0>
---0 0000
---u uuuu
E93h
Unimplemented
E94h
RA4PPS
E95h
RA5PPS
RA4PPS<4:0>
---0 0000
---u uuuu
RA5PPS<4:0>
---0 0000
---u uuuu
E96h
Unimplemented
E97h
Unimplemented
E98h
Unimplemented
E99h
Unimplemented
E9Ah
Unimplemented
E9Bh
Unimplemented
E9Ch
(4)
RB4PPS
RB4PPS<4:0>
---0 0000
---u uuuu
E9Dh
RB5PPS(4)
RB5PPS<4:0>
---0 0000
---u uuuu
E9Eh
(4)
RB6PPS
RB6PPS<4:0>
---0 0000
---u uuuu
E9Fh
RB7PPS(4)
RB7PPS<4:0>
---0 0000
---u uuuu
EA0h
RC0PPS
RC0PPS<4:0>
---0 0000
---u uuuu
EA1h
RC1PPS
RC1PPS<4:0>
---0 0000
---u uuuu
EA2h
RC2PPS
RC2PPS<4:0>
---0 0000
---u uuuu
EA3h
RC3PPS
RC3PPS<4:0>
---0 0000
---u uuuu
EA4h
RC4PPS
RC4PPS<4:0>
---0 0000
---u uuuu
EA5h
RC5PPS
RC5PPS<4:0>
---0 0000
---u uuuu
EA6h
(4)
RC6PPS
RC6PPS<4:0>
---0 0000
---u uuuu
EA7h
RC7PPS(4)
RC7PPS<4:0>
---0 0000
---u uuuu
EA8h
EEFh
Legend:
Note
1:
2:
3:
4:
Unimplemented
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved.
Shaded locations are unimplemented, read as 0.
Unimplemented, read as 1.
PIC16(L)F1704 only.
PIC16(L)F1708 only.
Unimplemented on PIC16LF1704/8.
DS40001715B-page 38
Preliminary
PIC16(L)F1704/8
TABLE 3-10:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
MLC3OUT
MLC2OUT
MLC1OUT
---- -000
---- -000
F10h CLC1CON
LC1EN
LC1OUT
LC1INTP
0-x0 0000
0-00 0000
F11h
LC1POL
LC1G1POL
x--- xxxx
0--- uuuu
F12h CLC1SEL0
LC1D1S<4:0>
---x xxxx
---u uuuu
F13h CLC1SEL1
LC1D2S<4:0>
---x xxxx
---u uuuu
F14h CLC1SEL2
LC1D3S<4:0>
---x xxxx
---u uuuu
F15h CLC1SEL3
LC1D4S<4:0>
---x xxxx
---u uuuu
Addr
Name
Bit 7
Bank 30
F0Ch
F0Eh
Unimplemented
F0Fh CLCDATA
CLC1POL
LC1INTN
LC1MODE<2:0>
F16h CLC1GLS0
LC1G1D1N
xxxx xxxx
uuuu uuuu
F17h CLC1GLS1
LC1G2D1N
xxxx xxxx
uuuu uuuu
F18h CLC1GLS2
LC1G3D1N
xxxx xxxx
uuuu uuuu
F19h CLC1GLS3
LC1G4D1N
xxxx xxxx
uuuu uuuu
F1Ah CLC2CON
LC2EN
LC2OUT
LC2INTP
F1Bh CLC2POL
LC2POL
F1Ch CLC2SEL0
F1Dh CLC2SEL1
F1Eh CLC2SEL2
F1Fh CLC2SEL3
LC2INTN
LC2MODE<2:0>
0-00 0000
0-00 0000
0--- xxxx
0--- uuuu
LC2D1S<4:0>
---x xxxx
---u uuuu
LC2D2S<4:0>
---x xxxx
---u uuuu
LC2D3S<4:0>
---x xxxx
---u uuuu
LC2D4S<4:0>
---x xxxx
---u uuuu
LC2G1POL
F20h CLC2GLS0
LC2G1D1N
xxxx xxxx
uuuu uuuu
F21h CLC2GLS1
LC2G2D1N
xxxx xxxx
uuuu uuuu
F22h CLC2GLS2
LC2G3D1N
xxxx xxxx
uuuu uuuu
F23h CLC2GLS3
LC2G4D1N
xxxx xxxx
uuuu uuuu
F24h CLC3CON
LC3EN
LC3OUT
LC3INTP
F25h CLC3POL
LC3POL
F26h CLC3SEL0
F27h CLC3SEL1
F28h CLC3SEL2
F29h CLC3SEL3
LC3INTN
LC3MODE<2:0>
0-00 0000
0-00 0000
0--- xxxx
0--- uuuu
LC3D1S<4:0>
---x xxxx
---u uuuu
LC3D2S<4:0>
---x xxxx
---u uuuu
LC3D3S<4:0>
---x xxxx
---u uuuu
LC3D4S<4:0>
---x xxxx
---u uuuu
LC3G1POL
F2Ah CLC3GLS0
LC3G1D1N
xxxx xxxx
uuuu uuuu
F2Bh CLC3GLS1
LC3G2D1N
xxxx xxxx
uuuu uuuu
F2Ch CLC3GLS2
LC3G3D1N
xxxx xxxx
uuuu uuuu
F2Dh CLC3GLS3
LC3G4D1N
xxxx xxxx
uuuu uuuu
F2Eh
F6Fh
Unimplemented
Legend:
Note
1:
2:
3:
4:
Preliminary
DS40001715B-page 39
PIC16(L)F1704/8
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
---- -xxx
---- -uuu
xxxx xxxx
uuuu uuuu
---x xxxx
---u uuuu
-xxx xxxx
uuuu uuuu
Bank 31
F8Ch
to
FE3h
Unimplemented
FE4h STATUS_
SHAD
FE5h WREG_
SHAD
DC
FE6h BSR_SHAD
FE7h PCLATH_
SHAD
FE8h FSR0L_
SHAD
xxxx xxxx
uuuu uuuu
FE9h FSR0H_
SHAD
xxxx xxxx
uuuu uuuu
FEAh FSR1L_
SHAD
xxxx xxxx
uuuu uuuu
FEBh FSR1H_
SHAD
xxxx xxxx
uuuu uuuu
FECh
Unimplemented
FEDh STKPTR
FEEh TOSL
Note
1:
2:
3:
4:
FEFh TOSH
Legend:
---1 1111
---1 1111
xxxx xxxx
uuuu uuuu
-xxx xxxx
-uuu uuuu
DS40001715B-page 40
Preliminary
PIC16(L)F1704/8
3.4
3.4.3
FIGURE 3-3:
PC
LOADING OF PC IN
DIFFERENT SITUATIONS
14
PCH
14
PCH
PCL
PCLATH
PC
ALU Result
PCL
14
11
PCLATH
14
PCH
PCL
PCH
CALLW
W
PCL
BRW
PCH
BRANCHING
PC + W
14
3.4.4
15
PC
The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
OPCODE <10:0>
PC
PC
Instruction with
PCL as
Destination
GOTO, CALL
PCLATH
PCL
0
BRA
15
PC + OPCODE <8:0>
3.4.1
MODIFYING PCL
3.4.2
COMPUTED GOTO
Preliminary
DS40001715B-page 41
PIC16(L)F1704/8
3.5
Stack
3.5.1
Note:
FIGURE 3-4:
TOSH:TOSL
0x0F
STKPTR = 0x1F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
TOSH:TOSL
DS40001715B-page 42
0x1F
0x0000
Preliminary
STKPTR = 0x1F
PIC16(L)F1704/8
FIGURE 3-5:
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL
FIGURE 3-6:
0x00
Return Address
STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
TOSH:TOSL
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
Preliminary
STKPTR = 0x06
DS40001715B-page 43
PIC16(L)F1704/8
FIGURE 3-7:
TOSH:TOSL
3.5.2
0x0F
Return Address
0x0E
Return Address
0x0D
Return Address
0x0C
Return Address
0x0B
Return Address
0x0A
Return Address
0x09
Return Address
0x08
Return Address
0x07
Return Address
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
STKPTR = 0x10
OVERFLOW/UNDERFLOW RESET
3.6
Indirect Addressing
DS40001715B-page 44
Preliminary
PIC16(L)F1704/8
FIGURE 3-8:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR
Address
Range
Reserved
0x7FFF
0x8000
0x0000
Program
Flash Memory
0xFFFF
Note:
0x7FFF
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
Preliminary
DS40001715B-page 45
PIC16(L)F1704/8
3.6.1
FIGURE 3-9:
BSR
Indirect Addressing
From Opcode
7
0
Bank Select
Location Select
0x00
FSRxH
0
FSRxL
0
Bank Select
11111
Bank 31
Location Select
0x7F
DS40001715B-page 46
Preliminary
PIC16(L)F1704/8
3.6.2
3.6.3
FIGURE 3-10:
7
FSRnH
0 0 1
FSRnL
FIGURE 3-11:
7
1
FSRnH
PROGRAM FLASH
MEMORY MAP
0
Location Select
Location Select
0x2000
FSRnL
0x8000
0x0000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x29AF
0xF6F
Preliminary
0xFFFF
0x7FFF
DS40001715B-page 47
PIC16(L)F1704/8
NOTES:
DS40001715B-page 48
Preliminary
PIC16(L)F1704/8
4.0
DEVICE CONFIGURATION
4.1
Configuration Words
Preliminary
DS40001715B-page 49
PIC16(L)F1704/8
4.2
REGISTER 4-1:
R/P-1
R/P-1
FCMEN
IESO
CLKOUTEN
R/P-1
R/P-1
U-1
BOREN<1:0>
bit 13
R/P-1
(1)
CP
R/P-1
R/P-1
MCLRE
PWRTE
bit 8
R/P-1
R/P-1
R/P-1
WDTE<1:0>
R/P-1
R/P-1
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
0 = Bit is cleared
1 = Bit is set
bit 13
bit 12
bit 11
bit 10-9
bit 8
Unimplemented: Read as 1
bit 7
bit 6
bit 5
bit 4-3
DS40001715B-page 50
Preliminary
PIC16(L)F1704/8
REGISTER 4-1:
bit 2-0
Note 1:
Preliminary
DS40001715B-page 51
PIC16(L)F1704/8
REGISTER 4-2:
(1)
R/P-1
DEBUG
R/P-1
(2)
LPBOR
R/P-1
(3)
BORV
R/P-1
R/P-1
STVREN
PLLEN
bit 13
bit 8
R/P-1
U-1
U-1
U-1
U-1
R/P-1
ZCDDIS
PPS1WAY
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
0 = Bit is cleared
1 = Bit is set
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-3
Unimplemented: Read as 1
bit 2
bit 1-0
Note 1:
2:
3:
The LVP bit cannot be programmed to 0 when Programming mode is entered via LVP.
The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers
and programmers. For normal device operation, this bit should be maintained as a 1.
See VBOR parameter for specific trip point voltages.
DS40001715B-page 52
Preliminary
PIC16(L)F1704/8
4.3
Code Protection
4.3.1
4.4
Write Protection
4.5
User ID
Preliminary
DS40001715B-page 53
PIC16(L)F1704/8
4.6
4.7
REGISTER 4-3:
DEV<13:8>
bit 13
R
bit 8
R
DEV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
1 = Bit is set
bit 13-0
0 = Bit is cleared
DEV<13:0>: Device ID bits
Device
DEVID<13:0> Values
PIC16F1704
PIC16LF1704
PIC16F1708
PIC16LF1708
REGISTER 4-4:
REV<13:8>
bit 13
R
bit 8
R
REV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
1 = Bit is set
bit 13-0
0 = Bit is cleared
REV<13:0>: Revision ID bits
DS40001715B-page 54
Preliminary
PIC16(L)F1704/8
5.0
RESETS
FIGURE 5-1:
MCLRE
VPP/MCLR
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
BOR
Active(1)
Brown-out
Reset
Done
LFINTOSC
LPBOR
Reset
Note 1:
PWRT
PWRTE
Preliminary
DS40001715B-page 55
PIC16(L)F1704/8
5.1
5.2
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
5.1.1
TABLE 5-1:
BOREN<1:0>
SBOREN
Device Mode
BOR Mode
11
Active
10
Awake
Active
Sleep
Disabled
Active
Disabled
Disabled
01
00
Note 1: In these specific cases, Release of POR and Wake-up from Sleep, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
5.2.1
BOR IS ALWAYS ON
5.2.3
5.2.2
DS40001715B-page 56
Preliminary
PIC16(L)F1704/8
FIGURE 5-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
TPWRT(1)
VDD
VBOR
Internal
Reset
< TPWRT
TPWRT(1)
VDD
VBOR
Internal
Reset
Note 1:
5.3
TPWRT(1)
REGISTER 5-1:
R/W-1/u
R/W-0/u
U-0
U-0
U-0
U-0
U-0
R-q/u
SBOREN
BORFS(1)
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-1
Unimplemented: Read as 0
bit 0
Note 1:
Preliminary
DS40001715B-page 57
PIC16(L)F1704/8
5.4
5.6
5.4.1
ENABLING LPBOR
5.4.1.1
5.5
MCLR
5.7
RESET Instruction
5.8
5.9
5.10
TABLE 5-2:
MCLR CONFIGURATION
MCLRE
LVP
MCLR
Disabled
Enabled
Enabled
5.5.1
MCLR ENABLED
MCLR DISABLED
DS40001715B-page 58
Start-up Sequence
5.5.2
5.11
Note:
Power-Up Timer
1.
2.
3.
The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See
Section 6.0 Oscillator Module (with Fail-Safe
Clock Monitor) for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low
long enough, the Power-up Timer and oscillator
start-up timer will expire. Upon bringing MCLR high, the
device will begin execution after 10 FOSC cycles (see
Figure 5-3). This is useful for testing purposes or to
synchronize more than one device operating in parallel.
Preliminary
PIC16(L)F1704/8
FIGURE 5-3:
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Internal Oscillator
Oscillator
FOSC
FOSC
Preliminary
DS40001715B-page 59
PIC16(L)F1704/8
5.12
TABLE 5-3:
RMCLR
RI
POR
BOR
TO
PD
Condition
Power-on Reset
Brown-out Reset
WDT Reset
TABLE 5-4:
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-- 110x
0000h
---u uuuu
uu-- 0uuu
0000h
---1 0uuu
uu-- 0uuu
WDT Reset
0000h
---0 uuuu
uu-- uuuu
PC + 1
---0 0uuu
uu-- uuuu
Brown-out Reset
0000h
---1 1uuu
00-- 11u0
---1 0uuu
uu-- uuuu
Condition
PC + 1
(1)
0000h
---u uuuu
uu-- u0uu
0000h
---u uuuu
1u-- uuuu
0000h
---u uuuu
u1-- uuuu
DS40001715B-page 60
Preliminary
PIC16(L)F1704/8
5.13
5.14
REGISTER 5-2:
R/W/HS-0/q
R/W/HS-0/q
U-0
STKOVF
STKUNF
R/W/HC-1/q R/W/HC-1/q
RWDT
R/W/HC-1/q
R/W/HC-q/u
R/W/HC-q/u
RI
POR
BOR
RMCLR
bit 7
bit 0
Legend:
HC = Bit is cleared by hardware
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS40001715B-page 61
PIC16(L)F1704/8
TABLE 5-5:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON
SBOREN
BORFS
BORRDY
57
PCON
STKOVF
STKUNF
RWDT
RMCLR
RI
POR
BOR
61
STATUS
TO
PD
DC
23
WDTCON
SWDTEN
102
WDTPS<4:0>
Legend: = unimplemented location, read as 0. Shaded cells are not used by Resets.
DS40001715B-page 62
Preliminary
PIC16(L)F1704/8
6.0
6.1
Overview
Preliminary
DS40001715B-page 63
PIC16(L)F1704/8
SIMPLIFIED PIC MCU CLOCK SOURCE BLOCK DIAGRAM
FIGURE 6-1:
Secondary
Oscillator Timer1
SOSCO
T1OSCEN
Enable
Oscillator
SOSCI
T1OSC
01
External
Oscillator
OSC2
0
Sleep
00
PRIMUX
OSC1
4 x PLL
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
500 kHz
Source
PLLMUX
500 kHz
(MFINTOSC)
31 kHz
Source
INTOSC
1111
SCS<1:0>
31 kHz
0000
31 kHz (LFINTOSC)
Inputs
SCS
FOSC<2:0>
PLLEN or
SPLLEN
0
=100
=00
100
00
DS40001715B-page 64
1
0
1X
MUX
16 MHz
(HFINTOSC)
Postscaler
Internal
Oscillator
Block
FOSC
To CPU and
Peripherals
IRCF<3:0>
HFPLL
Sleep
Outputs
IRCF
PRIMUX
PLLMUX
=1110
1110
Preliminary
PIC16(L)F1704/8
6.2
6.2.1
FIGURE 6-2:
OSC1/CLKIN
Clock from
Ext. System
PIC MCU
FOSC/4 or I/O(1)
Note 1:
OSC2/CLKOUT
6.2.1.1
EC Mode
6.2.1.2
Preliminary
DS40001715B-page 65
PIC16(L)F1704/8
FIGURE 6-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 6-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
PIC MCU
PIC MCU
OSC1/CLKIN
C1
C1
To Internal
Logic
Quartz
Crystal
C2
OSC1/CLKIN
RS(1)
RF(2)
Sleep
RP(3)
OSC2/CLKOUT
2:
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Application Notes:
DS40001715B-page 66
RF(2)
C2 Ceramic
RS(1)
Resonator
Note 1:
To Internal
Logic
Note 1:
Sleep
OSC2/CLKOUT
6.2.1.3
Preliminary
PIC16(L)F1704/8
6.2.1.4
4x PLL
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
6.2.1.5
Secondary Oscillator
FIGURE 6-5:
QUARTZ CRYSTAL
OPERATION
(SECONDARY
OSCILLATOR)
PIC MCU
SOSCI
C1
To Internal
Logic
32.768 kHz
Quartz
Crystal
C2
SOSCO
Preliminary
DS40001715B-page 67
PIC16(L)F1704/8
6.2.1.6
External RC Mode
6.2.2
The external Resistor-Capacitor (EXTRC) mode supports the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.
The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
CLKOUTEN bit in Configuration Words.
Figure 6-6 shows the external RC mode connections.
FIGURE 6-6:
EXTERNAL RC MODES
VDD
PIC MCU
REXT
OSC1/CLKIN
Internal
Clock
CEXT
VSS
FOSC/4 or I/O(1)
OSC2/CLKOUT
2.
3.
DS40001715B-page 68
Preliminary
PIC16(L)F1704/8
6.2.2.1
HFINTOSC
6.2.2.3
MFINTOSC
The
Medium-Frequency
Internal
Oscillator
(MFINTOSC) is a factory calibrated 500 kHz internal
clock source. The frequency of the MFINTOSC can be
altered via software using the OSCTUNE register
(Register 6-3).
The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 6-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 6.2.2.7 Internal
Oscillator Clock Switch Timing for more information.
The MFINTOSC is enabled by:
Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
FOSC<2:0> = 100, or
Set the System Clock Source (SCS) bits of the
OSCCON register to 1x
6.2.2.4
LFINTOSC
6.2.2.2
Preliminary
DS40001715B-page 69
PIC16(L)F1704/8
6.2.2.5
6.2.2.6
Note:
DS40001715B-page 70
Preliminary
PIC16(L)F1704/8
6.2.2.7
5.
6.
7.
Preliminary
DS40001715B-page 71
PIC16(L)F1704/8
FIGURE 6-7:
HFINTOSC/
MFINTOSC
HFINTOSC/
MFINTOSC
Start-up Time
2-cycle Sync
Running
LFINTOSC
0
IRCF <3:0>
System Clock
HFINTOSC/
MFINTOSC
HFINTOSC/
MFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
System Clock
LFINTOSC
HFINTOSC/MFINTOSC
LFINTOSC
Start-up Time
2-cycle Sync
Running
HFINTOSC/
MFINTOSC
IRCF <3:0>
=0
System Clock
DS40001715B-page 72
Preliminary
PIC16(L)F1704/8
6.3
Clock Switching
6.3.3
SECONDARY OSCILLATOR
6.3.1
6.3.4
6.3.2
Preliminary
DS40001715B-page 73
PIC16(L)F1704/8
6.4
6.4.1
TABLE 6-1:
Switch From
Switch To
Frequency
Oscillator Delay
LFINTOSC(1)
Sleep/POR
MFINTOSC(1)
HFINTOSC(1)
31 kHz
31.25 kHz-500 kHz
31.25 kHz-16 MHz
Sleep/POR
EC, RC(1)
DC 32 MHz
2 cycles
LFINTOSC
EC,
RC(1)
DC 32 MHz
1 cycle of each
Sleep/POR
Secondary Oscillator
32 kHz-20 MHz
LP, XT, HS(1)
MFINTOSC(1)
HFINTOSC(1)
2 s (approx.)
LFINTOSC(1)
31 kHz
PLL inactive
PLL active
2 ms (approx.)
Note 1:
16-32 MHz
1 cycle of each
PLL inactive.
DS40001715B-page 74
Preliminary
PIC16(L)F1704/8
6.4.2
1.
2.
3.
4.
5.
6.
7.
TWO-SPEED START-UP
SEQUENCE
6.4.3
FIGURE 6-8:
TWO-SPEED START-UP
INTOSC
TOST
OSC1
1022 1023
OSC2
Program Counter
PC - N
PC + 1
PC
System Clock
Preliminary
DS40001715B-page 75
PIC16(L)F1704/8
6.5
6.5.3
FIGURE 6-9:
External
Clock
LFINTOSC
Oscillator
64
31 kHz
(~32 s)
488 Hz
(~2 ms)
Sample Clock
6.5.1
6.5.4
Clock
Failure
Detected
FAIL-SAFE DETECTION
6.5.2
FAIL-SAFE OPERATION
DS40001715B-page 76
Preliminary
PIC16(L)F1704/8
FIGURE 6-10:
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Note:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Preliminary
DS40001715B-page 77
PIC16(L)F1704/8
6.6
REGISTER 6-1:
R/W-0/0
SPLLEN
R/W-1/1
R/W-1/1
R/W-1/1
IRCF<3:0>
U-0
R/W-0/0
R/W-0/0
SCS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-3
bit 2
Unimplemented: Read as 0
bit 1-0
Note 1:
2:
DS40001715B-page 78
Preliminary
PIC16(L)F1704/8
REGISTER 6-2:
R-1/q
R-0/q
R-q/q
R-0/q
R-0/q
R-q/q
R-0/0
R-0/q
SOSCR
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
q = Conditional
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS40001715B-page 79
PIC16(L)F1704/8
REGISTER 6-3:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TUN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
111111 =
000000 = Oscillator module is running at the factory-calibrated frequency
000001 =
011110 =
011111 = Maximum frequency
TABLE 6-2:
Name
Bit 6
Bit 5
Bit 4
OSCCON
SPLLEN
OSCSTAT
SOSCR
PLLR
OSCTUNE
PIR2
OSFIF
C2IF
C1IF
PIE2
OSFIE
C2IE
C1IE
T1CON
Legend:
CONFIG1
Legend:
Bit 2
IRCF<3:0>
TMR1CS<1:0>
OSTS
Bit 1
HFIOFR
HFIOFL
Bit 0
SCS<1:0>
MFIOFR
78
LFIOFR
HFIOFS
79
TMR6IF
TMR4IF
CCP2IF
91
BCL1IE
TMR6IE
TMR4IE
CCP2IE
88
T1OSCEN
T1SYNC
TMR1ON
261
TUN<5:0>
BCL1IF
T1CKPS<1:0>
Register
on Page
80
= unimplemented location, read as 0. Shaded cells are not used by clock sources.
TABLE 6-3:
Name
Bit 3
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
FCMEN
IESO
CLKOUTEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
FOSC<2:0>
Bit 8/0
Register
on Page
50
= unimplemented location, read as 0. Shaded cells are not used by clock sources.
DS40001715B-page 80
Preliminary
PIC16(L)F1704/8
7.0
INTERRUPTS
Operation
Interrupt Latency
Interrupts During Sleep
INT Pin
Automatic Context Saving
FIGURE 7-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
Peripheral Interrupts
(TMR1IF) PIR1<0>
(TMR1IE) PIE1<0>
Wake-up
(If in Sleep mode)
INTF
INTE
IOCIF
IOCIE
Interrupt
to CPU
PEIE
PIRn<7>
PIEn<7>
GIE
Preliminary
DS40001715B-page 81
PIC16(L)F1704/8
7.1
Operation
7.2
Interrupt Latency
The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits
will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
Current prefetched instruction is flushed
GIE bit is cleared
Current Program Counter (PC) is pushed onto the
stack
Critical registers are automatically saved to the
shadow registers (See Section 7.5 Automatic
Context Saving)
PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupts
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
DS40001715B-page 82
Preliminary
PIC16(L)F1704/8
FIGURE 7-2:
INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR
Interrupt Sampled
during Q1
Interrupt
GIE
PC
Execute
PC-1
PC
1 Cycle Instruction at PC
PC+1
0004h
0005h
NOP
NOP
Inst(0004h)
PC+1/FSR
ADDR
New PC/
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
FSR ADDR
PC+1
PC+2
0004h
0005h
INST(PC)
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
FSR ADDR
PC+1
0004h
0005h
INST(PC)
NOP
NOP
Inst(0004h)
Inst(PC)
Interrupt
GIE
PC
Execute
PC-1
PC
2 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
Preliminary
PC+2
NOP
NOP
DS40001715B-page 83
PIC16(L)F1704/8
FIGURE 7-3:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF
(5)
GIE
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
PC
Inst (PC)
Inst (PC 1)
PC + 1
Inst (PC + 1)
PC + 1
Forced NOP
Inst (PC)
0004h
Inst (0004h)
Forced NOP
0005h
Inst (0005h)
Inst (0004h)
2:
Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
4:
For minimum width of INT pulse, refer to AC specifications in Section 32.0 Electrical Specifications.
5:
DS40001715B-page 84
Preliminary
PIC16(L)F1704/8
7.3
7.4
INT Pin
7.5
W register
STATUS register (except for TO and PD)
BSR register
FSR registers
PCLATH register
Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the
value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the users
application, other registers may also need to be saved.
Preliminary
DS40001715B-page 85
PIC16(L)F1704/8
7.6
REGISTER 7-1:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
Note:
The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers
have been cleared by software.
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
DS40001715B-page 86
Preliminary
PIC16(L)F1704/8
REGISTER 7-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
Preliminary
DS40001715B-page 87
PIC16(L)F1704/8
REGISTER 7-3:
R/W-0/0
R/W-0/0
R/W-0/0
OSFIE
C2IE
C1IE
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
BCL1IE
TMR6IE
TMR4IE
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Note:
DS40001715B-page 88
Preliminary
PIC16(L)F1704/8
REGISTER 7-4:
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
COGIE
ZCDIE
CLC3IE
CLC2IE
CLC1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
Note:
Preliminary
DS40001715B-page 89
PIC16(L)F1704/8
REGISTER 7-5:
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
DS40001715B-page 90
Preliminary
PIC16(L)F1704/8
REGISTER 7-6:
R/W-0/0
R/W-0/0
R/W-0/0
OSFIF
C2IF
C1IF
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
BCL1IF
TMR6IF
TMR4IF
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Note:
Preliminary
DS40001715B-page 91
PIC16(L)F1704/8
REGISTER 7-7:
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
COGIF
ZCDIF
CLC3IF
CLC2IF
CLC1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
Note:
DS40001715B-page 92
Preliminary
PIC16(L)F1704/8
TABLE 7-1:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TMR0IF
Bit 1
Bit 0
INTF
IOCIF
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
88
OPTION_REG
PS<2:0>
86
251
PIE3
COGIE
ZCDIE
CLC3IE
CLC2IE
CLC1IE
89
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
90
PIR2
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
91
PIR3
COGIF
ZCDIF
CLC3IF
CLC2IF
CLC1IF
92
Legend:
Preliminary
DS40001715B-page 93
PIC16(L)F1704/8
NOTES:
DS40001715B-page 94
Preliminary
PIC16(L)F1704/8
8.0
8.1
1.
2.
3.
4.
5.
6.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Preliminary
DS40001715B-page 95
PIC16(L)F1704/8
8.1.1
FIGURE 8-1:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
TOST(3)
CLKOUT(2)
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
Processor in
Sleep
PC
Inst(PC) = Sleep
Inst(PC - 1)
PC + 1
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Forced NOP
0004h
0005h
Inst(0004h)
Inst(0005h)
Forced NOP
Inst(0004h)
DS40001715B-page 96
Preliminary
PIC16(L)F1704/8
8.2
8.2.2
8.2.1
The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time.
The normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
Preliminary
DS40001715B-page 97
PIC16(L)F1704/8
8.3
REGISTER 8-1:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-1/1
VREGPM
Reserved
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
2:
PIC16F1704/8 only.
See Section 32.0 Electrical Specifications.
TABLE 8-1:
Name
Bit 7
Bit 6
INTCON
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
IOCAP
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
149
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
149
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
149
IOCBP(1)
IOCBP7
IOCBP6
IOCBP5
IOCBP4
150
IOCBN(1)
IOCBN7
IOCBN6
IOCBN5
IOCBN4
150
IOCAF
(1)
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
150
IOCCP
IOCCP7(1)
IOCCP6(1)
IOCCP5
IOCCP4
IOCCP3
IOCCP2
IOCCP1
IOCCP0
151
IOCCN
IOCCN7(1)
IOCCN6(1)
IOCCN5
IOCCN4
IOCCN3
IOCCN2
IOCCN1
IOCCN0
151
IOCCF
IOCCF7(1)
IOCCF6(1)
IOCCF5
IOCCF4
IOCCF3
IOCCF2
IOCCF1
IOCCF0
151
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
88
PIE3
COGIE
ZCDIE
CLC3IE
CLC2IE
CLC1IE
89
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
90
PIR2
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
91
PIR3
COGIF
ZCDIF
CLC3IF
CLC2IF
CLC1IF
92
STATUS
TO
PD
DC
23
VREGCON(2)
VREGPM
Reserved
98
WDTCON
SWDTEN
102
Legend:
Note 1:
2:
WDTPS<4:0>
= unimplemented location, read as 0. Shaded cells are not used in Power-Down mode.
PIC16(L)F1708 only.
PIC16F1704/8 only.
DS40001715B-page 98
Preliminary
PIC16(L)F1704/8
9.0
FIGURE 9-1:
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
LFINTOSC
23-bit Programmable
Prescaler WDT
WDT Time-out
WDTE<1:0> = 10
Sleep
WDTPS<4:0>
Preliminary
DS40001715B-page 99
PIC16(L)F1704/8
9.1
9.4
9.2
9.2.1
9.2.3
TABLE 9-1:
Any Reset
CLRWDT instruction is executed
Device enters Sleep
Device wakes up from Sleep
Oscillator fail
WDT is disabled
Oscillator Start-up Timer (OST) is running
9.5
WDTE<1:0>
SWDTEN
Device
Mode
11
10
01
00
9.3
WDT IS ALWAYS ON
9.2.2
1
0
X
WDT
Mode
Active
Awake Active
Sleep
X
X
Disabled
Active
Disabled
Disabled
Time-Out Period
DS40001715B-page 100
Preliminary
PIC16(L)F1704/8
TABLE 9-2:
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Unaffected
Preliminary
DS40001715B-page 101
PIC16(L)F1704/8
9.6
REGISTER 9-1:
U-0
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
(1)
WDTPS<4:0>
R/W-0/0
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-1
bit 0
Note 1:
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
DS40001715B-page 102
Preliminary
PIC16(L)F1704/8
TABLE 9-3:
Name
Bit 6
OSCCON
SPLLEN
STATUS
WDTCON
Bit 5
Bit 4
Bit 3
IRCF<3:0>
Bit 2
TO
PD
Bit 1
Bit 0
SCS<1:0>
DC
WDTPS<4:0>
Register
on Page
78
23
SWDTEN
102
Legend: x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by
Watchdog Timer.
TABLE 9-4:
Name
CONFIG1
Bits
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
Bit 8/0
BOREN<1:0>
FOSC<2:0>
Register
on Page
50
Legend: = unimplemented location, read as 0. Shaded cells are not used by Watchdog Timer.
Preliminary
DS40001715B-page 103
PIC16(L)F1704/8
NOTES:
DS40001715B-page 104
Preliminary
PIC16(L)F1704/8
10.0
10.1.1
PMCON1
PMCON2
PMDATL
PMDATH
PMADRL
PMADRH
10.2
10.1
See Table 10-1 for Erase Row size and the number of
write latches for Flash program memory.
Preliminary
DS40001715B-page 105
PIC16(L)F1704/8
TABLE 10-1:
FLASH MEMORY
ORGANIZATION BY DEVICE
Device
PIC16(L)F1704
PIC16(L)F1708
10.2.1
Row Erase
(words)
Write
Latches
(words)
32
32
FIGURE 10-1:
Write
the
desired
address
to
the
PMADRH:PMADRL register pair.
Clear the CFGS bit of the PMCON1 register.
Then, set control bit RD of the PMCON1 register.
FLASH PROGRAM
MEMORY READ
FLOWCHART
Start
Read Operation
Select
Program or Configuration Memory
(CFGS)
Select
Word Address
(PMADRH:PMADRL)
End
Read Operation
DS40001715B-page 106
Preliminary
PIC16(L)F1704/8
FIGURE 10-2:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Flash ADDR
Flash Data
PC + 1
INSTR (PC)
INSTR(PC - 1)
executed here
PMADRH,PMADRL
INSTR (PC + 1)
BSF PMCON1,RD
executed here
PC
+3
PC+3
PMDATH,PMDATL
INSTR(PC + 1)
instruction ignored
Forced NOP
executed here
PC + 5
PC + 4
INSTR (PC + 3)
INSTR(PC + 2)
instruction ignored
Forced NOP
executed here
INSTR (PC + 4)
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 10-1:
PMADRL
PROG_ADDR_LO
PMADRL
PROG_ADDR_HI
PMADRH
BCF
BSF
NOP
NOP
PMCON1,CFGS
PMCON1,RD
;
;
;
;
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Preliminary
DS40001715B-page 107
PIC16(L)F1704/8
10.2.2
FIGURE 10-3:
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
Start
Unlock Sequence
Write 055h to
PMCON2
Write 0AAh to
PMCON2
End
Unlock Sequence
DS40001715B-page 108
Preliminary
PIC16(L)F1704/8
10.2.3
FIGURE 10-4:
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
Start
Erase Operation
Disable Interrupts
(GIE = 0)
Select
Program or Configuration Memory
(CFGS)
Unlock Sequence
Figure 10-3
(FIGURE
x-x)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
Preliminary
DS40001715B-page 109
PIC16(L)F1704/8
EXAMPLE 10-2:
Required
Sequence
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRL
ADDRL,W
PMADRL
ADDRH,W
PMADRH
PMCON1,CFGS
PMCON1,FREE
PMCON1,WREN
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
BCF
BSF
DS40001715B-page 110
PMCON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
Preliminary
PIC16(L)F1704/8
10.2.4
1.
2.
3.
Preliminary
DS40001715B-page 111
0 7
5 4
PMADRH
-
r9
r8
r7
r6
r5
PMADRL
r4
r3
r2
r1
r0
c4
c3
c2
c1
5
-
PMDATH
PMDATL
c0
Rev. 10-000004A_A0
0
8
14
Program Memory Write Latches
10
14
PMADRL<4:0>
Write Latch #0
00h
Preliminary
14
CFGS = 0
PMADRH<6:0>:
PMADRL<7:5>
Row
Address
Decode
14
14
Write Latch #1
01h
14
14
14
14
Row
Addr
Addr
Addr
Addr
000h
0000h
0001h
001Eh
001Fh
001h
0020h
0021h
003Eh
003Fh
002h
0040h
0041h
005Eh
005Fh
3FEh
7FC0h
7FC1h
7FDEh
7FDFh
3FFh
7FE0h
7FE1h
7FFEh
7FFFh
400h
CFGS = 1
8000h - 8003h
8004h 8005h
8006h
8007h 8008h
8009h - 801Fh
USER ID 0 - 3
reserved
DEVICE ID
Dev / Rev
Configuration
Words
reserved
Configuration Memory
PIC16(L)F1704/8
DS40001715B-page 112
FIGURE 10-5:
PIC16(L)F1704/8
FIGURE 10-6:
Start
Write Operation
Disable Interrupts
(GIE = 0)
Select
Program or Config. Memory
(CFGS)
Enable Write/Erase
Operation (WREN = 1)
Last word to
write ?
Yes
No
Unlock Sequence
(Figure10-3
x-x)
Figure
Increment Address
(PMADRH:PMADRL++)
Unlock Sequence
(Figure10-3
x-x)
Figure
Disable
Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Write Operation
Preliminary
DS40001715B-page 113
PIC16(L)F1704/8
EXAMPLE 10-3:
;
;
;
;
;
;
;
INTCON,GIE
PMADRH
ADDRH,W
PMADRH
ADDRL,W
PMADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR
FSR0H
PMCON1,CFGS
PMCON1,WREN
PMCON1,LWLO
;
;
;
;
;
;
;
;
;
;
;
;
;
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
PMDATL
FSR0++
PMDATH
MOVF
XORLW
ANDLW
BTFSC
GOTO
PMADRL,W
0x1F
0x1F
STATUS,Z
START_WRITE
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
PMADRL,F
LOOP
PMCON1,LWLO
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
;
;
;
;
;
Required
Sequence
LOOP
NOP
INCF
GOTO
Required
Sequence
START_WRITE
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BCF
BSF
DS40001715B-page 114
PMCON1,WREN
INTCON,GIE
Preliminary
PIC16(L)F1704/8
10.3
FIGURE 10-7:
FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
Start
Modify Operation
Read Operation
(Figure10-1
x.x)
Figure
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(Figure10-4
x.x)
Figure
Write Operation
use RAM image
(Figure10-6
x.x)
Figure
End
Modify Operation
Preliminary
DS40001715B-page 115
PIC16(L)F1704/8
10.4
TABLE 10-2:
Address
Function
Read Access
Write Access
8000h-8003h
8005h-8006h
8007h-8008h
User IDs
Device ID/Revision ID
Configuration Words 1 and 2
Yes
Yes
Yes
Yes
No
No
EXAMPLE 10-4:
* This code block will read 1 word of program memory at the memory address:
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
CLRF
PMADRL
PROG_ADDR_LO
PMADRL
PMADRH
BSF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
INTCON,GIE
;
;
;
;
;
;
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
DS40001715B-page 116
Preliminary
PIC16(L)F1704/8
10.5
Write Verify
FIGURE 10-8:
FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Start
Verify Operation
Read Operation
(Figure
x.x)
Figure
10-1
PMDAT =
RAM image
?
Yes
No
No
Fail
Verify Operation
Last
Word ?
Yes
End
Verify Operation
Preliminary
DS40001715B-page 117
PIC16(L)F1704/8
10.6
REGISTER 10-1:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 10-2:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 10-3:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
PMADR<7:0>: Specifies the Least Significant bits for program memory address
REGISTER 10-4:
U-1
R/W-0/0
(1)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<14:8>
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 1
bit 6-0
PMADR<14:8>: Specifies the Most Significant bits for program memory address
Note
1:
Unimplemented, read as 1.
DS40001715B-page 118
Preliminary
PIC16(L)F1704/8
REGISTER 10-5:
U-1
R/W-0/0
R/W-0/0
R/W/HC-0/0
R/W/HC-x/q(2)
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
(1)
CFGS
LWLO(3)
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 1
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
Preliminary
DS40001715B-page 119
PIC16(L)F1704/8
REGISTER 10-6:
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
TABLE 10-3:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
119
(1)
PMCON1
PMCON2
120
PMADRL
PMADRL<7:0>
118
(1)
PMADRH
PMADRH<6:0>
PMDATL
PMDATH
Legend:
Note 1:
CONFIG1
CONFIG2
Legend:
118
PMDATH<5:0>
118
= unimplemented location, read as 0. Shaded cells are not used by Flash program memory.
Unimplemented, read as 1.
TABLE 10-4:
Name
118
PMDATL<7:0>
Bits
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
CLKOUTEN
Bit 10/2
13:8
7:0
CP
MCLRE
PWRTE
13:8
LVP
DEBUG
LPBOR
BORV
7:0
ZCDDIS
PPS1WAY
WDTE<1:0>
Bit 9/1
Bit 8/0
BOREN<1:0>
FOSC<1:0>
STVREN
PLLEN
WRT<1:0>
Register
on Page
50
52
= unimplemented location, read as 0. Shaded cells are not used by Flash program memory.
DS40001715B-page 120
Preliminary
PIC16(L)F1704/8
11.0
I/O PORTS
FIGURE 11-1:
Read LATx
D
Write LATx
Write PORTx
CK
VDD
Data Register
Data Bus
I/O pin
Read PORTx
To digital peripherals
To analog peripherals
ANSELx
VSS
PIC16(L)F1704
PIC16(L)F1708
PORTC
Device
PORTB
TABLE 11-1:
TRISx
Preliminary
DS40001715B-page 121
PIC16(L)F1704/8
11.1
11.1.1
PORTA Registers
11.1.5
DATA REGISTER
11.1.2
11.1.6
DIRECTION CONTROL
11.1.3
11.1.4
ANALOG CONTROL
EXAMPLE 11-1:
DS40001715B-page 122
;
;
;
;
INITIALIZING PORTA
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
Preliminary
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
PIC16(L)F1704/8
11.1.7
Preliminary
DS40001715B-page 123
PIC16(L)F1704/8
11.2
REGISTER 11-1:
U-0
U-0
R/W-x/x
R/W-x/x
R-x/x
R/W-x/x
R/W-x/x
R/W-x/x
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is
return of actual I/O pin values.
REGISTER 11-2:
U-0
U-0
R/W-1/1
R/W-1/1
U-1
R/W-1/1
R/W-1/1
R/W-1/1
TRISA5
TRISA4
(1)
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 1
bit 2-0
Note 1:
Unimplemented, read as 1.
DS40001715B-page 124
Preliminary
PIC16(L)F1704/8
REGISTER 11-3:
U-0
U-0
R/W-x/u
R/W-x/u
U-0
R/W-x/u
R/W-x/u
R/W-x/u
LATA5
LATA4
LATA2
LATA1
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is
return of actual I/O pin values.
REGISTER 11-4:
U-0
U-0
U-0
R/W-1/1
U-0
R/W-1/1
R/W-1/1
R/W-1/1
ANSA4
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
Unimplemented: Read as 0
bit 2-0
ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Preliminary
DS40001715B-page 125
PIC16(L)F1704/8
REGISTER 11-5:
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
2:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is configured as an output.
REGISTER 11-6:
U-0
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
ODA5
ODA4
ODA2
ODA1
ODA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
DS40001715B-page 126
Preliminary
PIC16(L)F1704/8
REGISTER 11-7:
U-0
U-0
R/W-1/1
R/W-1/1
U-0
R/W-1/1
R/W-1/1
R/W-1/1
SLRA5
SLRA4
SLRA2
SLRA1
SLRA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
REGISTER 11-8:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Preliminary
DS40001715B-page 127
PIC16(L)F1704/8
TABLE 11-2:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
125
INLVLA
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
127
LATA
LATA5
LATA4
LATA2
LATA1
LATA0
125
ODA2
ODA1
ODA0
ODA5
ODA4
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PORTA
RA5
RA4
RA3
ODCONA
OPTION_REG
SLRCONA
SLRA5
SLRA4
TRISA
TRISA5
TRISA4
WPUA
WPUA5
WPUA4
Legend:
Note 1:
CONFIG1
Legend:
WPUA3
RA2
RA1
251
RA0
124
SLRA2
SLRA1
SLRA0
127
TRISA2
TRISA1
TRISA0
124
WPUA2
WPUA1
WPUA0
126
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTA.
Unimplemented, read as 1.
TABLE 11-3:
Name
(1)
126
PS<2:0>
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
FCMEN
IESO
CLKOUTEN
7:0
CP
MCLRE
PWRTE
Bit 10/2
WDTE<1:0>
Bit 9/1
BOREN<1:0>
FOSC<2:0>
Bit 8/0
Register
on Page
50
DS40001715B-page 128
Preliminary
PIC16(L)F1704/8
11.3
PORTB Registers
(PIC16(L)F1708 only)
11.3.4
11.3.1
DIRECTION CONTROL
11.3.2
11.3.3
11.3.5
ANALOG CONTROL
11.3.6
Preliminary
DS40001715B-page 129
PIC16(L)F1704/8
11.4
REGISTER 11-9:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
U-0
U-0
U-0
U-0
RB7
RB6
RB5
RB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note 1:
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of
actual I/O pin values.
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
TRISB7
TRISB6
TRISB5
TRISB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
R/W-x/u
R/W-x/u
R/W-x/u
U-0
U-0
U-0
U-0
LATB7
LATB6
LATB5
LATB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note 1:
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of
actual I/O pin values.
DS40001715B-page 130
Preliminary
PIC16(L)F1704/8
REGISTER 11-12: ANSELB: PORTB ANALOG SELECT REGISTER
U-0
U-0
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
ANSB5
ANSB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
ANSB<5:4>: Analog Select between Analog or Digital Function on pins RB<5:4>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 3-0
Unimplemented: Read as 0
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
WPUB7
WPUB6
WPUB5
WPUB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note 1:
2:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is configured as an output.
Preliminary
DS40001715B-page 131
PIC16(L)F1704/8
REGISTER 11-14: ODCONB: PORTB OPEN DRAIN CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
ODB7
ODB6
ODB5
ODB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
SLRB7
SLRB6
SLRB5
SLRB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
INLVLB7
INLVLB6
INLVLB5
INLVLB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
DS40001715B-page 132
Preliminary
PIC16(L)F1704/8
TABLE 11-4:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSB5
ANSB4
131
INLVLB7
INLVLB6
INLVLB5
INLVLB4
132
LATB
LATB7
LATB6
LATB5
LATB4
130
ODCONB
ODB7
ODB6
ODB5
ODB4
132
RB7
RB6
RB5
RB4
130
SLRB7
SLRB6
SLRB5
SLRB4
132
Name
ANSELB
INLVLB
PORTB
SLRCONB
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
132
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
131
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by
PORTB.
Preliminary
DS40001715B-page 133
PIC16(L)F1704/8
11.5
11.5.1
PORTC Registers
11.5.4
DATA REGISTER
11.5.2
DIRECTION CONTROL
11.5.3
DS40001715B-page 134
11.5.5
11.5.6
ANALOG CONTROL
11.5.7
Preliminary
PIC16(L)F1704/8
11.6
R/W-x/u
(2)
RC6
RC7
(2)
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
RC<7:0>: PORTC General Purpose I/O Pin bits(1, 2)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 7-0
Note 1:
2:
Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual
I/O pin values.
RC<7:6> are available on PIC16(L)F1708 only.
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
TRISC<7:0>: PORTC Tri-State Control bits(1)
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
bit 7-0
Note 1:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATC7(1)
LATC6(1)
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
Preliminary
DS40001715B-page 135
PIC16(L)F1704/8
REGISTER 11-20: ANSELC: PORTC ANALOG SELECT REGISTER
R/W-1/1
R/W-1/1
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSC7(2)
ANSC6(2)
ANSC5(3)
ANSC4(3)
ANSC3
ANSC2
ANSC1
ANSC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
ANSC<7:0>: Analog Select between Analog or Digital Function on pins RC<7:0>, respectively(1)
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 7-0
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
ANSC<7:6> are available on PIC16(L)F1708 only.
ANSC<5:4> are available on PIC16(L)F1704 only.
2:
3:
R/W-1/1
(3)
(3)
WPUC6
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
2:
3:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is configured as an output.
WPUC<7:6> are available on PIC16(L)F1708 only.
DS40001715B-page 136
Preliminary
PIC16(L)F1704/8
REGISTER 11-22: ODCONC: PORTC OPEN DRAIN CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ODC7(1)
ODC6(1)
ODC5
ODC4
ODC3
ODC2
ODC1
ODC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
ODC<7:0>: PORTC Open Drain Enable bits(1)
For RC<7:0> pins, respectively
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
bit 7-0
Note 1:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
SLRC7(1)
SLRC6(1)
SLRC5
SLRC4
SLRC3
SLRC2
SLRC1
SLRC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
SLRC<7:0>: PORTC Slew Rate Enable bits(1)
For RC<7:0> pins, respectively
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
bit 7-0
Note 1:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
INLVLC7(1)
INLVLC6(1)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
Preliminary
DS40001715B-page 137
PIC16(L)F1704/8
TABLE 11-5:
Name
ANSELC
ANSC6(1)
LATC7
(1)
SLRCONC
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSC5(2) ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
136
INLVLC1 INLVLC0
137
Bit 5
(1)
INLVLC6
Bit 4
INLVLC5
INLVLC4
INLVLC3
INLVLC2
(1)
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
(1)
LATC6
ODC5
ODC4
ODC3
ODC2
ODC1
ODC0
137
RC6(1)
RC5
RC4
RC3
RC2
RC1
RC0
135
SLRC7(1)
SLRC6(1)
SLRC5
SLRC4
SLRC3
SLRC2
SLRC1
SLRC0
137
(1)
(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
135
(1)
WPUC5
WPUC4
WPUC3
WPUC2
WPUC1
WPUC0
136
TRISC7
(1)
WPUC7
ODC6
135
RC7(1)
ODC7
PORTC
Note 1:
2:
ANSC7(1)
(1)
ODCONC
Legend:
Bit 6
INLVLC7
LATC
WPUC
Bit 7
(1)
INLVLC
TRISC
TRISC6
WPUC6
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by
PORTC.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
DS40001715B-page 138
Preliminary
PIC16(L)F1704/8
12.0
12.1
PPS Inputs
Although every peripheral has its own PPS input selection register, the selections are identical for every
peripheral
as
shown
in
Register 12-1
for
PIC16(L)F1704 devices and Register 12-2 for
PIC16(L)F1708 devices.
Note:
12.2
PPS Outputs
Each I/O pin has a PPS register with which the pin
output source is selected. With few exceptions, the port
TRIS control associated with that pin retains control
over the pin output driver. Peripherals that control the
pin output driver as part of the peripheral operation will
override the TRIS control as needed. These
peripherals include:
EUSART (synchronous operation)
MSSP (I2C)
COG (auto-shutdown)
Although every pin has its own PPS peripheral
selection register, the selections are identical for every
pin as shown in Register 12-3.
Note:
FIGURE 12-1:
PPS Inputs
abcPPS
RA0
RA0
Peripheral abc
RxyPPS
Rxy
Peripheral xyz
RC7
xyzPPS
RC7PPS
RC7
Preliminary
DS40001715B-page 139
PIC16(L)F1704/8
12.3
Bidirectional Pins
12.5
12.4
12.6
PPS Lock
EXAMPLE 12-1:
12.7
Effects of a Reset
PPS LOCK/UNLOCK
SEQUENCE
; suspend interrupts
bcf
INTCON,GIE
;
BANKSEL PPSLOCK
; set bank
; required sequence, next 5 instructions
movlw
0x55
movwf
PPSLOCK
movlw
0xAA
movwf
PPSLOCK
; Set PPSLOCKED bit to disable writes or
; Clear PPSLOCKED bit to enable writes
bsf
PPSLOCK,PPSLOCKED
; restore interrupts
bsf
INTCON,GIE
DS40001715B-page 140
Preliminary
PIC16(L)F1704/8
12.8
REGISTER 12-1:
U-0
U-0
U-0
R/W-q/u
R/W-q/u
R/W-q/u
R/W-q/u
R/W-q/u
xxxPPS<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
Preliminary
DS40001715B-page 141
PIC16(L)F1704/8
REGISTER 12-2:
U-0
U-0
U-0
R/W-q/u
R/W-q/u
R/W-q/u
R/W-q/u
R/W-q/u
xxxPPS<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
DS40001715B-page 142
Preliminary
PIC16(L)F1704/8
REGISTER 12-3:
U-0
U-0
U-0
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
RxyPPS<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
Note 1:
Preliminary
DS40001715B-page 143
PIC16(L)F1704/8
REGISTER 12-4:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
PPSLOCKED
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-1
Unimplemented: Read as 0
bit 0
DS40001715B-page 144
Preliminary
PIC16(L)F1704/8
TABLE 12-1:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
PPSLOCK
PPSLOCKED
144
INTPPS
INTPPS<4:0>
142
T0CKIPPS
T0CKIPPS<4:0>
142
T1CKIPPS
T1CKIPPS<4:0>
142
T1GPPS
T1GPPS<4:0>
142
CCP1PPS
CCP1PPS<4:0>
142
CCP2PPS
CCP2PPS<4:0>
142
COGPPS
COGPPS<4:0>
142
SSPCLKPPS
SSPCLKPPS<4:0>
142
SSPDATPPS
SSPDATPPS<4:0>
142
SSPSSPPS
SSPSSPPS<4:0>
142
RXPPS
RXPPS<4:0>
142
CKPPS
CKPPS<4:0>
142
CLCIN0PPS
CLCIN0PPS<4:0>
142
CLCIN1PPS
CLCIN1PPS<4:0>
142
CLCIN2PPS
CLCIN2PPS<4:0>
142
CLCIN3PPS
CLCIN3PPS<4:0>
142
RA0PPS
RA0PPS<4:0>
143
RA1PPS
RA1PPS<4:0>
143
RA2PPS
RA2PPS<4:0>
143
RA4PPS
RA4PPS<4:0>
143
RA5PPS
RA5PPS<4:0>
143
RB4PPS(1)
RB4PPS<4:0>
143
RB5PPS(1)
RB5PPS<4:0>
143
(1)
RB6PPS<4:0>
143
RB7PPS(1)
RB7PPS<4:0>
143
RC0PPS
RC0PPS<4:0>
143
RC1PPS
RC1PPS<4:0>
143
RC2PPS
RC2PPS<4:0>
143
RC3PPS
RC3PPS<4:0>
143
RC4PPS
RC4PPS<4:0>
143
RC5PPS
RC5PPS<4:0>
143
RC6PPS(1)
RC6PPS<4:0>
143
RC7PPS(1)
RC7PPS<4:0>
143
Name
RB6PPS
Legend: = unimplemented, read as 0. Shaded cells are unused by the DAC module.
Note 1: PIC16(L)F1708 only.
Preliminary
DS40001715B-page 145
PIC16(L)F1704/8
NOTES:
DS40001715B-page 146
Preliminary
PIC16(L)F1704/8
13.0
INTERRUPT-ON-CHANGE
13.3
13.4
13.1
Interrupt Flags
13.2
EXAMPLE 13-1:
MOVLW
XORWF
ANDWF
13.5
CLEARING INTERRUPT
FLAGS
(PORTA EXAMPLE)
0xff
IOCAF, W
IOCAF, F
Operation in Sleep
Preliminary
DS40001715B-page 147
PIC16(L)F1704/8
FIGURE 13-1:
IOCANx
Q4Q1
edge
detect
RAx
IOCAPx
data bus =
0 or 1
write IOCAFx
to data bus
IOCAFx
IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors
FOSC
Q1
Q1
Q2
Q2
Q2
Q3
Q3
Q4
Q4Q1
Q1
Q3
Q4
Q4Q1
DS40001715B-page 148
Q4
Q4Q1
Preliminary
Q4Q1
PIC16(L)F1704/8
13.6
REGISTER 13-1:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 13-2:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 13-3:
U-0
U-0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Preliminary
DS40001715B-page 149
PIC16(L)F1704/8
IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER(1)
REGISTER 13-4:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
IOCBP7
IOCBP6
IOCBP5
IOCBP4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note
1:
PIC16(L)F1708 only.
REGISTER 13-5:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
IOCBN7
IOCBN6
IOCBN5
IOCBN4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Note
Unimplemented: Read as 0
1:
PIC16(L)F1708 only.
REGISTER 13-6:
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
U-0
U-0
U-0
U-0
IOCBF7
IOCBF6
IOCBF5
IOCBF4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note
1:
PIC16(L)F1708 only.
DS40001715B-page 150
Preliminary
PIC16(L)F1704/8
REGISTER 13-7:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCCP7(1)
IOCCP6(1)
IOCCP5
IOCCP4
IOCCP3
IOCCP2
IOCCP1
IOCCP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
PIC16(L)F1708 only.
REGISTER 13-8:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCCN7(1)
IOCCN6(1)
IOCCN5
IOCCN4
IOCCN3
IOCCN2
IOCCN1
IOCCN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
IOCCN<7:0>: Interrupt-on-Change PORTC Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCCFx bit and IOCIF flag will be set upon
detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
bit 7-0
PIC16(L)F1708 only.
Note 1:
REGISTER 13-9:
R/W/HS-0/0
(1)
IOCCF7
R/W/HS-0/0
(1)
IOCCF6
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCCF5
IOCCF4
IOCCF3
IOCCF2
IOCCF1
IOCCF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
PIC16(L)F1708 only.
Preliminary
DS40001715B-page 151
PIC16(L)F1704/8
TABLE 13-1:
Name
ANSELA
(1)
ANSELB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
125
ANSB4
131
136
(1)
ANSB5
(1)
ANSC3
ANSC2
ANSC1
ANSC0
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
149
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
149
ANSC7
ANSC5
(2)
GIE
ANSELC
INTCON
ANSC6
(2)
ANSC4
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
149
IOCBF(1)
IOCBF7
IOCBF6
IOCBF5
IOCBF4
150
IOCBN(1)
IOCBN7
IOCBN6
IOCBN5
IOCBN4
150
(1)
IOCBP7
IOCBP6
IOCBP5
IOCBP4
150
IOCAP
IOCBP
IOCCF
IOCCF7
IOCCF6(1)
IOCCF5
IOCCF4
IOCCF3
IOCCF2
IOCCF1
IOCCF0
151
IOCCN
IOCCN7(1) IOCCN6(1)
IOCCN5
IOCCN4
IOCCN3
IOCCN2
IOCCN1
IOCCN0
151
IOCCP
IOCCP7(1) IOCCP6(1)
IOCCP5
IOCCP4
IOCCP3
IOCCP2
IOCCP1
IOCCP0
151
TRISA2
TRISA1
TRISA0
124
TRISA
(1)
TRISB
TRISC
Legend:
Note 1:
2:
3:
(1)
TRISB7
TRISC7
(1)
TRISA5
TRISA4
(3)
TRISB6
TRISB5
TRISB4
130
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
135
DS40001715B-page 152
Preliminary
PIC16(L)F1704/8
14.0
14.1
14.2
Preliminary
D40001715B-page 153
PIC16(L)F1704/8
FIGURE 14-1:
CDAFVR<1:0>
2
X1
X2
X4
FVR BUFFER1
(To ADC Module)
X1
X2
X4
FVR BUFFER2
(To Comparators, DAC)
HFINTOSC Enable
HFINTOSC
To BOR, LDO
FVREN
+
FVRRDY
TABLE 14-1:
Peripheral
HFINTOSC
Conditions
Description
BOREN<1:0> = 11
BOR
LDO
The device runs off of the ULP regulator when in Sleep mode
D40001715B-page 154
Preliminary
PIC16(L)F1704/8
14.3
REGISTER 14-1:
R/W-0/0
R-q/q
FVREN
FVRRDY(1)
R/W-0/0
TSEN
(3)
R/W-0/0
TSRNG
R/W-0/0
(3)
R/W-0/0
R/W-0/0
CDAFVR<1:0>
R/W-0/0
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
Note 1:
2:
3:
TABLE 14-2:
Name
FVRCON
Legend:
Bit 6
Bit 5
Bit 4
FVREN
FVRRDY
TSEN
TSRNG
Bit 3
Bit 2
CDAFVR<1:0>
Bit 1
Bit 0
ADFVR<1:0>
Register
on page
155
Shaded cells are not used with the Fixed Voltage Reference.
Preliminary
D40001715B-page 155
PIC16(L)F1704/8
NOTES:
D40001715B-page 156
Preliminary
PIC16(L)F1704/8
15.0
TEMPERATURE INDICATOR
MODULE
FIGURE 15-1:
VDD
TSEN
TSRNG
15.1
Circuit Operation
EQUATION 15-1:
VOUT
Temp. Indicator
15.2
VOUT RANGES
TEMPERATURE CIRCUIT
DIAGRAM
To ADC
TABLE 15-1:
Low Range: VOUT = VDD - 2VT
3.6V
1.8V
15.3
Temperature Output
Preliminary
DS40001715B-page 157
PIC16(L)F1704/8
15.4
TABLE 15-2:
Name
FVRCON
Legend:
Bit 6
Bit 5
Bit 4
FVREN
FVRRDY
TSEN
TSRNG
Bit 3
Bit 2
CDFVR<1:0>
Bit 1
Bit 0
ADFVR<1:0>
Register
on page
155
DS40001715B-page 158
Preliminary
PIC16(L)F1704/8
16.0
COMPARATOR MODULE
FIGURE 16-1:
16.1
SINGLE COMPARATOR
VIN+
VIN-
Output
VINVIN+
Output
Note:
Comparator Overview
TABLE 16-1:
AVAILABLE COMPARATORS
Device
PIC16(L)F1704/8
C1
C2
Preliminary
DS40001715B-page 159
PIC16(L)F1704/8
FIGURE 16-2:
CxNCH<2:0>
CxON(1)
CxINTP
Interrupt
det
CXIN0-
CXIN1-
CXIN2-
2 MUX
Set CxIF
CXIN3-
det
Reserved
Reserved
FVR Buffer2
CxINTN
Interrupt
(2)
CXPOL
CxVN
Cx
CxVP
ZLF
EN
Q1
7
CxHYS
AGND
CxSP
to CMXCON0 (CXOUT)
and CM2CON1 (MCXOUT)
CxZLF
async_CxOUT
CXSYNC
TRIS bit
CXOUT
CXIN+
Reserved
Reserved
Reserved
Reserved
DAC_Output
FVR Buffer2
D
From Timer1
tmr1_clk
sync_CxOUT
To Timer1
and PSMC Logic
MUX
(2)
7
AGND
CxON
CXPCH<2:0>
3
Note 1:
2:
DS40001715B-page 160
Preliminary
PIC16(L)F1704/8
16.2
Comparator Control
16.2.3
Enable
Output
Output polarity
Zero latency filter
Speed/Power selection
Hysteresis enable
Output synchronization
TABLE 16-2:
Interrupt enable
Interrupt edge polarity
Positive input channel selection
Negative input channel selection
16.2.1
CxPOL
CxOUT
16.2.4
COMPARATOR ENABLE
16.2.2
COMPARATOR OUTPUT
SELECTION
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition
COMPARATOR SPEED/POWER
SELECTION
Preliminary
DS40001715B-page 161
PIC16(L)F1704/8
16.3
Comparator Hysteresis
16.4
16.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
16.5
Comparator Interrupt
16.6
16.7
DS40001715B-page 162
Preliminary
PIC16(L)F1704/8
16.8
16.9
FIGURE 16-3:
TZLF
Preliminary
DS40001715B-page 163
PIC16(L)F1704/8
16.10 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 16-4. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
0. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
FIGURE 16-4:
Rs < 10K
Analog
Input
pin
VT 0.6V
RIC
To Comparator
VA
CPIN
5 pF
VT 0.6V
ILEAKAGE(1)
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
= Interconnect Resistance
= Source Impedance
RS
= Analog Voltage
VA
VT
= Threshold Voltage
Note 1: See I/O Ports in Table 32-4: I/O Ports.
DS40001715B-page 164
Preliminary
PIC16(L)F1704/8
16.11 Register Definitions: Comparator Control
REGISTER 16-1:
R/W-0/0
R-0/0
U-0
R/W-0/0
R/W-0/0
R/W-1/1
R/W-0/0
R/W-0/0
CxON
CxOUT
CxPOL
CxZLF
CxSP
CxHYS
CxSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS40001715B-page 165
PIC16(L)F1704/8
REGISTER 16-2:
R/W-0/0
R/W-0/0
CxINTP
CxINTN
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CxPCH<2:0>
R/W-0/0
R/W-0/0
CxNCH<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-3
bit 2-0
DS40001715B-page 166
Preliminary
PIC16(L)F1704/8
REGISTER 16-3:
U-0
U-0
U-0
U-0
U-0
U-0
R-0/0
R-0/0
MC2OUT
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
Unimplemented: Read as 0
bit 1
bit 0
TABLE 16-3:
Name
ANSELA
ANSELB(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
125
131
ANSB5
ANSB4
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
136
CM1CON0
C1ON
C1OUT
C1POL
C1ZLF
C1SP
C1HYS
C1SYNC
165
CM2CON0
C2ON
C2OUT
C2POL
C2ZLF
C2SP
C2HYS
C2SYNC
165
CM1CON1
C1NTP
C1INTN
C1PCH<2:0>
C1NCH<2:0>
CM2CON1
C2NTP
C2INTN
C2PCH<2:0>
C2NCH<2:0>
CMOUT
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
DAC1EN
DAC1OE1
DAC1OE2
DAC1PSS<1:0>
ANSELC
DAC1CON0
DAC1CON1
MC2OUT
166
166
MC1OUT
ADFVR<1:0>
DAC1NSS
DAC1R<7:0>
167
155
244
244
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
88
PIR2
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
91
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
124
INTCON
TRISA
TRISB(1)
TRISC
Legend:
Note 1:
2:
3:
TRISB7
TRISB6
TRISB5
TRISB4
130
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
135
= unimplemented location, read as 0. Shaded cells are unused by the comparator module.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
Unimplemented, read as 1.
Preliminary
DS40001715B-page 167
PIC16(L)F1704/8
NOTES:
DS40001715B-page 168
Preliminary
PIC16(L)F1704/8
17.0
PR2
T2CON
PWMxDCH
PWMxDCL
PWMxCON
FIGURE 17-1:
Latched
(Not visible to user)
PWMxOUT
to other peripherals: CLC and CWG
Comparator
PWMx
TMR2 Module
TMR2
(1)
Comparator
PR2
Note
1:
Clear Timer,
PWMx pin and
latch Duty Cycle
8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to
create a 10-bit time base.
FIGURE 17-2:
PWM OUTPUT
Period
Pulse Width
TMR2 = 0
TMR2 = PR2
TMR2 =
PWMxDCH<7:0>:PWMxDCL<7:6>
Preliminary
DS40001715B-page 169
PIC16(L)F1704/8
17.1
FUNDAMENTAL OPERATION
17.1.4
EQUATION 17-2:
EQUATION 17-3:
PWM PERIOD
PWM PERIOD
PULSE WIDTH
EQUATION 17-1:
17.1.3
PWMxDCH:PWMxDCL<7:6>
Duty Cycle Ratio = ----------------------------------------------------------------------------------4 PR2 + 1
TOSC = 1/FOSC
DS40001715B-page 170
Preliminary
PIC16(L)F1704/8
17.1.5
PWM RESOLUTION
EQUATION 17-4:
PWM RESOLUTION
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
Note:
TABLE 17-1:
PWM Frequency
0.31 kHz
Timer Prescale
PR2 Value
78.12 kHz
156.3 kHz
208.3 kHz
64
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
PWM Frequency
0.31 kHz
Timer Prescale
PR2 Value
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
64
0x65
0x65
0x65
0x19
0x0C
0x09
17.1.6
19.53 kHz
0xFF
TABLE 17-2:
4.88 kHz
17.1.7
17.1.8
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
PWM registers to their Reset states.
Preliminary
DS40001715B-page 171
PIC16(L)F1704/8
17.1.9
17.1.10
5.
6.
7.
Note:
DS40001715B-page 172
Preliminary
PIC16(L)F1704/8
17.2
REGISTER 17-1:
R/W-0/0
U-0
R-0/0
R/W-0/0
U-0
U-0
U-0
U-0
PWMxEN
PWMxOUT
PWMxPOL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
bit 3-0
Unimplemented: Read as 0
Preliminary
DS40001715B-page 173
PIC16(L)F1704/8
REGISTER 17-2:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PWMxDCH<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits
These bits are the MSbs of the PWM duty cycle. The two LSbs are found in PWMxDCL Register.
bit 7-0
REGISTER 17-3:
R/W-x/u
R/W-x/u
PWMxDCL<7:6>
U-0
U-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as 0
TABLE 17-3:
Name
CCPTMRS
Bit 6
P4TSEL<1:0>
Bit 5
Bit 3
P3TSEL<1:0>
PR2
Bit 2
C2TSEL<1:0>
Bit 1
Bit 0
C1TSEL<1:0>
PWM3CON
PWM3EN
PWM3OE
PWM3OUT
PWM3DCH
PWM3POL
PWM3DCL<7:6>
PWM4CON
PWM4EN
PWM4OE
269
173
174
174
PWM4OUT
PWM4POL
173
PWM4DCH
PWM4DCH<7:0>
PWM4DCL
PWM4DCL<7:6>
RxyPPS
T2CON
TOUTPS3
TOUTPS2
TMR2
Register
on Page
265
PWM3DCH<7:0>
PWM3DCL
Legend:
Bit 4
174
174
T2CKPS1
T2CKPS0
267
RxyPPS<4:0>
TOUTPS1
TOUTPS0
TMR2ON
143
265
- = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
DS40001715B-page 174
Preliminary
PIC16(L)F1704/8
18.0
18.1
COMPLEMENTARY OUTPUT
GENERATOR (COG) MODULE
18.1.1
Fundamental Operation
STEERING (ALL MODES)
18.1.2
18.1.3
FULL-BRIDGE MODES
Preliminary
DS40001715B-page 175
V+
FET
Driver
QC
QA
FET
Driver
COGxA
Load
Preliminary
COGxB
FET
Driver
COGxC
FET
Driver
QD
QB
VCOGxD
PIC16(L)F1704/8
DS40001715B-page 176
FIGURE 18-1:
PIC16(L)F1704/8
18.1.4
HALF-BRIDGE MODE
18.1.5
PUSH-PULL MODE
18.1.6
Preliminary
DS40001715B-page 177
reserved
HFINTOSC
11
10
Fosc/4
Fosc
01
00
GxCS<1:0>
unimplemented
PWM3OUT
CCP2
CCP1
CLC1OUT
C2OUT
C1OUT
COGINPPS
1
0
High-Z
COG_clock
GxPOLA
src7
src6
src5
src4
src3
src2
src1
src0
Preliminary
src7
src6
src5
src4
src3
src2
src1
src0
GxSDATA
GxASDBD<1:0>
clock
1
0
High-Z
Reset Dominates
rising_event
S Q
count_en
GxPOLB
GxSDATB
1
0
High-Z
11
10
01
00
1
count_en
GxPOLC
GxSDATC
GxASDBD<1:0>
1
0
High-Z
GxPOLD
GxSDATD
11
10
01
00
COGxD
GxSTRD
GxASE
S Q
GxARSEN
Write GxASE Low
COGxC
GxEN
Auto-shutdown source
COGxB
GxASDAC<1:0>
clock
falling_event
1
0
GxSTRB
GxSTRC
11
10
01
00
R Q
COGxA
GxSTRA
COGINPPS
GxAS0E
C1OUT
GxAS1E
C2OUT
GxAS2E
CLC2OUT
GxAS3E
11
10
01
00
R
Set Dominates
S
D Q
PIC16(L)F1704/8
DS40001715B-page 178
FIGURE 18-2:
FIGURE 18-3:
reserved
HFINTOSC
11
10
Fosc/4
Fosc
01
00
GxCS<1:0>
unimplemented
PWM3OUT
CCP2
CCP1
CLC1OUT
C2OUT
C1OUT
COGINPPS
1
0
High-Z
COG_clock
GxPOLA
GxSTRA
Preliminary
src7
src6
src5
src4
src3
src2
src1
src0
GxSDATA
GxASDBD<1:0>
1
0
High-Z
Reset Dominates
rising_event
S Q
count_en
GxPOLB
GxSTRB
GxSDATB
D Q
1
0
High-Z
11
10
01
00
1
count_en
GxPOLC
GxSDATC
D Q
GxASDBD<1:0>
GxSDATD
DS40001715B-page 179
R
Set Dominates
COGxD
D Q
GxASE
S Q
GxARSEN
Write GxASE Low
11
10
01
00
S
D Q
PIC16(L)F1704/8
1
GxPOLD
GxSTRD
COGxC
1
0
High-Z
Auto-shutdown source
COGxB
GxASDAC<1:0>
clock
falling_event
1
0
GxEN
11
10
01
00
R Q
COGxA
D Q
clock
GxSTRC
COGINPPS
GxAS0E
C1OUT
GxAS1E
C2OUT
GxAS2E
CLC2OUT
GxAS3E
11
10
01
00
SIMPLIFIED COG BLOCK DIAGRAM (FULL-BRIDGE MODES, FORWARD: GXMD = 2, REVERSE: GXMD = 3)
GxASDAC<1:0>
reserved
HFINTOSC
11
10
Fosc/4
Fosc
01
00
Rising Input Block
src7
src6
src5
src4
src3
src2
src1
src0
GxSDATA
GxPOLA
clock
clock
Reset Dominates
rising_event
Preliminary
src7
src6
src5
src4
src3
src2
src1
src0
1
0
High-Z
count_en
GxSDATB
Falling Dead-Band Block
11
10
01
00
signal_out
signal_in
falling_event
11
10
01
00
1
count_en
GxMD0
GxEN
1
0
High-Z
GxSDATD
Auto-shutdown source
GxPOLD
R
Set Dominates
GxASDBD<1:0>
11
10
01
00
COGxD
GxSTRD
GxASE
S Q
GxARSEN
Write GxASE Low
COGxC
GxSDATC 0
GxPOLC
GxSTRC
D Q
COGxB
GxASDAC<1:0>
GxSTRB
1
0
High-Z
1
0
clock
clock
GxASDBD<1:0>
R Q
Forward/Reverse
GxSTRA
signal_out
signal_in
COGxA
S Q
COGINPPS
GxAS0E
C1OUT
GxAS1E
C2OUT
GxAS2E
CLC2OUT
GxAS3E
GxPOLB
unimplemented
PWM3OUT
CCP2
CCP1
CLC1OUT
C2OUT
C1OUT
COGINPPS
11
10
01
00
COG_clock
GxCS<1:0>
unimplemented
PWM3OUT
CCP2
CCP1
CLC1OUT
C2OUT
C1OUT
COGINPPS
1
0
High-Z
S
D Q
PIC16(L)F1704/8
DS40001715B-page 180
FIGURE 18-4:
FIGURE 18-5:
reserved
HFINTOSC
11
10
Fosc/4
Fosc
01
00
GxCS<1:0>
unimplemented
PWM3OUT
CCP2
CCP1
CLC1OUT
C2OUT
C1OUT
COGINPPS
1
0
High-Z
COG_clock
GxSDATA
GxPOLA
clock
Reset Dominates
rising_event
S Q
Preliminary
src7
src6
src5
src4
src3
src2
src1
src0
GxSTRA
1
0
High-Z
signal_out
signal_in
count_en
GxSDATB
Falling Dead-Band Block
1
0
High-Z
signal_out
signal_in
falling_event
11
10
01
00
1
GxSDATD
Auto-shutdown source
GxPOLD
DS40001715B-page 181
R
Set Dominates
11
10
01
00
COGxD
GxSTRD
GxASE
S Q
GxARSEN
Write GxASE Low
GxASDBD<1:0>
S
D Q
PIC16(L)F1704/8
COGxC
GxSDATC 0
GxPOLC
GxSTRC
1
0
High-Z
COGxB
GxASDAC<1:0>
count_en
1
0
GxSTRB
GxEN
11
10
01
00
clock
clock
GxASDBD<1:0>
R Q
COGxA
clock
GxPOLB
COGINPPS
GxAS0E
C1OUT
GxAS1E
C2OUT
GxAS2E
CLC2OUT
GxAS3E
11
10
01
00
reserved
HFINTOSC
11
10
Fosc/4
Fosc
01
00
GxCS<1:0>
unimplemented
PWM3OUT
CCP2
CCP1
CLC1OUT
C2OUT
C1OUT
COGINPPS
1
0
High-Z
COG_clock
GxSDATA
GxPOLA
Reset Dominates
Preliminary
src7
src6
src5
src4
src3
src2
src1
src0
rising_event
S Q
1
0
High-Z
D Q
R
count_en
GxSDATB
1
0
High-Z
falling_event
11
10
01
00
1
1
0
High-Z
GxSDATD
Auto-shutdown source
GxPOLD
R
Set Dominates
GxASDBD<1:0>
11
10
01
00
COGxD
GxSTRD
GxASE
S Q
GxARSEN
Write GxASE Low
COGxC
GxSDATC 0
GxPOLC
GxSTRC
count_en
COGxB
GxASDAC<1:0>
GxSTRB
clock
1
0
GxEN
GxASDBD<1:0>
11
10
01
00
R Q
COGxA
GxSTRA
Push-Pull
clock
COGINPPS
GxAS0E
C1OUT
GxAS1E
C2OUT
GxAS2E
CLC2OUT
GxAS3E
GxPOLB
unimplemented
PWM3OUT
CCP2
CCP1
CLC1OUT
C2OUT
C1OUT
COGINPPS
11
10
01
00
S
D Q
PIC16(L)F1704/8
DS40001715B-page 182
FIGURE 18-6:
FIGURE 18-7:
GxPH(R/F)<3:0>
Blanking
=
Cnt/Clr
count_en
Phase
Delay
GxBLK(F/R)<3:0>
src7
Gx(R/F)IS7
src6
Gx(R/F)SIM7
Gx(R/F)IS6
src5
Gx(R/F)SIM6
Preliminary
Gx(R/F)IS5
src4
Gx(R/F)SIM5
Gx(R/F)IS4
src3
Gx(R/F)SIM4
Gx(R/F)IS3
Gx(R/F)IS2
src1
Gx(R/F)SIM2
Gx(R/F)IS1
DS40001715B-page 183
src0
Gx(R/F)SIM1
Gx(R/F)IS0
Gx(R/F)SIM0
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
D Q
LE
(rising/falling)_event
PIC16(L)F1704/8
src2
Gx(R/F)SIM3
D Q
PIC16(L)F1704/8
FIGURE 18-8:
Gx(R/F)DBTS
Synchronous
Delay
=
Cnt/Clr
clock
0
1
GxDBR<3:0>
Asynchronous
Delay Chain
signal_out
signal_in
DS40001715B-page 184
Preliminary
PIC16(L)F1704/8
FIGURE 18-9:
COG_clock
Source
CCP1
COGxA
Rising_event Dead-band
Falling_event Dead-band
Falling_event Dead-band
COGxB
FIGURE 18-10:
COG_clock
Source
CCP1
COGxA
Falling_event Dead-Band
Phase Delay
Rising_event
Dead-Band
COGxB
FIGURE 18-11:
Falling_event
Dead-Band
CCP1
COGxA
COGxB
Preliminary
DS40001715B-page 185
PIC16(L)F1704/8
FIGURE 18-12:
CCP1
COGxA
COGxB
COGxC
COGxD
FIGURE 18-13:
CCP1
COGxA
Falling_event Dead-Band
COGxB
COGxC
COGxD
CxMD0
DS40001715B-page 186
Preliminary
PIC16(L)F1704/8
18.2
Clock Sources
FIGURE 18-14:
Rising (CCP1)
Falling (C1OUT)
COGOUT
Edge Sensitive
Falling (C1OUT)
C1IN-
COGOUT
18.3.1
hyst
C1IN-
18.3
hyst
Level Sensitive
18.3.2
RISING EVENT
18.3.3
FALLING EVENT
Preliminary
DS40001715B-page 187
PIC16(L)F1704/8
18.4
Output Control
18.4.1
OUTPUT ENABLES
There are no output enable controls in the COG module. Instead, each device pin has an individual output
selection control called the PPS register. All four COG
outputs are available for selection in the PPS register
of every pin.
When a COG output is enabled by PPS selection, the
output on the pin has several possibilities, which
depend on the steering control, GxEN bit, and shutdown state as shown in Table 18-1
.
TABLE 18-1:
GxEN
Active
Shutdown override
Inactive
Inactive state
Inactive
x
0
1
18.4.2
Output
Inactive
POLARITY CONTROL
18.5
Dead-Band Control
DS40001715B-page 188
18.5.1
GxSTR
Shutdown
bit
18.5.2
SYNCHRONOUS COUNTER
DEAD-BAND DELAY
18.5.3
SYNCHRONOUS COUNTER
DEAD-BAND TIME UNCERTAINTY
Preliminary
PIC16(L)F1704/8
18.5.4
Rising event dead band delays the turn-on of the primary outputs from when complementary outputs are
turned off. The rising event dead-band time starts
when the rising_ event output goes true.
See Section 18.5.1, Asynchronous delay chain
dead-band delay and Section 18.5.2, Synchronous
counter dead-band delay for more information on setting the rising edge dead-band time.
18.5.5
Falling event dead band delays the turn-on of complementary outputs from when the primary outputs are
turned off. The falling event dead-band time starts
when the falling_ event output goes true.
See Section 18.5.1, Asynchronous delay chain
dead-band delay and Section 18.5.2, Synchronous
counter dead-band delay for more information on setting the rising edge dead-band time.
18.5.6
Rising-to-Falling Overlap
Falling-to-Rising Overlap
18.6
Blanking Control
18.6.2
Rising-to-falling
Falling-to-rising
18.5.6.2
18.6.1
DEAD-BAND OVERLAP
18.5.6.1
18.6.3
18.7
Phase Delay
Preliminary
DS40001715B-page 189
PIC16(L)F1704/8
18.7.1
CUMULATIVE UNCERTAINTY
EXAMPLE 18-1:
EQUATION 18-1:
PHASE, DEAD-BAND,
AND BLANKING TIME
CALCULATION
Given:
Count = Ah = 10d
F COG_Clock = 8MHz
Therefore:
1
T uncertainty = -------------------------F COG_clock
1
= --------------- = 125ns
8MHz
Proof:
T min = Count
Count
T min = -------------------------F COG_clock
= 125ns 10d = 1.25s
F COG_clock
T max
Count + 1
= -------------------------F COG_clock
Count + 1
T max = -------------------------F COG_clock
= 125ns 10d + 1
Also:
1
T uncertainty = -------------------------F COG_clock
Where:
TIMER UNCERTAINTY
= 1.375s
Therefore:
COGxPHR
COGxPHF
COGxDBR
COGxDBF
COGxBLKR
COGxBLKF
DS40001715B-page 190
= 1.375s 1.25s
Count
= 125ns
Preliminary
PIC16(L)F1704/8
18.8
Auto-shutdown Control
18.8.2
18.8.1
SHUTDOWN
18.8.1.1
Forced low
Forced high
Tri-state
PWM inactive state (same state as that caused by
a falling event)
18.8.3
AUTO-SHUTDOWN RESTART
18.8.3.1
18.8.1.2
The levels driven to the output pins, while the shutdown is active, are controlled by the GxASDAC<1:0>
and GxASDBC<1:0> bits of the COGxASD0 register
(Register 18-7). GxASDAC<1:0> controls the COGxA
and COGxC override levels and GxASDBC<1:0> controls the COGxB and COGxD override levels. There
are four override options for each output pair:
Note:
18.8.3.2
Auto-Restart
Preliminary
DS40001715B-page 191
CCP1
GxARSEN
Next rising event
Shutdown input
Next rising event
GxASE
Cleared in hardware
Preliminary
Cleared in software
GxASDAC
2b00
2b00
2b00
GxASDBD
COGxA
COGxB
Operating State
NORMAL OUTPUT
SHUTDOWN
NORMAL OUTPUT
SHUTDOWN
NORMAL OUTPUT
AUTO-RESTART
PIC16(L)F1704/8
DS40001715B-page 192
FIGURE 18-15: AUTO-SHUTDOWN WAVEFORM CCP1 AS RISING AND FALLING EVENT INPUT SOURCE
PIC16(L)F1704/8
18.9
Buffer Updates
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
Preliminary
DS40001715B-page 193
PIC16(L)F1704/8
18.13 Register Definitions: COG Control
REGISTER 18-1:
R/W-0/0
R/W-0/0
U-0
GxEN
GxLD
R/W-0/0
R/W-0/0
R/W-0/0
GxCS<1:0>
R/W-0/0
R/W-0/0
GxMD<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4-3
bit 2-0
DS40001715B-page 194
Preliminary
PIC16(L)F1704/8
REGISTER 18-2:
R/W-0/0
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxRDBS
GxFDBS
GxPOLD
GxPOLC
GxPOLB
GxPOLA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0.
bit 3
bit 2
bit 1
bit 0
Preliminary
DS40001715B-page 195
PIC16(L)F1704/8
REGISTER 18-3:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxRIS6
GxRIS5
GxRIS4
GxRIS3
GxRIS2
GxRIS1
GxRIS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001715B-page 196
Preliminary
PIC16(L)F1704/8
REGISTER 18-4:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxRSIM6
GxRSIM5
GxRSIM4
GxRSIM3
GxRSIM2
GxRSIM1
GxRSIM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS40001715B-page 197
PIC16(L)F1704/8
REGISTER 18-5:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxFIS6
GxFIS5
GxFIS4
GxFIS3
GxFIS2
GxFIS1
GxFIS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001715B-page 198
Preliminary
PIC16(L)F1704/8
REGISTER 18-6:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxFSIM6
GxFSIM5
GxFSIM4
GxFSIM3
GxFSIM2
GxFSIM1
GxFSIM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS40001715B-page 199
PIC16(L)F1704/8
REGISTER 18-7:
R/W-0/0
R/W-0/0
GxASE
GxARSEN
R/W-0/0
R/W-0/0
GxASDBD<1:0>
R/W-0/0
R/W-0/0
GxASDAC<1:0>
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
bit 3-2
bit 1-0
Unimplemented: Read as 0
DS40001715B-page 200
Preliminary
PIC16(L)F1704/8
REGISTER 18-8:
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxAS3E
GxAS2E
GxAS1E
GxAS0E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Preliminary
DS40001715B-page 201
PIC16(L)F1704/8
REGISTER 18-9:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxDATD
GxDATC
GxDATB
GxDATA
GxSTRD
GxSTRC
GxSTRB
GxSTRA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001715B-page 202
Preliminary
PIC16(L)F1704/8
REGISTER 18-10: COGxDBR: COG RISING EVENT DEAD-BAND COUNT REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxDBR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxDBF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Preliminary
DS40001715B-page 203
PIC16(L)F1704/8
REGISTER 18-12: COGxBLKR: COG RISING EVENT BLANKING COUNT REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxBLKR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxBLKF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS40001715B-page 204
Preliminary
PIC16(L)F1704/8
REGISTER 18-14: COGxPHR: COG RISING EDGE PHASE DELAY COUNT REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxPHR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 18-15: COGxPHF: COG FALLING EDGE PHASE DELAY COUNT REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxPHF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Preliminary
DS40001715B-page 205
PIC16(L)F1704/8
TABLE 18-2:
Name
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
125
ANSB5
ANSB4
131
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
136
Bit 7
Bit 6
ANSELA
ANSELB(1)
ANSELC
COG1PHR
G1PHR<5:0>
205
COG1PHF
G1PHF<5:0>
205
COG1BLKR
G1BLKR<5:0>
204
COG1BLKF
G1BLKF<5:0>
204
COG1DBR
G1DBR<5:0>
203
COG1DBF
G1DBF<5:0>
COG1RIS
G1RIS6
G1RIS5
G1RIS4
G1RIS3
G1RIS2
G1RIS1
G1RIS0
196
COG1RSIM
G1RSIM6
G1RSIM5
G1RSIM4
G1RSIM3
G1RSIM2
G1RSIM1
G1RSIM0
197
COG1FIS
G1FIS6
G1FIS5
G1FIS4
G1FIS3
G1FIS2
G1FIS1
G1FIS0
198
COG1FSIM
G1FSIM6
G1FSIM5
G1FSIM4
G1FSIM3
G1FSIM2
G1FSIM1
G1FSIM0
199
COG1CON0
G1EN
G1LD
COG1CON1
G1RDBS
G1FDBS
COG1ASD0
G1ASE
G1ARSEN
COG1ASD1
G1AS3E
COG1STR
G1SDATD
G1SDATC
G1SDATB
G1SDATA
GIE
PEIE
T0IE
INTE
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
PIR2
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
INTCON
COG1PPS
RxyPPS
Legend:
Note 1:
2:
G1CS<1:0>
G1ASDBD<1:0>
203
G1MD<2:0>
G1POLD
G1POLC
194
G1POLB
G1POLA
200
G1AS2E
G1AS1E
G1AS0E
201
G1STRD
G1STRC
G1STRB
G1STRA
202
IOCIE
T0IF
INTF
IOCIF
G1ASDAC<1:0>
COG1PPS<4:0>
195
86
142
RxyPPS<4:0>
88
91
143
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by COG.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
DS40001715B-page 206
Preliminary
PIC16(L)F1704/8
19.0
The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations
of software execution. The logic cell takes up to 32
input signals and, through the use of configurable
gates, reduces the 32 inputs to four logic lines that drive
one of eight selectable single-output logic functions.
Input sources are a combination of the following:
I/O pins
Internal clocks
Peripherals
Register bits
FIGURE 19-1:
LCxOUT
MLCxOUT
Q1
.
.
.
LCx_in[29]
LCx_in[30]
LCx_in[31]
to Peripherals
Input Data Selection Gates(1)
LCx_in[0]
LCx_in[1]
LCx_in[2]
LCxEN
lcxg1
lcxg2
lcxg3
Logic
Function
LCx_out
lcxq
(2)
PPS
Module
CLCx
lcxg4
LCxPOL
LCxMODE<2:0>
Interrupt
det
LCXINTP
LCXINTN
set bit
CLCxIF
Interrupt
det
Note 1:
2:
Preliminary
DS40001715B-page 207
PIC16(L)F1704/8
19.1
CLCx Setup
TABLE 19-1:
Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four
stages are:
Data selection
Data gating
Logic function selection
Output polarity
lcxdy
DxS
CLCx
Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
19.1.1
Data Input
DATA SELECTION
There are 32 signals available as inputs to the configurable logic. Four 32-input multiplexers are used to
select the inputs to pass on to the next stage.
Note:
DS40001715B-page 208
01001 C2OUT
LCx_in[8]
01000 C1OUT
LCx_in[7]
00111 Reserved
LCx_in[6]
LCx_in[5]
LCx_in[4]
LCx_in[3]
LCx_in[2]
LCx_in[1]
LCx_in[0]
Preliminary
PIC16(L)F1704/8
19.1.2
DATA GATING
19.1.3
TABLE 19-2:
LCxG1POL
Gate Logic
0x55
AND
0x55
NAND
0xAA
NOR
0xAA
OR
0x00
Logic 0
0x00
Logic 1
LOGIC FUNCTION
AND-OR
OR-XOR
AND
S-R Latch
D Flip-Flop with Set and Reset
D Flip-Flop with Reset
J-K Flip-Flop with Reset
Transparent Latch with Set and Reset
19.1.4
OUTPUT POLARITY
CLCxGLS0
Preliminary
DS40001715B-page 209
PIC16(L)F1704/8
19.1.5
19.2
CLCx Interrupts
19.3
19.4
Effects of a Reset
19.5
DS40001715B-page 210
Preliminary
PIC16(L)F1704/8
FIGURE 19-2:
LCx_in[0]
Data GATE 1
LCx_in[31]
lcxd1T
LCxD1G1T
lcxd1N
LCxD1G1N
11111
LCxD2G1T
LCxD1S<4:0>
LCxD2G1N
LCx_in[0]
lcxg1
00000
LCxD3G1T
lcxd2T
LCxG1POL
LCxD3G1N
lcxd2N
LCx_in[31]
LCxD4G1T
11111
LCxD2S<4:0>
LCx_in[0]
LCxD4G1N
00000
Data GATE 2
lcxg2
lcxd3T
lcxd3N
LCx_in[31]
Data GATE 3
11111
lcxg3
LCxD3S<4:0>
LCx_in[0]
00000
lcxg4
(Same as Data GATE 1)
lcxd4T
lcxd4N
LCx_in[31]
11111
LCxD4S<4:0>
Note:
Preliminary
DS40001715B-page 211
PIC16(L)F1704/8
FIGURE 19-3:
OR - XOR
lcxg1
lcxg1
lcxg2
lcxg2
lcxq
lcxg3
lcxq
lcxg3
lcxg4
lcxg4
LCxMODE<2:0>= 000
LCxMODE<2:0>= 001
4-Input AND
S-R Latch
lcxg1
lcxg1
lcxg2
lcxg2
lcxq
lcxg3
lcxg3
lcxg4
lcxg4
LCxMODE<2:0>= 010
lcxq
LCxMODE<2:0>= 011
lcxg4
lcxg2
lcxg4
Q
lcxq
lcxg2
lcxg1
lcxg1
lcxq
R
lcxg3
lcxg3
LCxMODE<2:0>= 100
LCxMODE<2:0>= 101
lcxg2
lcxq
lcxg1
lcxg4
lcxg2
lcxg1
LE
lcxg3
lcxq
lcxg3
LCxMODE<2:0>= 110
DS40001715B-page 212
LCxMODE<2:0>= 111
Preliminary
PIC16(L)F1704/8
19.6
REGISTER 19-1:
R/W-0/0
U-0
R-0/0
R/W-0/0
R/W-0/0
LCxEN
LCxOUT
LCxINTP
LCxINTN
R/W-0/0
R/W-0/0
R/W-0/0
LCxMODE<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a rising edge occurs on lcx_out
0 = CLCxIF will not be set
bit 3
LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a falling edge occurs on lcx_out
0 = CLCxIF will not be set
bit 2-0
Preliminary
DS40001715B-page 213
PIC16(L)F1704/8
REGISTER 19-2:
R/W-0/0
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxPOL
LCxG4POL
LCxG3POL
LCxG2POL
LCxG1POL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS40001715B-page 214
Preliminary
PIC16(L)F1704/8
REGISTER 19-3:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD1S<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
REGISTER 19-4:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD2S<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
REGISTER 19-5:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD3S<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
REGISTER 19-6:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD4S<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
Preliminary
DS40001715B-page 215
PIC16(L)F1704/8
REGISTER 19-7:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG1D4T
LCxG1D4N
LCxG1D3T
LCxG1D3N
LCxG1D2T
LCxG1D2N
LCxG1D1T
LCxG1D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001715B-page 216
Preliminary
PIC16(L)F1704/8
REGISTER 19-8:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG2D4T
LCxG2D4N
LCxG2D3T
LCxG2D3N
LCxG2D2T
LCxG2D2N
LCxG2D1T
LCxG2D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS40001715B-page 217
PIC16(L)F1704/8
REGISTER 19-9:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG3D4T
LCxG3D4N
LCxG3D3T
LCxG3D3N
LCxG3D2T
LCxG3D2N
LCxG3D1T
LCxG3D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001715B-page 218
Preliminary
PIC16(L)F1704/8
REGISTER 19-10: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG4D4T
LCxG4D4N
LCxG4D3T
LCxG4D3N
LCxG4D2T
LCxG4D2N
LCxG4D1T
LCxG4D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS40001715B-page 219
PIC16(L)F1704/8
REGISTER 19-11: CLCDATA: CLC DATA OUTPUT
U-0
U-0
U-0
U-0
U-0
R-0
R-0
R-0
MLC3OUT
MLC2OUT
MLC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
DS40001715B-page 220
Preliminary
PIC16(L)F1704/8
TABLE 19-3:
Name
ANSELA
ANSELB(1)
ANSELC
Bit6
Bit4
BIt3
Bit2
Bit1
Bit0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
125
ANSB4
131
ANSC2
ANSC1
ANSC0
136
Bit5
ANSB5
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
CLC1CON
LC1EN
LC1OUT
LC1INTP
LC1INTN
LC1MODE<2:0>
213
CLC2CON
LC2EN
LC2OUT
LC2INTP
LC2INTN
LC2MODE<2:0>
213
CLC3CON
LC3EN
LC3OUT
LC3INTP
LC3INTN
CLCDATA
MLC3OUT
MLC2OUT
MLC1OUT
220
CLC1GLS0
LC1G1D4T
LC1G1D4N
LC1G1D3T
LC1G1D3N
LC1G1D2T
LC1G1D2N
LC1G1D1T
LC1G1D1N
216
CLC1GLS1
LC1G2D4T
LC1G2D4N
LC1G2D3T
LC1G2D3N
LC1G2D2T
LC1G2D2N
LC1G2D1T
LC1G2D1N
217
CLC1GLS2
LC1G3D4T
LC1G3D4N
LC1G3D3T
LC1G3D3N
LC1G3D2T
LC1G3D2N
LC1G3D1T
LC1G3D1N
218
CLC1GLS3
LC1G4D4T
LC1G4D4N
LC1G4D3T
LC1G4D3N
LC1G4D2T
LC1G4D2N
LC1G4D1T
LC1G4D1N
219
CLC1POL
LC1POL
LC1G4POL
LC1G3POL
LC1G2POL
LC1G1POL
214
LC3MODE<2:0>
213
CLC1SEL0
LC1D1S<4:0>
215
CLC1SEL1
LC1D2S<4:0>
215
CLC1SEL2
LC1D3S<4:0>
215
CLC1SEL3
LC1D4S<4:0>
CLC2GLS0
LC2G1D4T
LC2G1D4N
LC2G1D3T
LC2G1D3N
LC2G1D2T
LC2G1D2N
LC2G1D1T
LC2G1D1N
216
CLC2GLS1
LC2G2D4T
LC2G2D4N
LC2G2D3T
LC2G2D3N
LC2G2D2T
LC2G2D2N
LC2G2D1T
LC2G2D1N
217
CLC2GLS2
LC2G3D4T
LC2G3D4N
LC2G3D3T
LC2G3D3N
LC2G3D2T
LC2G3D2N
LC2G3D1T
LC2G3D1N
218
CLC2GLS3
LC2G4D4T
LC2G4D4N
LC2G4D3T
LC2G4D3N
LC2G4D2T
LC2G4D2N
LC2G4D1T
LC2G4D1N
219
CLC2POL
LC2POL
LC2G4POL
LC2G3POL
LC2G2POL
LC2G1POL
214
CLC2SEL0
LC2D1S<4:0>
215
CLC2SEL1
LC2D2S<4:0>
215
CLC2SEL2
LC2D3S<4:0>
215
CLC2SEL3
LC2D4S<4:0>
215
CLC3GLS0
LC3G1D4T
LC3G1D4N
LC3G1D3T
LC3G1D3N
LC3G1D2T
LC3G1D2N
LC3G1D1T
LC3G1D1N
216
CLC3GLS1
LC3G2D4T
LC3G2D4N
LC3G2D3T
LC3G2D3N
LC3G2D2T
LC3G2D2N
LC3G2D1T
LC3G2D1N
217
CLC3GLS2
LC3G3D4T
LC3G3D4N
LC3G3D3T
LC3G3D3N
LC3G3D2T
LC3G3D2N
LC3G3D1T
LC3G3D1N
218
CLC3GLS3
LC3G4D4T
LC3G4D4N
LC3G4D3T
LC3G4D3N
LC3G4D2T
LC3G4D2N
LC3G4D1T
LC3G4D1N
219
CLC3POL
LC3POL
LC3G4POL
LC3G3POL
LC3G2POL
LC3G1POL
CLC3SEL0
LC3D1S<4:0>
215
CLC3SEL1
LC3D2S<4:0>
215
CLC3SEL2
LC3D3S<4:0>
215
CLC3SEL3
LC3D4S<4:0>
215
CLCxPPS
CLCxPPS<4:0>
141, 142
INTCON
215
214
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE3
COGIE
ZCDIE
CLC3IE
CLC2IE
CLC1IE
89
PIR3
COGIF
ZCDIF
CLC3IF
CLC2IF
CLC1IF
RxyPPS
TRISA
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
124
TRISB7
TRISB6
TRISB5
TRISB4
130
TRISC7(4)
TRISC6(4)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
135
TRISB(4)
TRISC
Legend:
Note 1:
2:
3:
RxyPPS<4:0>
92
143
= unimplemented read as 0. Shaded cells are not used for CLC module.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
Unimplemented, read as 1.
Preliminary
DS40001715B-page 221
PIC16(L)F1704/8
NOTES:
DS40001715B-page 222
Preliminary
PIC16(L)F1704/8
20.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
FIGURE 20-1:
VREF+
ADPREF = 10
VREF- = VSS
AN0
00000
VREF+/AN1
00001
AN2
00010
AN3
00011
AN4
00100
AN5
00101
AN6
00110
AN7
00111
Ref+ Ref-
AN8
01000
ADC
AN9
01001
AN10
01010
AN11
01011
10
GO/DONE
ADFM
0 = Left Justify
1 = Right Justify
16
ADON
FVR Buffer2
11100
Temp Indicator
11101
DAC_output
11110
FVR Buffer1
11111
VSS
ADRESH
ADRESL
CHS<4:0>
Note 1:
Preliminary
DS40001715B-page 223
PIC16(L)F1704/8
20.1
ADC Configuration
20.1.4
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Result formatting
20.1.1
20.1.2
The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
PORT CONFIGURATION
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (internal RC oscillator)
CHANNEL SELECTION
CONVERSION CLOCK
20.1.3
VREF+ pin
VDD
FVR 2.048V
FVR 4.096V (Not available on LF devices)
VSS
DS40001715B-page 224
Preliminary
PIC16(L)F1704/8
TABLE 20-1:
ADC
Clock Source
ADCS<2:0>
32 MHz
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
FOSC/2
000
62.5ns(2)
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
FOSC/4
100
125 ns
(2)
(2)
(2)
(2)
FOSC/8
001
0.5 s(2)
400 ns(2)
0.5 s(2)
FOSC/16
101
800 ns
800 ns
1.0 s
FOSC/32
200 ns
1.0 s
010
250 ns
1.6 s
2.0 s
4.0 s
1.0 s
2.0 s
8.0 s(3)
2.0 s
4.0 s
16.0 s(3)
(3)
4.0 s
110
2.0 s
3.2 s
4.0 s
FRC
x11
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
32.0 s(2)
8.0 s
(3)
FOSC/64
Legend:
Note 1:
2:
3:
4:
1.0 s
500 ns
(2)
8.0 s
64.0 s(2)
16.0 s
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
FIGURE 20-2:
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
TAD9
TAD10
TAD11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
THCD
Conversion Starts
TACQ
Preliminary
DS40001715B-page 225
PIC16(L)F1704/8
20.1.5
INTERRUPTS
20.1.6
RESULT FORMATTING
FIGURE 20-3:
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
Unimplemented: Read as 0
MSB
bit 7
LSB
bit 0
Unimplemented: Read as 0
DS40001715B-page 226
bit 0
bit 7
bit 0
10-bit ADC Result
Preliminary
PIC16(L)F1704/8
20.2
20.2.1
ADC Operation
20.2.4
STARTING A CONVERSION
20.2.2
COMPLETION OF A CONVERSION
20.2.3
TERMINATING A CONVERSION
20.2.5
AUTO-CONVERSION TRIGGER
TABLE 20-2:
AUTO-CONVERSION
SOURCES
Source Peripheral
Signal Name
CCP1
CCP2
Timer0
T0_overflow
Timer1
T1_overflow
Timer2
T2_match
Timer4
T4_match
Timer6
T6_match
Comparator C1
C1OUT_sync
Comparator C2
C2OUT_sync
CLC1
LC1_out
CLC2
LC2_out
CLC3
LC3_out
Preliminary
DS40001715B-page 227
PIC16(L)F1704/8
20.2.6
2.
3.
4.
5.
6.
7.
8.
Configure Port:
Disable pin output driver (Refer to the TRIS
register)
Configure pin as analog (Refer to the ANSEL
register)
Configure the ADC module:
Select ADC conversion clock
Configure voltage reference
Select ADC input channel
Turn on ADC module
Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 20-1:
ADC CONVERSION
DS40001715B-page 228
Preliminary
PIC16(L)F1704/8
20.3
REGISTER 20-1:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CHS<4:0>
R/W-0/0
R/W-0/0
R/W-0/0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-2
bit 1
bit 0
Note 1:
2:
3:
See Section 22.0 8-Bit Digital-to-Analog Converter (DAC1) Module for more information.
See Section 14.0 Fixed Voltage Reference (FVR) for more information.
See Section 15.0 Temperature Indicator Module for more information.
Preliminary
DS40001715B-page 229
PIC16(L)F1704/8
REGISTER 20-2:
R/W-0/0
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
ADCS<2:0>
U-0
U-0
R/W-0/0
R/W-0/0
ADPREF<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3-2
Unimplemented: Read as 0
bit 1-0
Note 1:
When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Table 32-16: ADC Conversion Requirements for details.
DS40001715B-page 230
Preliminary
PIC16(L)F1704/8
REGISTER 20-3:
R/W-0/0
R/W-0/0
R/W-0/0
TRIGSEL<3:0>
R/W-0/0
(1)
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Note 1:
2:
Preliminary
DS40001715B-page 231
PIC16(L)F1704/8
REGISTER 20-4:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 20-5:
R/W-x/u
R/W-x/u
ADRES<1:0>
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
DS40001715B-page 232
Preliminary
PIC16(L)F1704/8
REGISTER 20-6:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1-0
REGISTER 20-7:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Preliminary
DS40001715B-page 233
PIC16(L)F1704/8
20.4
EQUATION 20-1:
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + Temperature - 25C 0.05s/C
The value for TC can be approximated with the following equations:
1
= V CHOLD
V AP P LI ED 1 -------------------------n+1
2
1
TC
----------
RC
V AP P LI ED 1 e = V CHOLD
Tc
---------
1
RC
;combining [1] and [2]
V AP P LI ED 1 e = V A PP LIE D 1 -------------------------n+1
2
1
T C = C HOLD R IC + R SS + R S ln(1/2047)
= 10pF 1k + 7k + 10k ln(0.0004885)
= 1.37 s
Therefore:
T A CQ = 2s + 892ns + 50C- 25C 0.05 s/C
= 4.62s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS40001715B-page 234
Preliminary
PIC16(L)F1704/8
FIGURE 20-4:
Analog
Input
pin
Rs
VT 0.6V
CPIN
5 pF
VA
RIC 1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
VT 0.6V
CHOLD = 10 pF
Ref-
Legend: CHOLD
CPIN
6V
5V
VDD 4V
3V
2V
= Sample/Hold Capacitance
= Input Capacitance
RSS
= Sampling Switch
VT
= Threshold Voltage
Note 1:
FIGURE 20-5:
5 6 7 8 9 10 11
Sampling Switch
(k)
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
3FBh
03h
02h
01h
00h
Ref-
1.5 LSB
Zero-Scale
Transition
Full-Scale
Transition
Preliminary
Ref+
DS40001715B-page 235
PIC16(L)F1704/8
TABLE 20-3:
Name
ADCON0
ADCON1
ADFM
ADCON2
Bit 6
Bit 5
Bit 4
Bit 2
ADPREF<1:0>
230
231
CHS<4:0>
ADCS<2:0>
TRIGSEL<3:0>
Bit 1
Bit 0
GO/DONE
ADON
Register
on Page
Bit 3
229
ADRESH
232, 233
ADRESL
232, 233
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
125
ANSB5
ANSB4
131
ANSELC
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
136
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
90
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
124
TRISB7
TRISB6
TRISB5
TRISB4
130
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
135
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
DAC1EN
DAC1OE1
DAC1OE2
DAC1PSS<1:0>
ANSELB
(1)
TRISA
TRISB(1)
TRISC
FVRCON
DAC1CON0
Legend:
Note 1:
2:
3:
ADFVR<1:0>
DAC1NSS
155
244
x = unknown, u = unchanged, = unimplemented read as 0, q = value depends on condition. Shaded cells are not
used for the ADC module.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
Unimplemented, read as 1.
DS40001715B-page 236
Preliminary
PIC16(L)F1704/8
21.0
OPERATIONAL AMPLIFIER
(OPA) MODULES
FIGURE 21-1:
OPAxIN+
0x
DAC_output
10
FVR Buffer 2
11
OPAXEN
OPAXSP
OPAxIN-
OPA
OPAXOUT
OPAxNCH<1:0>
OPAXUG
Preliminary
DS40001715B-page 237
PIC16(L)F1704/8
21.1
21.1.1
21.1.2
21.2
Effects of Reset
DS40001715B-page 238
Preliminary
PIC16(L)F1704/8
21.3
REGISTER 21-1:
R/W-0/0
R/W-0/0
U-0
R/W-0/0
U-0
U-0
OPAxEN
OPAxSP
OPAxUG
R/W-0/0
R/W-0/0
OPAxCH<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3-2
Unimplemented: Read as 0
bit 1-0
TABLE 21-1:
Name
ANSELB(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSB5
ANSB4
131
ANSELC
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
131
DAC1CON0
DAC1EN
DAC1NSS
244
FVREN
FVRRDY
TSEN
TSRNG
OPA1CON
OPA1EN
OPA1SP
OPA1UG
OPA2CON
OPA2EN
OPA2SP
OPA2UG
DAC1OE1 DAC1OE2
DAC1CON1
FVRCON
(1)
DAC1PSS<1:0>
DAC1R<7:0>
244
CDAFVR<1:0>
ADFVR<1:0>
155
OPA1PCH<1:0>
239
OPA2PCH<1:0>
239
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
130
TRISC
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
135
Legend:
Note 1:
2:
3:
Preliminary
DS40001715B-page 239
PIC16(L)F1704/8
NOTES:
DS40001715B-page 240
Preliminary
PIC16(L)F1704/8
22.0
8-BIT DIGITAL-TO-ANALOG
CONVERTER (DAC1) MODULE
22.1
The DAC has 256 voltage level ranges. The 256 levels
are set with the DAC1R<7:0> bits of the DAC1CON1
register.
The DAC output voltage is determined by Equation 22-1:
EQUATION 22-1:
IF DAC1EN = 1
DAC1R 7:0
VOUT = VSOURCE+ VSOURCE- -------------------------------- + VSOURCE8
2
VSOURCE+ = VDD, VREF, or FVR BUFFER 2
VSOURCE- = VSS
22.2
22.3
Preliminary
DS40001715B-page 241
PIC16(L)F1704/8
FIGURE 22-1:
FVR Buffer2
VSOURCE+
VDD
VREF+
DAC1R<4:0>
R
R
DAC1PSS<1:0>
2
R
DAC1EN
R
256
Steps
R
32-to-1 MUX
R
DAC1_Output
DAC1OUT1
DAC1OE1
DAC1NSS
DAC1OUT2
VREF-
DAC1OE2
VSOURCE-
VSS
FIGURE 22-2:
DAC
Module
R
Voltage
Reference
Output
Impedance
DS40001715B-page 242
DAC1OUTX
Preliminary
PIC16(L)F1704/8
22.4
22.5
Effects of a Reset
Preliminary
DS40001715B-page 243
PIC16(L)F1704/8
22.6
REGISTER 22-1:
R/W-0/0
U-0
R/W-0/0
R/W-0/0
DAC1EN
DAC1OE1
DAC1OE2
R/W-0/0
R/W-0/0
U-0
R/W-0/0
DAC1NSS
DAC1PSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
bit 3-2
bit 1
Unimplemented: Read as 0
bit 0
REGISTER 22-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DAC1R<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
TABLE 22-1:
Name
DAC1CON0
Bit 6
DAC1EN
DAC1CON1
Legend:
Bit 5
Bit 4
DAC1OE1 DAC1OE2
Bit 3
Bit 2
DAC1PSS<1:0>
Bit 1
Bit 0
Register
on page
DAC1NSS
244
DAC1R<7:0>
244
= Unimplemented location, read as 0. Shaded cells are not used with the DAC module.
DS40001715B-page 244
Preliminary
PIC16(L)F1704/8
23.0
ZERO-CROSS DETECTION
(ZCD) MODULE
23.1
FIGURE 23-1:
EQUATION 23-1:
EXTERNAL RESISTOR
PeakVoltage
Resistor = --------------------------------4
3 10
23.2
Ref
External current
limiting resistor
External
voltage
source
ZCDx_output
D
ZCDxPOL
Q1
ZCDxOUT
LE
Interrupt
det
ZCDxINTP
Sets
ZCDIF flag
ZCDxINTN
Interrupt
det
Preliminary
DS40001715B-page 245
PIC16(L)F1704/8
23.3
23.5
23.4
ZCD Interrupts
23.6
Effects of a Reset
DS40001715B-page 246
Preliminary
PIC16(L)F1704/8
23.7
REGISTER 23-1:
R/W-q/q
U-0
R-x/x
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
ZCDxEN
ZCDxOUT
ZCDxPOL
ZCDxINTP
ZCDxINTN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
bit 3-2
Unimplemented: Read as 0
bit 1
bit 0
TABLE 23-1:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
PIE3
COGIE
ZCDIE
CLC3IE
CLC2IE
CLC1IE
89
PIR3
COGIF
ZCDIF
CLC3IF
CLC2IF
CLC1IF
92
ZCD1EN
ZCD1OUT
ZCD1POL
Name
ZCD1CON
Legend:
CONFIG2
Legend:
247
TABLE 23-2:
Name
ZCD1INTP ZCD1INTN
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
Register
on Page
13:8
LVP
DEBUG
LPBOR
BORV
STVREN
PLLEN
52
7:0
ZCDDIS
PPS1WAY
WRT<1:0>
= unimplemented location, read as 0. Shaded cells are not used by the ZCD module.
Preliminary
DS40001715B-page 247
PIC16(L)F1704/8
NOTES:
DS40001715B-page 248
Preliminary
PIC16(L)F1704/8
24.0
TIMER0 MODULE
24.1.2
24.1
Timer0 Operation
24.1.1
FIGURE 24-1:
FOSC/4
Data Bus
0
T0CKI
1
1
8
Sync
2 TCY
TMR0
TMR0SE TMR0CS
8-bit
Prescaler
PSA
PS<2:0>
Preliminary
DS40001715B-page 249
PIC16(L)F1704/8
24.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by
setting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
24.1.4
TIMER0 INTERRUPT
24.1.5
24.1.6
DS40001715B-page 250
Preliminary
PIC16(L)F1704/8
24.2
REGISTER 24-1:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
R/W-1/1
R/W-1/1
R/W-1/1
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TABLE 24-1:
Name
INTCON
TRISA
Timer0 Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
OPTION_REG WPUEN
TMR0
Bit Value
INTEDG
TMR0CS TMR0SE
PSA
PS<2:0>
251
TRISA5
249*
TRISA4
(1)
TRISA2
TRISA1
TRISA0
124
Legend: = Unimplemented location, read as 0. Shaded cells are not used by the Timer0 module.
* Page provides register information.
Note 1: Unimplemented, read as 1.
Preliminary
DS40001715B-page 251
PIC16(L)F1704/8
NOTES:
DS40001715B-page 252
Preliminary
PIC16(L)F1704/8
25.0
FIGURE 25-1:
T1GSS<1:0>
T1GSPM
00
T1G
From Timer0
Overflow
01
sync_C1OUT
10
sync_C2OUT
t1g_in
Single-Pulse
D
CK
R
11
TMR1ON
T1GPOL
T1GTM
T1GVAL
0
1
Acq. Control
Q1
Data Bus
D
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
Set
TMR1GIF
det
TMR1GE
TMR1ON
To Comparator Module
TMR1(2)
TMR1H
EN
TMR1L
T1CLK
Synchronized
clock input
0
1
TMR1CS<1:0>
SOSCO
Reserved
SOSC
SOSCI
T1SYNC
OUT
11
Synchronize(3)
Prescaler
1, 2, 4, 8
det
10
EN
0
T1OSCEN
(1)
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep input
T1CKI
To Clock Switching Modules
Preliminary
DS40001715B-page 253
PIC16(L)F1704/8
25.1
Timer1 Operation
25.2
TABLE 25-1:
TIMER1 ENABLE
SELECTIONS
25.2.1
Timer1
Operation
TMR1ON
TMR1GE
Off
Off
25.2.2
Always On
Count Enabled
TABLE 25-2:
TMR1CS<1:0>
Clock Source
11
LFINTOSC
10
01
00
DS40001715B-page 254
Preliminary
PIC16(L)F1704/8
25.3
Timer1 Prescaler
25.5.1
25.4
25.5
Timer1 Operation in
Asynchronous Counter Mode
25.6
Timer1 Gate
25.6.1
TABLE 25-3:
T1CLK
T1GPOL
T1G
Counts
Holds Count
Holds Count
Counts
Preliminary
Timer1 Operation
DS40001715B-page 255
PIC16(L)F1704/8
25.6.2
TABLE 25-4:
T1GSS
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
11
25.6.2.1
25.6.2.2
25.6.2.3
25.6.2.4
25.6.3
Note:
25.6.4
00
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
25.6.5
When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control
value. The value is stored in the T1GVAL bit in the
T1GCON register. The T1GVAL bit is valid even when
the Timer1 gate is not enabled (TMR1GE bit is
cleared).
25.6.6
DS40001715B-page 256
Preliminary
PIC16(L)F1704/8
25.7
Timer1 Interrupt
25.9
25.8
Section 27.0
FIGURE 25-2:
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
Preliminary
DS40001715B-page 257
PIC16(L)F1704/8
FIGURE 25-3:
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1
FIGURE 25-4:
N+1
N+2
N+3
N+4
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
Timer1
DS40001715B-page 258
N+4
Preliminary
N+8
PIC16(L)F1704/8
FIGURE 25-5:
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
TMR1GIF
N+1
Set by hardware on
falling edge of T1GVAL
Cleared by software
N+2
Preliminary
Cleared by
software
DS40001715B-page 259
PIC16(L)F1704/8
FIGURE 25-6:
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
TMR1GIF
DS40001715B-page 260
Cleared by software
N+1
N+2
N+3
N+4
Set by hardware on
falling edge of T1GVAL
Preliminary
Cleared by
software
PIC16(L)F1704/8
25.11 Register Definitions: Timer1 Control
T
REGISTER 25-1:
R/W-0/u
R/W-0/u
TMR1CS<1:0>
R/W-0/u
R/W-0/u
T1CKPS<1:0>
R/W-0/u
R/W-0/u
U-0
R/W-0/u
T1OSCEN
T1SYNC
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3
bit 2
bit 1
Unimplemented: Read as 0
bit 0
Preliminary
DS40001715B-page 261
PIC16(L)F1704/8
REGISTER 25-2:
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
R/W-0/u
R/W-0/u
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
DS40001715B-page 262
Preliminary
PIC16(L)F1704/8
TABLE 25-5:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
125
CCP1CON
DC1B<1:0>
CCP1M<3:0>
CCP2CON
DC2B<1:0>
CCP2M<3:0>
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
Name
INTCON
PIE1
PIR1
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TRISA
T1CON
T1GCON
Legend:
*
Note 1:
TMR1CS<1:0>
TMR1GE
T1GPOL
TRISA5
TRISA4
T1CKPS<1:0>
T1GTM
T1GSPM
280
280
90
253*
253*
(1)
TRISA2
TRISA1
TRISA0
124
T1OSCEN
T1SYNC
TMR1ON
261
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
262
= unimplemented location, read as 0. Shaded cells are not used by the Timer1 module.
Page provides register information.
Unimplemented, read as 1.
Preliminary
DS40001715B-page 263
PIC16(L)F1704/8
NOTES:
DS40001715B-page 264
Preliminary
PIC16(L)F1704/8
26.0
TIMER2/4/6 MODULE
timers
that
FIGURE 26-1:
Fosc/4
Prescaler
1:1, 1:4, 1:16, 1:64
T2_match
TMR2
To Peripherals
2
T2CKPS<1:0>
Comparator
Postscaler
1:1 to 1:16
set bit
TMR2IF
4
PR2
Preliminary
T2OUTPS<3:0>
DS40001715B-page 265
PIC16(L)F1704/8
26.1
Timer2 Operation
26.3
Timer2 Output
26.4
26.2
Timer2 Interrupt
DS40001715B-page 266
Preliminary
PIC16(L)F1704/8
26.5
REGISTER 26-1:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
T2OUTPS<3:0>
R/W-0/0
R/W-0/0
TMR2ON
bit 7
R/W-0/0
T2CKPS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
Preliminary
DS40001715B-page 267
PIC16(L)F1704/8
TABLE 26-1:
Bit 6
CCP2CON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
90
PR2
INTCON
PIE1
T2CON
TMR2
Bit 5
Bit 4
Bit 3
DC2B<1:0>
Bit 2
Bit 1
Bit 0
Register
on Page
Name
CCP2M<3:0>
280
265*
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
267
265*
Legend: = unimplemented location, read as 0. Shaded cells are not used for Timer2 module.
* Page provides register information.
DS40001715B-page 268
Preliminary
PIC16(L)F1704/8
26.6
26.7
REGISTER 26-2:
R/W-0/0
R/W-0/0
P4TSEL<1:0>
R/W-0/0
R/W-0/0
R/W-0/0
P3TSEL<1:0>
R/W-0/0
R/W-0/0
C2TSEL<1:0>
bit 7
R/W-0/0
C1TSEL<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3-2
bit 1-0
Preliminary
DS40001715B-page 269
PIC16(L)F1704/8
NOTES:
DS40001715B-page 270
Preliminary
PIC16(L)F1704/8
27.0
CAPTURE/COMPARE/PWM
MODULES
Preliminary
DS40001715B-page 271
PIC16(L)F1704/8
27.1
Capture Mode
27.1.2
27.1.1
FIGURE 27-1:
Prescaler
1, 4, 16
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Set Flag bit CCPxIF
(PIRx register)
CCPx
pin
CCPRxH
and
Edge Detect
DS40001715B-page 272
27.1.3
27.1.4
CCP PRESCALER
EXAMPLE 27-1:
CCPRxL
Capture
Enable
TMR1H
CCPxM<3:0>
System Clock (FOSC)
TMR1L
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCPxCON
CLRF
MOVLW
MOVWF
Preliminary
PIC16(L)F1704/8
27.1.5
Preliminary
DS40001715B-page 273
PIC16(L)F1704/8
27.2
Compare Mode
27.2.2
FIGURE 27-2:
S
R
Output
Logic
Match
TRIS
Output Enable
Comparator
TMR1H
TMR1L
Auto-conversion Trigger
27.2.1
DS40001715B-page 274
AUTO-CONVERSION TRIGGER
Resets Timer1
Starts an ADC conversion if ADC is enabled
CCPxM<3:0>
Mode Select
CCPx
Pin
27.2.3
27.2.4
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Preliminary
PIC16(L)F1704/8
27.2.5
Preliminary
DS40001715B-page 275
PIC16(L)F1704/8
27.3
PWM Overview
FIGURE 27-3:
Period
Pulse Width
TMR2 = 0
FIGURE 27-4:
CCP1CON<5:4>
CCPR1L
CCPR1H(2) (Slave)
CCP1
R
Comparator
(1)
TMR2
S
TRIS
Comparator
PR2
Note
TMR2 = PR2
TMR2 = CCPRxH:CCPxCON<5:4>
27.3.1
1:
2:
Clear Timer,
toggle CCP1 pin and
latch duty cycle
PR2 registers
T2CON registers
CCPRxL registers
CCPxCON registers
DS40001715B-page 276
Preliminary
PIC16(L)F1704/8
27.3.2
2.
3.
4.
5.
6.
27.3.3
TMR2 is cleared
The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
The PWM duty cycle is latched from CCPRxL into
CCPRxH.
Note:
27.3.5
EQUATION 27-2:
EQUATION 27-3:
27.3.4
PULSE WIDTH
CCPRxL:CCPxCON<5:4>
Duty Cycle Ratio = ----------------------------------------------------------------------4 PR2 + 1
PWM PERIOD
EQUATION 27-1:
PWM PERIOD
TOSC = 1/FOSC
Preliminary
DS40001715B-page 277
PIC16(L)F1704/8
27.3.6
PWM RESOLUTION
EQUATION 27-4:
TABLE 27-1:
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
Note:
PWM Frequency
Timer Prescale
PR2 Value
Maximum Resolution (bits)
TABLE 27-2:
PWM RESOLUTION
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
PWM Frequency
Timer Prescale
PR2 Value
Maximum Resolution (bits)
DS40001715B-page 278
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
0x65
0x65
0x65
0x19
0x0C
0x09
Preliminary
PIC16(L)F1704/8
27.3.7
27.3.8
27.3.9
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 27-3:
Name
CCP1CON
CCPR1L
CCPTMRS
INTCON
PIE1
Bit 6
Bit 5
Bit 4
Bit 3
DC1B<1:0>
Bit 2
Bit 1
Bit 0
CCP1M<3:0>
280
Register
on Page
277*
P3TSEL<1:0>
C2TSEL<1:0>
C1TSEL<1:0>
269
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
88
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
90
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
PIR2
PR2
RxyPPS
T2CON
TMR2
91
265*
RxyPPS<4:0>
T2OUTPS<3:0>
TMR2ON
143
T2CKPS<1:0>
267
265
Legend: = Unimplemented location, read as 0. Shaded cells are not used by the PWM.
* Page provides register information.
Note 1: Unimplemented, read as 1.
Preliminary
DS40001715B-page 279
PIC16(L)F1704/8
27.4
REGISTER 27-1:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
DCxB<1:0>
R/W-0/0
R/W-0/0
R/W-0/0
CCPxM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3-0
0011 =
0010 =
0001 =
0000 =
Reserved
Compare mode: toggle output on match
Reserved
Capture/Compare/PWM off (resets CCPx module)
DS40001715B-page 280
Preliminary
PIC16(L)F1704/8
28.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
28.1
Master mode
Slave mode
Clock Parity
Slave Select Synchronization (Slave mode only)
Daisy-chain connection of slave devices
FIGURE 28-1:
Write
SSPBUF Reg
SDI
SSPSR Reg
SDO
bit 0
SS
SS Control
Enable
Shift
Clock
2 (CKP, CKE)
Clock Select
Edge
Select
SSPM<3:0>
4
SCK
Edge
Select
TRIS bit
Preliminary
T2_match
2
Prescaler TOSC
4, 16, 64
Baud Rate
Generator
(SSPADD)
DS40001715B-page 281
PIC16(L)F1704/8
The I2C interface supports the following modes and
features:
Master mode
Slave mode
Byte NACKing (Slave mode)
Limited multi-master support
7-bit and 10-bit addressing
Start and Stop interrupts
Interrupt masking
Clock stretching
Bus collision detection
General call address matching
Address masking
Address Hold and Data Hold modes
Selectable SDA hold times
Figure 28-2 is a block diagram of the I2C interface module in Master mode. Figure 28-3 is a diagram of the I2C
interface module in Slave mode.
[SSPM<3:0>]
Write
SSP1BUF
Shift
Clock
SDA in
SCL
SCL in
Bus Collision
DS40001715B-page 282
LSb
Preliminary
Clock Cntl
SSPSR
MSb
SDA
Baud Rate
Generator
(SSPADD)
FIGURE 28-2:
PIC16(L)F1704/8
FIGURE 28-3:
Write
SSPBUF Reg
SCL
Shift
Clock
SSPSR Reg
SDA
MSb
LSb
SSPMSK Reg
Match Detect
Addr Match
SSPADD Reg
Start and
Stop bit Detect
Preliminary
Set, Reset
S, P bits
(SSPSTAT Reg)
DS40001715B-page 283
PIC16(L)F1704/8
28.2
DS40001715B-page 284
Preliminary
PIC16(L)F1704/8
FIGURE 28-4:
SPI Master
SCK
SCK
SDO
SDI
SDI
SDO
General I/O
General I/O
SS
General I/O
SCK
SDI
SDO
SPI Slave
#1
SPI Slave
#2
SS
SCK
SDI
SDO
SPI Slave
#3
SS
28.2.1
Preliminary
DS40001715B-page 285
PIC16(L)F1704/8
28.2.2
DS40001715B-page 286
Preliminary
PIC16(L)F1704/8
FIGURE 28-5:
SDO
LSb
SCK
General I/O
Processor 1
SDO
SDI
Shift Register
(SSPSR)
MSb
Serial Clock
Slave Select
(optional)
Preliminary
Shift Register
(SSPSR)
MSb
LSb
SCK
SS
Processor 2
DS40001715B-page 287
PIC16(L)F1704/8
28.2.3
DS40001715B-page 288
Preliminary
PIC16(L)F1704/8
FIGURE 28-6:
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
Preliminary
DS40001715B-page 289
PIC16(L)F1704/8
28.2.4
28.2.5
Daisy-Chain Configuration
SLAVE SELECT
SYNCHRONIZATION
DS40001715B-page 290
Preliminary
PIC16(L)F1704/8
FIGURE 28-7:
SPI Master
SCK
SCK
SDO
SDI
SDI
SPI Slave
#1
SDO
General I/O
SS
SCK
SDI
SPI Slave
#2
SDO
SS
SCK
SDI
SPI Slave
#3
SDO
SS
FIGURE 28-8:
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SSPBUF to
SSPSR
SDO
bit 7
bit 6
bit 7
SDI
bit 6
bit 0
bit 0
bit 7
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Preliminary
DS40001715B-page 291
PIC16(L)F1704/8
FIGURE 28-9:
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 0
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
FIGURE 28-10:
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 0
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
DS40001715B-page 292
Preliminary
PIC16(L)F1704/8
28.2.6
TABLE 28-1:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
ANSA4
ANSA2
ANSA1
ANSA0
125
ANSELC
ANSC7(2)
ANSC6(2)
ANSC5(3)
ANSC4(3)
ANSC3
ANSC2
ANSC1
ANSC0
136
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
TMR1GIF
ADIF
RCIF
RxyPPS
RxyPPS<4:0>
SSPCLKPPS
SSPCLKPPS<4:0>
141, 142
SSPDATPPS
SSPDATPPS<4:0>
141, 142
SSPSSPPS
SSPSSPPS<4:0>
141, 142
SSP1BUF
90
143
285*
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SSP1STAT
SMP
CKE
D/A
R/W
UA
BF
330
TRISA5
TRISA4
(1)
TRISA2
TRISA1
TRISA0
124
TRISB7
TRISB6
TRISB5
TRISB4
130
TRISC7(2)
TRISC6(2)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISA0
135
TRISA
TRISB(2)
TRISC
Legend:
*
Note 1:
2:
3:
SSPM<3:0>
SDAHT
SBCDE
332
AHEN
DHEN
330
= Unimplemented location, read as 0. Shaded cells are not used by the MSSP in SPI mode.
Page provides register information.
Unimplemented, read as 1.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
Preliminary
DS40001715B-page 293
PIC16(L)F1704/8
28.3
FIGURE 28-11:
VDD
SCL
SDA
DS40001715B-page 294
Slave
SDA
SCL
VDD
Master
I2C MASTER/
SLAVE CONNECTION
Preliminary
PIC16(L)F1704/8
When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCL line, is called clock stretching.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on
the SDA line, it is called arbitration. Arbitration ensures
that there is only one master device communicating at
any single time.
28.3.1
CLOCK STRETCHING
28.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a transmission on or about the same time. When this occurs,
the process of arbitration begins. Each transmitter
checks the level of the SDA data line and compares it
to the level that it expects to find. The first transmitter to
observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line.
For example, if one transmitter holds the SDA line to a
logical one (lets it float) and a second transmitter holds
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any complications, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
If two master devices are sending a message to two
different slave devices at the address stage, the master
sending the lower slave address always wins arbitration. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.
Preliminary
DS40001715B-page 295
PIC16(L)F1704/8
28.4
TABLE 28-2:
BYTE FORMAT
TERM
Transmitter
DS40001715B-page 296
Preliminary
PIC16(L)F1704/8
28.4.5
28.4.7
START CONDITION
RESTART CONDITION
STOP CONDITION
FIGURE 28-12:
SDA
SCL
S
Start
P
Change of
Change of
Data Allowed
Data Allowed
Condition
FIGURE 28-13:
Stop
Condition
Sr
Change of
Change of
Data Allowed
Restart
Data Allowed
Condition
Preliminary
DS40001715B-page 297
PIC16(L)F1704/8
28.4.9
28.5
ACKNOWLEDGE SEQUENCE
DS40001715B-page 298
Preliminary
PIC16(L)F1704/8
28.5.2
28.5.2.2
SLAVE RECEPTION
Preliminary
DS40001715B-page 299
DS40001715B-page 300
Preliminary
SSPOV
BF
SSPIF
A7
A6
A5
A4
A3
A2
A1
ACK
D7
D6
D4
D3
D2
D1
SSPBUF is read
Cleared by software
D5
Receiving Data
D6
First byte
of data is
available
in SSPBUF
D0 ACK D7
D4
D3
D2
D1
Cleared by software
D5
Receiving Data
D0
ACK = 1
FIGURE 28-14:
SCL
SDA
Receiving Address
PIC16(L)F1704/8
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
Preliminary
CKP
SSPOV
BF
SSPIF
SCL
A7
A6
A5
A4
A3
A2
A1
R/W=0 ACK
SEN
2
D6
D5
D4
D3
D2
D1
D0
SSPBUF is read
Cleared by software
D7
Receive Data
ACK
SEN
3
D5
D4
D3
First byte
of data is
available
in SSPBUF
D2
D1
Cleared by software
D6
D7
Receive Data
D0
ACK
FIGURE 28-15:
SDA
Receive Address
PIC16(L)F1704/8
DS40001715B-page 301
DS40001715B-page 302
Preliminary
ACKTIM
CKP
ACKDT
BF
SSPIF
Receiving Address
Slave software
clears ACKDT to
Address is
read from
SSBUF
If AHEN = 1:
SSPIF is set
When AHEN=1:
CKP is cleared by hardware
and SCL is stretched
A7 A6 A5 A4 A3 A2 A1
Receiving Data
9
2
ACKTIM cleared by
hardware in 9th
rising edge of SCL
When DHEN=1:
CKP is cleared by
hardware on 8th falling
edge of SCL
SSPIF is set on
9th falling edge of
SCL, after ACK
ACK D7 D6 D5 D4 D3 D2 D1 D0
Received Data
Slave software
sets ACKDT to
not ACK
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
No interrupt
after not ACK
from Slave
ACK=1
Master sends
Stop condition
FIGURE 28-16:
SCL
SDA
PIC16(L)F1704/8
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
Preliminary
ACKTIM
CKP
ACKDT
BF
SSPIF
Receiving Address
4
5
6 7
When AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
Received
address is loaded into
SSPBUF
2 3
A7 A6 A5 A4 A3 A2 A1
ACK
Receive Data
2 3
6 7
When DHEN = 1;
on the 8th falling edge
of SCL of a received
data byte, CKP is cleared
Received data is
available on SSPBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Receive Data
1
3 4
6 7
Set by software,
release SCL
Slave sends
not ACK
SSPBUF can be
read any time before
next byte is loaded
D7 D6 D5 D4 D3 D2 D1 D0
ACK
No interrupt after
if not ACK
from Slave
Master sends
Stop condition
FIGURE 28-17:
SCL
SDA
R/W = 0
Master releases
SDA to slave for ACK sequence
PIC16(L)F1704/8
DS40001715B-page 303
PIC16(L)F1704/8
28.5.3
SLAVE TRANSMISSION
28.5.3.2
7-bit Transmission
1.
28.5.3.1
DS40001715B-page 304
Preliminary
Preliminary
D/A
R/W
ACKSTAT
CKP
BF
SSPIF
Receiving Address
Received address
is read from SSPBUF
Indicates an address
has been received
A7 A6 A5 A4 A3 A2 A1
8
R/W = 1 Automatic
ACK
Transmitting Data
Automatic
Set by software
Data to transmit is
loaded into SSPBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting Data
CKP is not
held for not
ACK
BF is automatically
cleared after 8th falling
edge of SCL
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
FIGURE 28-18:
SCL
SDA
Master sends
Stop condition
PIC16(L)F1704/8
DS40001715B-page 305
PIC16(L)F1704/8
28.5.3.3
DS40001715B-page 306
Preliminary
Preliminary
D/A
R/W
ACKTIM
CKP
ACKSTAT
ACKDT
BF
SSPIF
Receiving Address
Slave clears
ACKDT to ACK
address
ACK
When R/W = 1;
CKP is always
cleared after ACK
R/W = 1
Received address
is read from SSPBUF
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
A7 A6 A5 A4 A3 A2 A1
3
Cleared by software
Set by software,
releases SCL
Data to transmit is
loaded into SSPBUF
Transmitting Data
Automatic
D7 D6 D5 D4 D3 D2 D1 D0 ACK
ACKTIM is cleared
on 9th rising edge of SCL
Automatic
Transmitting Data
Masters ACK
response is copied
to SSPSTAT
BF is automatically
cleared after 8th falling
edge of SCL
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
Master sends
Stop condition
FIGURE 28-19:
SCL
SDA
PIC16(L)F1704/8
DS40001715B-page 307
PIC16(L)F1704/8
28.5.4
28.5.5
3.
4.
5.
6.
7.
8.
DS40001715B-page 308
Preliminary
Preliminary
CKP
UA
BF
SSPIF
1
5
0 A9 A8
Set by hardware
on 9th falling edge
When UA = 1;
SCL is held low
If address matches
SSPADD it is loaded into
SSPBUF
ACK
A7 A6 A5 A4 A3 A2 A1 A0 ACK
9
1
Data is read
from SSPBUF
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
Set by software,
When SEN = 1;
releasing SCL
CKP is cleared after
9th falling edge of received byte
Receive address is
read from SSPBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
FIGURE 28-20:
SCL
SDA
Master sends
Stop condition
PIC16(L)F1704/8
DS40001715B-page 309
DS40001715B-page 310
Preliminary
ACKTIM
CKP
UA
ACKDT
BF
A9
A8
Set by hardware
on 9th falling edge
If when AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
R/W = 0
ACK
UA
A6
A5
A4
A3
A2
A1
Update to SSPADD is
not allowed until 9th
falling edge of SCL
SSPBUF can be
read anytime before
the next received byte
Cleared by software
A7
A0
ACK
UA
D6
D5
D4
D2
D1
Update of SSPADD,
clears UA and releases
SCL
D3
Receive Data
Cleared by software
D7
Received data
is read from
SSPBUF
D6 D5
Receive Data
D0 ACK D7
FIGURE 28-21:
SSPIF
SCL
SDA
PIC16(L)F1704/8
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
Preliminary
D/A
R/W
ACKSTAT
CKP
UA
BF
SSPIF
Set by hardware
Indicates an address
has been received
UA indicates SSPADD
must be updated
SSPBUF loaded
with received address
SCL
1
3
7 8
After SSPADD is
updated, UA is cleared
and SCL is released
Cleared by software
A7 A6 A5 A4 A3 A2 A1 A0 ACK
1
4
7 8
Set by hardware
2 3
When R/W = 1;
CKP is cleared on
9th falling edge of SCL
Received address is
read from SSPBUF
Sr
1 1 1 1 0 A9 A8
ACK
Set by software
releases SCL
Data to transmit is
loaded into SSPBUF
D7 D6 D5 D4 D3 D2 D1 D0
Master sends
Stop condition
ACK = 1
Master sends
not ACK
FIGURE 28-22:
SDA
Master sends
Restart event
PIC16(L)F1704/8
DS40001715B-page 311
PIC16(L)F1704/8
28.5.6
CLOCK STRETCHING
28.5.6.2
FIGURE 28-23:
Byte NACKing
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an
external I2C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I2C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 28-23).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX 1
DX
SCL
CKP
Master device
asserts clock
Master device
releases clock
WR
SSPCON1
DS40001715B-page 312
Preliminary
PIC16(L)F1704/8
28.5.8
FIGURE 28-24:
SDA
SCL
S
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
SSPIF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
GCEN (SSPCON2<7>)
28.5.9
Preliminary
DS40001715B-page 313
PIC16(L)F1704/8
28.6
28.6.1
DS40001715B-page 314
Preliminary
PIC16(L)F1704/8
28.6.2
CLOCK ARBITRATION
FIGURE 28-25:
SDA
DX 1
DX
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
03h
02h
28.6.3
Preliminary
DS40001715B-page 315
PIC16(L)F1704/8
28.6.4
CONDITION TIMING
FIGURE 28-26:
SDA = 1,
SCL = 1
TBRG
TBRG
SDA
1st bit
2nd bit
TBRG
SCL
S
DS40001715B-page 316
Preliminary
TBRG
PIC16(L)F1704/8
28.6.5
FIGURE 28-27:
Write to SSPCON2
occurs here
SDA = 1,
SCL (no change)
SDA = 1,
SCL = 1
TBRG
TBRG
TBRG
1st bit
SDA
Sr
TBRG
Repeated Start
Preliminary
DS40001715B-page 317
PIC16(L)F1704/8
28.6.6
28.6.6.3
28.6.6.1
7.
8.
9.
10.
11.
12.
13.
BF Status Flag
28.6.6.2
DS40001715B-page 318
Preliminary
Preliminary
R/W
PEN
SEN
BF (SSPSTAT<0>)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
Cleared by software
SSPBUF written
D7
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
A7
D5
D4
D3
D2
D1
D0
D6
Cleared by software
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 28-28:
SEN = 0
PIC16(L)F1704/8
DS40001715B-page 319
PIC16(L)F1704/8
28.6.7
28.6.7.4
28.6.7.1
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
BF Status Flag
11.
28.6.7.2
12.
13.
14.
28.6.7.3
15.
DS40001715B-page 320
Preliminary
Preliminary
RCEN
ACKEN
SSPOV
BF
(SSPSTAT<0>)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
A7
4
5
Cleared by software
A6 A5 A4 A3 A2
7
8
ACK
D0
ACK
RCEN cleared
automatically
5
6
Cleared by software
Cleared in
software
ACK
P
Set SSPIF interrupt
at end of Acknowledge sequence
Bus master
terminates
transfer
Set P bit
(SSPSTAT<4>)
and SSPIF
PEN bit = 1
written here
D0
RCEN cleared
automatically
D7 D6 D5 D4 D3 D2 D1
RCEN cleared
automatically
RCEN = 1, start
next receive
Cleared by software
Cleared by software
D7 D6 D5 D4 D3 D2 D1
RCEN cleared
automatically
A1 R/W
FIGURE 28-29:
SCL
SDA
SEN = 0
Write to SSPBUF occurs here,
start XMIT
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
PIC16(L)F1704/8
DS40001715B-page 321
PIC16(L)F1704/8
28.6.8
ACKNOWLEDGE SEQUENCE
TIMING
28.6.9
28.6.8.1
28.6.9.1
FIGURE 28-30:
TBRG
SDA
ACK
D0
SCL
SSPIF
SSPIF set at
the end of receive
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
Cleared in
software
FIGURE 28-31:
Write to SSPCON2,
set PEN
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
DS40001715B-page 322
Preliminary
PIC16(L)F1704/8
28.6.10
SLEEP OPERATION
28.6.13
28.6.11
EFFECTS OF A RESET
28.6.12
MULTI-MASTER MODE
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a 1 on SDA, by letting SDA float high and
another master asserts a 0. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a 1 and the data sampled on the SDA pin is 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 28-32).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2
register are cleared. When the user services the bus
collision Interrupt Service Routine and if the I2C bus is
free, the user can resume communication by asserting a
Start condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 28-32:
SDA
SCL
BCLIF
Preliminary
DS40001715B-page 323
PIC16(L)F1704/8
28.6.13.1
FIGURE 28-33:
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN
BCLIF
SSPIF
SSPIF and BCLIF are
cleared by software
DS40001715B-page 324
Preliminary
PIC16(L)F1704/8
FIGURE 28-34:
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
by software
S
SSPIF
FIGURE 28-35:
SDA
Set SSPIF
TBRG
SCL
SEN
BCLIF
SSPIF
SDA = 0, SCL = 1,
set SSPIF
Preliminary
Interrupts cleared
by software
DS40001715B-page 325
PIC16(L)F1704/8
28.6.13.2
FIGURE 28-36:
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared by software
S
SSPIF
FIGURE 28-37:
TBRG
SDA
SCL
BCLIF
RSEN
S
SSPIF
DS40001715B-page 326
Preliminary
PIC16(L)F1704/8
28.6.13.3
b)
FIGURE 28-38:
TBRG
TBRG
SDA
SDA sampled
low after TBRG,
set BCLIF
SSPIF
FIGURE 28-39:
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
SSPIF
Preliminary
DS40001715B-page 327
PIC16(L)F1704/8
TABLE 28-3:
Name
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page:
ANSA4
ANSA2
ANSA1
ANSA0
125
ANSB5
ANSB4
131
Bit 7
Bit 6
ANSELA
ANSELB(1)
(1)
ANSELC
ANSC6
(2)
ANSC5
(2)
ANSC4
ANSC3
ANSC2
ANSC1
ANSC0
136
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
ANSC7
INTCON
(1)
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIE2
OSFIE
C2IE
C1IE
BCL1IE
TMR6IE
TMR4IE
CCP2IE
88
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
90
PIR2
OSFIF
C2IF
C1IF
BCL1IF
TMR6IF
TMR4IF
CCP2IF
91
RxyPPS
RxyPPS<4:0>
143
SSPCLKPPS
SSPCLKPPS<4:0>
141, 142
SSPDATPPS
SSPDATPPS<4:0>
141, 142
SSPSSPPS
SSPSSPPS<4:0>
141, 142
SSP1ADD
SSP1BUF
SSP1CON1
ADD<7:0>
335
285*
WCOL
SSPOV
SSPEN
CKP
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
333
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
334
SMP
CKE
D/A
R/W
UA
BF
330
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
124
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
130
TRISC
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISA0
135
SSP1MSK
SSP1STAT
TRISA
(1)
Legend:
*
Note 1:
2:
3:
SSPM<3:0>
332
MSK<7:0>
335
= unimplemented location, read as 0. Shaded cells are not used by the MSSP module in I2C mode.
Page provides register information.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
Unimplemented, read as 1.
DS40001715B-page 328
Preliminary
PIC16(L)F1704/8
28.7
The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPADD register (Register 28-6).
When a write occurs to SSPBUF, the Baud Rate
Generator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
EQUATION 28-1:
FOSC
FCLOCK = ------------------------------------------------ SSPxADD + 1 4
FIGURE 28-40:
SSPM<3:0>
Reload
SSPADD<7:0>
Reload
Control
SCL
SSPCLK
FOSC/2
TABLE 28-4:
Note:
FOSC
FCY
BRG Value
FCLOCK
(2 Rollovers of BRG)
32 MHz
8 MHz
13h
400 kHz
32 MHz
8 MHz
19h
308 kHz
32 MHz
8 MHz
4Fh
100 kHz
16 MHz
4 MHz
09h
400 kHz
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
Refer to the I/O port electrical specifications in Table 32-4 to ensure the system is designed to support IOL
requirements.
Preliminary
DS40001715B-page 329
PIC16(L)F1704/8
28.8
REGISTER 28-1:
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 4
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is 0 on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is 0 on Reset)
0 = Start bit was not detected last
bit 2
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1
DS40001715B-page 330
Preliminary
PIC16(L)F1704/8
REGISTER 28-1:
bit 0
Preliminary
DS40001715B-page 331
PIC16(L)F1704/8
REGISTER 28-2:
R/C/HS-0/0
R/C/HS-0/0
R/W-0/0
R/W-0/0
WCOL
SSPOV(1)
SSPEN
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
C = User cleared
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note
1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output. Use SSPSSPPS, SSPCLKPPS, SSPDATPPS, and RxyPPS
to select the pins.
When enabled, the SDA and SCL pins must be configured as inputs. Use SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins.
SSPADD values of 0, 1 or 2 are not supported for I2C mode.
SSPADD value of 0 is not supported. Use SSPM = 0000 instead.
DS40001715B-page 332
Preliminary
PIC16(L)F1704/8
SSP1CON2: SSP CONTROL REGISTER 2(1)
REGISTER 28-3:
R/W-0/0
R-0/0
R/W-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/W/HS-0/0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
HC = Cleared by hardware
S = User set
bit 7
GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0 = General call address disabled
bit 6
bit 5
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3
bit 2
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
Preliminary
DS40001715B-page 333
PIC16(L)F1704/8
REGISTER 28-4:
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ACKTIM(3)
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the
BCL1IF bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1
bit 0
Note 1:
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
DS40001715B-page 334
Preliminary
PIC16(L)F1704/8
REGISTER 28-5:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
MSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-1
bit 0
REGISTER 28-6:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
Master mode:
bit 7-0
Not used: Unused for Most Significant Address Byte. Bit state of this register is a dont care. Bit
pattern sent by master is fixed by I2C specification and must be equal to 11110. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1
bit 0
bit 0
Preliminary
DS40001715B-page 335
PIC16(L)F1704/8
NOTES:
DS40001715B-page 336
Preliminary
PIC16(L)F1704/8
29.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
FIGURE 29-1:
TXIE
Interrupt
TXIF
TXREG Register
8
MSb
LSb
(8)
TX/CK pin
Pin Buffer
and Control
FOSC
TX9
BRG16
+1
SPBRGH
SPBRGL
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
TX9D
Preliminary
DS40001715B-page 337
PIC16(L)F1704/8
FIGURE 29-2:
CREN
RX/DT pin
Data
Recovery
FOSC
SPBRGH
SPBRGL
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
Stop
(8)
LSb
0 Start
RX9
BRG16
+1
RSR Register
MSb
Pin Buffer
and Control
RCIDL
OERR
FERR
RX9D
RCREG Register
8
FIFO
Data Bus
RCIF
RCIE
Interrupt
DS40001715B-page 338
Preliminary
PIC16(L)F1704/8
29.1
29.1.1.2
Transmitting Data
29.1.1.3
29.1.1
29.1.1.4
EUSART ASYNCHRONOUS
TRANSMITTER
29.1.1.1
Preliminary
DS40001715B-page 339
PIC16(L)F1704/8
29.1.1.5
TSR Status
29.1.1.7
29.1.1.6
1.
2.
3.
FIGURE 29-3:
Write to TXREG
BRG Output
(Shift Clock)
TX/CK
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
DS40001715B-page 340
4.
5.
6.
7.
8.
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
1 TCY
Word 1
Transmit Shift Reg.
Preliminary
PIC16(L)F1704/8
FIGURE 29-4:
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
TX/CK
pin
Start bit
bit 0
bit 1
Word 1
1 TCY
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
bit 7/8
Stop bit
Start bit
Word 2
bit 0
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 2
Transmit Shift Reg.
Note:
TABLE 29-1:
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
ANSA4
ANSA2
ANSA1
ANSA0
125
ANSB5
ANSB4
131
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
136
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
349
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
90
RC1STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
348
RxyPPS
Name
Bit 7
Bit 6
ANSELA
ANSELB(1)
ANSELC
BAUD1CON
INTCON
RxyPPS<4:0>
143
SP1BRGL
BRG<7:0>
350*
SP1BRGH
BRG<15:8>
350*
TRISA
TRISB(2)
TRISC
TX1REG
TX1STA
Legend:
*
Note 1:
2:
3:
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
TRISB7
TRISB6
TRISB5
TRISB4
130
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
135
SYNC
SENDB
BRGH
TRMT
TX9D
TX9
TXEN
124
339*
347
= unimplemented location, read as 0. Shaded cells are not used for asynchronous transmission.
Page provides register information.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
Unimplemented, read as 1.
Preliminary
DS40001715B-page 341
PIC16(L)F1704/8
29.1.2
EUSART ASYNCHRONOUS
RECEIVER
29.1.2.2
29.1.2.1
Receiving Data
29.1.2.3
Receive Interrupts
DS40001715B-page 342
Preliminary
PIC16(L)F1704/8
29.1.2.4
29.1.2.7
29.1.2.5
Address Detection
29.1.2.6
Preliminary
DS40001715B-page 343
PIC16(L)F1704/8
29.1.2.8
29.1.2.9
1.
FIGURE 29-5:
Rcv Shift
Reg
Rcv Buffer Reg.
RCIDL
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX/DT pin
bit 1
Start
bit
bit 0
Word 1
RCREG
Start
bit
bit 7/8
Stop
bit
Word 2
RCREG
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS40001715B-page 344
Preliminary
PIC16(L)F1704/8
TABLE 29-2:
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
125
ANSB5
ANSB4
131
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
136
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
349
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
90
RC1STA
SPEN
RX9
SREN
OERR
RX9D
RxyPPS
Name
Bit 7
Bit 6
ANSELA
ANSELB(1)
ANSELC
BAUD1CON
INTCON
RC1REG
SP1BRGL
TRISB(1)
TRISC
TX1STA
Legend:
*
Note 1:
2:
3:
ADDEN
342*
FERR
RxyPPS<4:0>
348
143
BRG<7:0>
SP1BRGH
TRISA
CREN
350
BRG<15:8>
350
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
124
TRISB7
TRISB6
TRISB5
TRISB4
130
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISA0
135
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
347
(1)
TRISC7
CSRC
(1)
TRISC6
TX9
= unimplemented location, read as 0. Shaded cells are not used for asynchronous reception.
Page provides register information.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
Unimplemented, read as 1.
Preliminary
DS40001715B-page 345
PIC16(L)F1704/8
29.2
DS40001715B-page 346
Preliminary
PIC16(L)F1704/8
29.3
REGISTER 29-1:
R/W-/0
R/W-0/0
CSRC
TX9
R/W-0/0
TXEN
(1)
R/W-0/0
R/W-0/0
R/W-0/0
R-1/1
R/W-0/0
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
Preliminary
DS40001715B-page 347
PIC16(L)F1704/8
REGISTER 29-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001715B-page 348
Preliminary
PIC16(L)F1704/8
REGISTER 29-3:
R-0/0
R-1/1
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
Preliminary
DS40001715B-page 349
PIC16(L)F1704/8
29.4
EXAMPLE 29-1:
CALCULATING BAUD
RATE ERROR
16000000
-----------------------9600
= ------------------------ 1
64
= 25.042 = 25
16000000
Calculated Baud Rate = --------------------------64 25 + 1
= 9615
Calc. Baud Rate Desired Baud Rate
Error = -------------------------------------------------------------------------------------------Desired Baud Rate
9615 9600
= ---------------------------------- = 0.16%
9600
DS40001715B-page 350
Preliminary
PIC16(L)F1704/8
TABLE 29-3:
Configuration Bits
BRG/EUSART Mode
8-bit/Asynchronous
FOSC/[64 (n+1)]
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
SYNC
BRG16
BRGH
1
Legend:
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
TABLE 29-4:
Name
BAUD1CON ABDOVF
RC1STA
SPEN
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
RCIDL
SCKP
BRG16
WUE
ABDEN
349
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
348
SP1BRGL
BRG<7:0>
350
SP1BRGH
BRG<15:8>
350
TX1STA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
347
Legend: = unimplemented location, read as 0. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
Preliminary
DS40001715B-page 351
PIC16(L)F1704/8
TABLE 29-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
1221
1.73
255
1200
0.00
239
1200
0.00
143
2400
2404
0.16
207
2404
0.16
129
2400
0.00
119
2400
0.00
71
9600
9615
0.16
51
9470
-1.36
32
9600
0.00
29
9600
0.00
17
10417
10417
0.00
47
10417
0.00
29
10286
-1.26
27
10165
-2.42
16
19.2k
19.23k
0.16
25
19.53k
1.73
15
19.20k
0.00
14
19.20k
0.00
57.6k
55.55k
-3.55
57.60k
0.00
57.60k
0.00
115.2k
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
300
0.16
207
300
0.00
191
300
0.16
51
1200
1202
0.16
103
1202
0.16
51
1200
0.00
47
1202
0.16
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
9600
9615
0.16
12
9600
0.00
10417
10417
0.00
11
10417
0.00
19.2k
19.20k
0.00
57.6k
57.60k
0.00
115.2k
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
2400
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
71
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.82k
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.64k
2.12
16
113.64k
-1.36
10
115.2k
0.00
115.2k
0.00
DS40001715B-page 352
Preliminary
PIC16(L)F1704/8
TABLE 29-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
1202
0.16
207
1200
0.00
191
300
1202
0.16
0.16
207
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
300.0
0.00
6666
300.0
-0.01
4166
300.0
0.00
3839
300.0
0.00
2303
1200
1200
-0.02
3332
1200
-0.03
1041
1200
0.00
959
1200
0.00
575
2400
2401
-0.04
832
2399
-0.03
520
2400
0.00
479
2400
0.00
287
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
71
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.818
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.6k
2.12
16
113.636
-1.36
10
115.2k
0.00
115.2k
0.00
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
299.9
-0.02
1666
300.1
0.04
832
300.0
0.00
767
300.5
0.16
207
1200
1199
-0.08
416
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19.23k
0.16
25
19.23k
0.16
12
19.20k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
Preliminary
DS40001715B-page 353
PIC16(L)F1704/8
TABLE 29-5:
BAUD
RATE
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
300.0
1200
0.00
0.00
26666
6666
300.0
1200
0.00
-0.01
16665
4166
300.0
1200
0.00
0.00
15359
3839
300.0
1200
0.00
0.00
9215
2303
2400
2400
0.01
3332
2400
0.02
2082
2400
0.00
1919
2400
0.00
1151
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
9600
9604
0.04
832
9597
-0.03
520
9600
0.00
479
9600
0.00
287
10417
10417
0.00
767
10417
0.00
479
10425
0.08
441
10433
0.16
264
19.2k
19.18k
-0.08
416
19.23k
0.16
259
19.20k
0.00
239
19.20k
0.00
143
57.6k
57.55k
-0.08
138
57.47k
-0.22
86
57.60k
0.00
79
57.60k
0.00
47
115.2k
115.9k
0.64
68
116.3k
0.94
42
115.2k
0.00
39
115.2k
0.00
23
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
300.0
0.00
6666
300.0
0.01
3332
300.0
0.00
3071
300.1
0.04
832
1200
1200
-0.02
1666
1200
0.04
832
1200
0.00
767
1202
0.16
207
2400
2401
0.04
832
2398
0.08
416
2400
0.00
383
2404
0.16
103
9600
9615
0.16
207
9615
0.16
103
9600
0.00
95
9615
0.16
25
10417
10417
191
10417
0.00
95
10473
0.53
87
10417
0.00
23
19.2k
19.23k
0.16
103
19.23k
0.16
51
19.20k
0.00
47
19.23k
0.16
12
57.6k
57.14k
-0.79
34
58.82k
2.12
16
57.60k
0.00
15
115.2k
117.6k
2.12
16
111.1k
-3.55
115.2k
0.00
DS40001715B-page 354
Preliminary
PIC16(L)F1704/8
29.4.1
AUTO-BAUD DETECT
TABLE 29-6:
FIGURE 29-6:
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
FOSC/64
FOSC/512
FOSC/16
FOSC/128
FOSC/16
FOSC/128
FOSC/4
FOSC/32
Note:
BRG Value
RX pin
0000h
001Ch
Start
Edge #1
bit 1
bit 0
Edge #2
bit 3
bit 2
Edge #3
bit 5
bit 4
Edge #4
bit 7
bit 6
Edge #5
Stop bit
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRGL
XXh
1Ch
SPBRGH
XXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
Preliminary
DS40001715B-page 355
PIC16(L)F1704/8
29.4.2
AUTO-BAUD OVERFLOW
29.4.3.1
29.4.3
AUTO-WAKE-UP ON BREAK
Special Considerations
Break Character
To avoid character errors or character fragments
during a wake-up event, the wake-up character must
be all zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all 0s. This must be ten or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
DS40001715B-page 356
Preliminary
PIC16(L)F1704/8
FIGURE 29-7:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Auto Cleared
WUE bit
RX/DT Line
RCIF
Note 1:
FIGURE 29-8:
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
Auto Cleared
Note 1
RCIF
Sleep Command Executed
Note 1:
2:
Sleep Ends
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
Preliminary
DS40001715B-page 357
PIC16(L)F1704/8
29.4.4
29.4.4.1
29.4.5
FIGURE 29-9:
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
DS40001715B-page 358
Preliminary
Auto Cleared
PIC16(L)F1704/8
29.5
29.5.1
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
29.5.1.3
29.5.1.4
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
1.
29.5.1.1
29.5.1.2
2.
3.
4.
5.
6.
Master Clock
7.
8.
Clock Polarity
Preliminary
DS40001715B-page 359
PIC16(L)F1704/8
FIGURE 29-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
Word 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
1
Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 29-11:
bit 0
bit 1
bit 2
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS40001715B-page 360
Preliminary
PIC16(L)F1704/8
TABLE 29-7:
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
125
ANSB5
ANSB4
131
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
136
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
349
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
90
RC1STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
348
RxyPPS
Name
Bit 7
Bit 6
ANSELA
ANSELB(1)
ANSELC
BAUD1CON
INTCON
RxyPPS<4:0>
SP1BRGL
BRG<7:0>
SP1BRGH
BRG<15:8>
TRISA
TRISB(1)
TRISC
Legend:
*
Note 1:
2:
3:
TRISA4
350
350
(3)
TRISA2
TRISA1
TRISA0
124
TRISB7
TRISB6
TRISB5
TRISB4
130
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISA0
135
TRMT
TX9D
TX1REG
TX1STA
TRISA5
143
CSRC
TX9
TXEN
SYNC
SENDB
339*
BRGH
347
= unimplemented location, read as 0. Shaded cells are not used for synchronous master transmission.
Page provides register information.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
Unimplemented, read as 1.
Preliminary
DS40001715B-page 361
PIC16(L)F1704/8
29.5.1.5
29.5.1.6
Slave Clock
29.5.1.7
29.5.1.8
29.5.1.9
1.
DS40001715B-page 362
Preliminary
PIC16(L)F1704/8
FIGURE 29-12:
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0
RCIF bit
(Interrupt)
Read
RCREG
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Note:
TABLE 29-8:
Name
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
125
ANSB5
ANSB4
131
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
136
SCKP
BRG16
WUE
ABDEN
349
Bit 7
Bit 6
ANSELA
ANSELB(1)
ANSELC
BAUD1CON
ABDOVF
RCIDL
CKPPS
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
90
RC1STA
SPEN
RX9
SREN
OERR
RX9D
RXPPS
RXPPS<4:0>
141, 142
RxyPPS
RxyPPS<4:0>
143
RC1REG
CKPPS<4:0>
141, 142
ADDEN
86
342*
FERR
348
SP1BRGL
BRG<7:0>
350*
SP1BRGH
BRG<15:8>
350*
TRISA
(1)
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
124
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
130
TRISC
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISA0
135
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
347
TX1STA
Legend:
*
Note 1:
2:
3:
= unimplemented location, read as 0. Shaded cells are not used for synchronous master reception.
Page provides register information.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
Unimplemented, read as 1.
Preliminary
DS40001715B-page 363
PIC16(L)F1704/8
29.5.2
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
1.
2.
3.
4.
29.5.2.1
5.
29.5.2.2
1.
2.
3.
4.
5.
6.
7.
8.
DS40001715B-page 364
Preliminary
PIC16(L)F1704/8
TABLE 29-9:
Name
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
125
ANSB5
ANSB4
131
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
136
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
Bit 7
Bit 6
ANSELA
ANSELB(1)
ANSELC
BAUD1CON
CKPPS
CKPPS<4:0>
349
141, 142
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
INTCON
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
90
RC1STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
348
RXPPS
RXPPS<4:0>
141, 142
RxyPPS
RxyPPS<4:0>
143
TRISA
TRISB(1)
TRISC
TRISA5
TRISA4
(3)
TRISA2
TRISA1
TRISA0
TRISB7
TRISB6
TRISB5
TRISB4
130
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISA0
135
TX1REG
TX1STA
Legend:
*
Note 1:
2:
3:
TX9
TXEN
SYNC
SENDB
124
339*
BRGH
TRMT
TX9D
347
= unimplemented location, read as 0. Shaded cells are not used for synchronous slave transmission.
Page provides register information.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
Unimplemented, read as 1.
Preliminary
DS40001715B-page 365
PIC16(L)F1704/8
29.5.2.3
29.5.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
ANSELA
(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
125
ANSELB
ANSB5
ANSB4
131
ANSELC
ANSC7(1)
ANSC6(1)
ANSC5(2)
ANSC4(2)
ANSC3
ANSC2
ANSC1
ANSC0
136
BAUD1CON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
349
CKPPS
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
86
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
87
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
RC1REG
CKPPS<4:0>
RC1STA
SPEN
RX9
SREN
RXPPS
TRISA
TRISA5
TRISB(1)
TRISC
TX1STA
Legend:
*
Note 1:
2:
3:
141, 142
CREN
ADDEN
FERR
OERR
RX9D
RXPPS<4:0>
TRISA4
(3)
90
342*
TRISA2
348
141, 142
TRISA1
TRISA0
124
TRISB7
TRISB6
TRISB5
TRISB4
130
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISA0
135
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
347
= unimplemented location, read as 0. Shaded cells are not used for synchronous slave reception.
Page provides register information.
PIC16(L)F1708 only.
PIC16(L)F1704 only.
Unimplemented, read as 1.
DS40001715B-page 366
Preliminary
PIC16(L)F1704/8
29.6
29.6.1
29.6.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
Preliminary
DS40001715B-page 367
PIC16(L)F1704/8
NOTES:
DS40001715B-page 368
Preliminary
PIC16(L)F1704/8
30.0
IN-CIRCUIT SERIAL
PROGRAMMING (ICSP)
30.3
FIGURE 30-1:
VDD
30.1
ICSPDAT
NC
2 4 6
ICSPCLK
1 3 5
Target
VSS
PC Board
Bottom Side
Pin Description*
1 = VPP/MCLR
VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
30.2
5 = ICSPCLK
6 = No Connect
Preliminary
DS40001715B-page 369
PIC16(L)F1704/8
FIGURE 30-2:
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
1
2
3
4
5
6
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
FIGURE 30-3:
Device to be
Programmed
VDD
VDD
VDD
VPP
MCLR/VPP
VSS
VSS
Data
ICSPDAT
Clock
ICSPCLK
To Normal Connections
DS40001715B-page 370
Preliminary
PIC16(L)F1704/8
31.0
31.1
Read-Modify-Write Operations
Byte Oriented
Bit Oriented
Literal and Control
TABLE 31-1:
Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The
opcodes are broken into three broad categories.
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
Register file address (0x00 to 0x7F)
mm
TABLE 31-2:
ABBREVIATION
DESCRIPTIONS
Field
Program Counter
TO
Time-Out bit
C
DC
Z
PD
Description
PC
Preliminary
Carry bit
Digit Carry bit
Zero bit
Power-Down bit
DS40001715B-page 371
PIC16(L)F1704/8
FIGURE 31-1:
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
General
13
OPCODE
0
k (literal)
OPCODE
k (literal)
0
k (literal)
5 4
0
k (literal)
0
k (literal)
6
n
0
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSR Increment instructions
13
OPCODE
2 1
0
n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
DS40001715B-page 372
Preliminary
PIC16(L)F1704/8
TABLE 31-3:
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DECFSZ
INCFSZ
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
1(2)
1(2)
00
00
1, 2
1, 2
1
1
01
01
2
2
1, 2
1, 2
BTFSC
BTFSS
f, b
f, b
1 (2)
1 (2)
01
01
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Note 1:
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
2:
Preliminary
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
DS40001715B-page 373
PIC16(L)F1704/8
TABLE 31-3:
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
k
k
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
ADDFSR
MOVIW
n, k
n mm
MOVWI
k[n]
n mm
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100 TO, PD
0000
0010
0001
0011 TO, PD
0fff
INHERENT OPERATIONS
1
1
1
1
1
1
C-COMPILER OPTIMIZED
k[n]
Note 1:
2:
3:
1
1
11
00
2, 3
1
1
11
00
2
2, 3
11
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
See Table in the MOVIW and MOVWI instruction descriptions.
DS40001715B-page 374
Preliminary
PIC16(L)F1704/8
31.2
Instruction Descriptions
ADDFSR
ANDLW
Syntax:
Syntax:
[ label ] ANDLW
Operands:
-32 k 31
n [ 0, 1]
Operands:
0 k 255
Operation:
FSR(n) + k FSR(n)
Status Affected:
None
Description:
Operation:
Status Affected:
Description:
ANDWF
AND W with f
ADDLW
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operation:
Status Affected:
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d 0,1
(W) + k (W)
Operation:
C, DC, Z
Status Affected:
Description:
Description:
ASRF
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
0 f 127
d 0,1
Operation:
Status Affected:
C, DC, Z
Description:
f,d
ADDWFC
Syntax:
[ label ] ADDWFC
Operands:
0 f 127
d [0,1]
Operation:
Syntax:
[ label ] ASRF
Operands:
0 f 127
d [0,1]
f {,d}
Operation:
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
C, Z
Description:
f {,d}
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data memory location f. If d is 0, the result is
placed in W. If d is 1, the result is
placed in data memory location f.
f,d
Preliminary
DS40001715B-page 375
PIC16(L)F1704/8
BCF
Bit Clear f
Syntax:
[ label ] BCF
BTFSC
f,b
Syntax:
Operands:
0 f 127
0b7
Operands:
Operation:
0 (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
BRA
Relative Branch
BTFSS
Syntax:
Syntax:
Operands:
0 f 127
0b<7
Operands:
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k PC
Status Affected:
None
Status Affected:
None
Description:
Description:
BRW
Syntax:
[ label ] BRW
Operands:
None
Operation:
(PC) + (W) PC
Status Affected:
None
Description:
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 127
0b7
Operation:
1 (f<b>)
Status Affected:
None
Description:
DS40001715B-page 376
f,b
Preliminary
PIC16(L)F1704/8
CALL
Call Subroutine
CLRWDT
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 k 2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<6:3>) PC<14:11>
Operation:
Status Affected:
None
00h WDT
0 WDT prescaler,
1 TO
1 PD
Description:
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
CALLW
COMF
Complement f
Syntax:
[ label ] CALLW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
(PC) +1 TOS,
(W) PC<7:0>,
(PCLATH<6:0>) PC<14:8>
0 f 127
d [0,1]
Operation:
(f) (destination)
Status Affected:
Description:
DECF
Decrement f
Syntax:
Status Affected:
None
Description:
CLRF
Clear f
Syntax:
[ label ] CLRF
f,d
Operands:
0 f 127
Operands:
Operation:
00h (f)
1Z
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Status Affected:
Description:
Description:
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h (W)
1Z
Status Affected:
Description:
Preliminary
DS40001715B-page 377
PIC16(L)F1704/8
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
GOTO k
INCFSZ f,d
IORLW k
Operands:
0 k 2047
Operands:
0 k 255
Operation:
k PC<10:0>
PCLATH<6:3> PC<14:11>
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
Status Affected:
Status Affected:
Description:
Description:
DS40001715B-page 378
INCF f,d
Preliminary
IORWF
f,d
PIC16(L)F1704/8
LSLF
MOVF
Syntax:
[ label ] LSLF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<7>) C
(f<6:0>) dest<7:1>
0 dest<0>
Operation:
(f) (dest)
f {,d}
Status Affected:
C, Z
Description:
register f
Description:
Words:
Cycles:
Syntax:
[ label ] LSRF
Operands:
0 f 127
d [0,1]
Operation:
0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
C, Z
Description:
MOVF
FSR, 0
After Instruction
W = value in FSR register
Z = 1
LSRF
f {,d}
register f
MOVF f,d
Status Affected:
Example:
Move f
Preliminary
DS40001715B-page 379
PIC16(L)F1704/8
MOVIW
Move INDFn to W
MOVLP
Syntax:
Syntax:
[ label ] MOVLP k
Operands:
0 k 127
Operation:
k PCLATH
Status Affected:
None
Operands:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
Description:
Operation:
INDFn W
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
Status Affected:
MOVLW
Move literal to W
Syntax:
[ label ]
0 k 255
Operation:
k (W)
Status Affected:
None
Description:
The 8-bit literal k is loaded into W register. The dont cares will assemble as
0s.
Words:
1
1
Mode
Syntax
mm
Cycles:
Preincrement
++FSRn
00
Example:
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
Syntax:
[ label ] MOVLB k
Operands:
0 k 31
Operation:
k BSR
Status Affected:
None
Description:
DS40001715B-page 380
0x5A
MOVWF
Move W to f
Syntax:
[ label ]
MOVWF
Operands:
0 f 127
Operation:
(W) (f)
0x5A
Status Affected:
None
Description:
Words:
Cycles:
Example:
MOVLW
After Instruction
W =
MOVLB
MOVLW k
Operands:
Predecrement
Preliminary
MOVWF
OPTION_REG
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
PIC16(L)F1704/8
MOVWI
Move W to INDFn
NOP
No Operation
Syntax:
Syntax:
[ label ]
Operands:
None
Operation:
No operation
Status Affected:
None
n [0,1]
mm [00,01, 10, 11]
-32 k 31
Description:
No operation.
Words:
Cycles:
Operands:
Operation:
Status Affected:
W INDFn
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
None
NOP
OPTION
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W) OPTION_REG
Status Affected:
None
Description:
Mode
Syntax
Preincrement
++FSRn
00
Predecrement
--FSRn
01
Postincrement
FSRn++
10
Words:
Postdecrement
FSRn--
11
Cycles:
Example:
OPTION
Description:
mm
Example:
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
None
Operation:
Status Affected:
None
Description:
NOP
Preliminary
DS40001715B-page 381
PIC16(L)F1704/8
RETFIE
RETURN
Syntax:
[ label ]
Syntax:
[ label ]
None
RETFIE k
RETURN
Operands:
None
Operands:
Operation:
TOS PC,
1 GIE
Operation:
TOS PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Words:
Cycles:
Example:
RETFIE
After Interrupt
PC =
GIE =
TOS
1
RETLW
Syntax:
[ label ]
Operands:
0 k 255
Operation:
k (W);
TOS PC
Status Affected:
None
Description:
Words:
Cycles:
Example:
TABLE
RETLW k
RLF
Syntax:
[ label ]
Operands:
0 f 127
d [ 0, 1]
Operation:
Status Affected:
Description:
RLF
C
CALL TABLE;W contains table
;offset value
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
Before Instruction
W =
After Instruction
W =
DS40001715B-page 382
Words:
Cycles:
Example:
RLF
f,d
Register f
REG1,0
Before Instruction
REG1
C
After Instruction
REG1
W
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0x07
value of k8
Preliminary
PIC16(L)F1704/8
SUBLW
Syntax:
[ label ]
RRF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
Status Affected:
C, DC, Z
Status Affected:
Description:
Description:
RRF f,d
SUBLW k
Operands:
0 k 255
Operation:
k - (W) W)
Register f
C=0
Wk
C=1
Wk
DC = 0
W<3:0> k<3:0>
DC = 1
W<3:0> k<3:0>
SLEEP
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
SLEEP
Operands:
None
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected:
TO, PD
Description:
SUBWF f,d
Operation:
Status Affected:
C, DC, Z
Description:
C=0
Wf
C=1
Wf
DC = 0
W<3:0> f<3:0>
DC = 1
W<3:0> f<3:0>
SUBWFB
Syntax:
SUBWFB
Operands:
0 f 127
d [0,1]
Operation:
f {,d}
Status Affected:
C, DC, Z
Description:
Preliminary
DS40001715B-page 383
PIC16(L)F1704/8
SWAPF
Swap Nibbles in f
XORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
SWAPF f,d
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected:
None
Description:
Operands:
0 k 255
Operation:
(W) .XOR. k W)
Status Affected:
Description:
XORWF
TRIS
XORLW k
Exclusive OR W with f
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
XORWF
f,d
Syntax:
[ label ] TRIS f
Operands:
5f7
Operation:
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
DS40001715B-page 384
Preliminary
PIC16(L)F1704/8
32.0
ELECTRICAL SPECIFICATIONS
32.1
2:
Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 32-6: Thermal
Characteristics to calculate device specifications.
Power dissipation is calculated as follows:
Pdis = VDD* {Idd- Ioh} + {VDD-Voh)*Ioh} + (Vol*IoI).
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
Preliminary
DS40001715B-page 385
PIC16(L)F1704/8
32.2
The standard operating conditions for any device are defined as:
Operating Voltage:
Operating Temperature:
DS40001715B-page 386
Preliminary
PIC16(L)F1704/8
VOLTAGE FREQUENCY GRAPH, -40C TA +125C, PIC16F1704/8 ONLY
FIGURE 32-1:
VDD (V)
5.5
2.5
2.3
0
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 32-7 for each Oscillator modes supported frequencies.
VDD (V)
FIGURE 32-2:
3.6
2.5
1.8
0
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 32-7 for each Oscillator modes supported frequencies.
Preliminary
DS40001715B-page 387
PIC16(L)F1704/8
32.3
DC Characteristics
TABLE 32-1:
SUPPLY VOLTAGE
PIC16LF1704/8
PIC16F1704/8
Param.
No.
D001
Sym.
VDD
Characteristic
PIC16F1704/8
VDR
VFVR
D004*
SVDD
*
Note
1:
2:
3:
4:
Conditions
VDDMIN
1.8
2.5
VDDMAX
3.6
3.6
V
V
FOSC 16 MHz
FOSC 32 MHz (Note 2)
2.3
2.5
5.5
5.5
V
V
FOSC 16 MHz:
FOSC 32 MHz (Note 2)
1.5
1.7
1.6
1.6
0.8
1.5
-4
+4
-5
+5
0.05
V/ms
D002B*
D003
Units
D002A*
D002B* VPORR*
Max.
D002*
D002A* VPOR
Typ
Supply Voltage
D001
D002*
Min.
(2)
DS40001715B-page 388
Preliminary
PIC16(L)F1704/8
FIGURE 32-3:
VDD
VPOR
VPORR
SVDD
VSS
NPOR(1)
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
TPOR(3)
Preliminary
DS40001715B-page 389
PIC16(L)F1704/8
TABLE 32-2:
PIC16LF1704/8
PIC16F1704/8
Param
No.
Device
Characteristics
LDO Regulator
D009
D010
D010
D012
D012
D014
D014
D015
D015
Note 1:
2:
3:
4:
5:
Conditions
Min.
Typ
Max.
Units
75
15
Sleep, VREGCON<1> = 0
0.3
Sleep, VREGCON<1> = 1
1.8
12
3.0
FOSC = 32 kHz,
LP Oscillator mode,
-40C TA +85C
15
2.3
17
3.0
21
5.0
140
1.8
250
3.0
210
2.3
280
3.0
340
5.0
115
1.8
210
3.0
180
2.3
240
3.0
VDD
300
5.0
2.1
mA
3.0
2.5
mA
3.6
2.1
mA
3.0
2.2
mA
5.0
Note
FOSC = 32 kHz,
LP Oscillator mode (Note 4),
-40C TA +85C
FOSC = 4 MHz,
XT Oscillator mode
FOSC = 4 MHz,
XT Oscillator mode
FOSC = 4 MHz,
External Clock (ECM),
Medium-Power mode
FOSC = 4 MHz,
External Clock (ECM),
Medium-Power mode
FOSC = 32 MHz,
External Clock (ECH),
High-Power mode (Note 5)
FOSC = 32 MHz,
External Clock (ECH),
High-Power mode (Note 5)
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
For EXTRC oscillator configurations, current through REXT is not included. The current through the resistor can be
extended by the formula IR = VDD/2REXT (mA) with REXT in k
FVR and BOR are disabled.
8 MHz clock with 4x PLL enabled.
DS40001715B-page 390
Preliminary
PIC16(L)F1704/8
TABLE 32-2:
PIC16LF1704/8
PIC16F1704/8
Param
No.
Device
Characteristics
D017
D017
Conditions
Min.
Typ
Max.
Units
130
1.8
150
3.0
150
2.3
170
3.0
VDD
220
5.0
D019
0.8
mA
1.8
1.2
mA
3.0
D019
1.0
mA
2.3
1.3
mA
3.0
1.4
mA
5.0
2.1
mA
3.0
2.5
mA
3.6
2.1
mA
3.0
2.2
mA
5.0
2.1
mA
3.0
2.5
mA
3.6
2.1
mA
3.0
2.2
mA
5.0
D020
D020
D022
D022
Note 1:
2:
3:
4:
5:
Note
FOSC = 16 MHz,
HFINTOSC mode
FOSC = 16 MHz,
HFINTOSC mode
FOSC = 32 MHz,
HFINTOSC mode (Note 5)
FOSC = 32 MHz,
HFINTOSC mode (Note 5)
FOSC = 32 MHz,
HS Oscillator mode (Note 5)
FOSC = 32 MHz
HS Oscillator mode (Note 5)
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
For EXTRC oscillator configurations, current through REXT is not included. The current through the resistor can be
extended by the formula IR = VDD/2REXT (mA) with REXT in k
FVR and BOR are disabled.
8 MHz clock with 4x PLL enabled.
Preliminary
DS40001715B-page 391
PIC16(L)F1704/8
0
TABLE 32-3:
PIC16LF1704/8
PIC16F1704/8
Param
No.
Device Characteristics
Min.
Typ
Max.
+85C
Max.
+125C
Units
Conditions
Note
VDD
D023
Base IPD
0.05
1.0
8.0
1.8
0.08
2.0
9.0
3.0
D023
Base IPD
0.3
11
2.3
0.4
12
3.0
0.5
15
5.0
9.8
16
18
2.3
10.3
18
20
3.0
11.5
21
26
5.0
D024
0.5
14
1.8
WDT Current
0.8
17
3.0
D024
0.8
15
2.3
0.9
20
3.0
1.0
22
5.0
15
28
30
1.8
18
30
33
3.0
18
33
35
2.3
19
35
37
3.0
D023A
Base IPD
D025
D025
WDT Current
FVR Current
FVR Current
20
37
39
5.0
D026
7.5
25
28
3.0
BOR Current
D026
10
25
28
3.0
BOR Current
12
28
31
5.0
D027
0.5
10
3.0
LPBOR Current
D027
0.8
14
3.0
LPBOR Current
17
5.0
0.5
1.8
0.8
8.5
12
3.0
1.1
10
2.3
1.3
8.5
20
3.0
D028
D028
D029
D029
Note 1:
2:
3:
1.4
10
25
5.0
0.05
1.8
0.08
10
3.0
0.3
12
2.3
0.4
13
3.0
0.5
16
5.0
SOSC Current
SOSC Current
DS40001715B-page 392
Preliminary
PIC16(L)F1704/8
TABLE 32-3:
PIC16LF1704/8
PIC16F1704/8
Param
No.
Device Characteristics
D030
D030
Conditions
Min.
Typ
Max.
+85C
Max.
+125C
Units
250
1.8
280
3.0
230
2.3
250
3.0
VDD
Note
350
5.0
D031
250
650
3.0
Op Amp (High-power)
D031
250
650
3.0
Op Amp (High-power)
350
650
5.0
250
600
1.8
300
650
3.0
280
600
2.3
300
650
3.0
310
650
5.0
D032
D032
Note 1:
2:
3:
Comparator,
CxSP = 0
Comparator,
CxSP = 0
VREGPM = 0
Preliminary
DS40001715B-page 393
PIC16(L)F1704/8
TABLE 32-4:
I/O PORTS
Sym.
VIL
Characteristic
Min.
Typ
Max.
Units
Conditions
I/O PORT:
D034
0.8
0.15 VDD
0.2 VDD
0.3 VDD
D034A
D035
0.8
D036
0.2 VDD
(Note 1)
D036A
0.3 VDD
VIH
I/O ports:
D040
2.0
0.25 VDD +
0.8
0.8 VDD
0.7 VDD
D040A
D041
MCLR
2.1
0.8 VDD
D043A
0.7 VDD
D043B
0.9 VDD
VDD 2.0V(Note 1)
125
nA
1000
nA
50
200
nA
25
100
200
25
140
300
0.6
VDD - 0.7
15
pF
50
pF
IIL
D060
I/O Ports
MCLR(3)
D061
IPUR
D070*
VOL
D080
I/O ports
VOH
D090
I/O ports
D101*
D101A* CIO
*
Note 1:
2:
3:
4:
DS40001715B-page 394
Preliminary
PIC16(L)F1704/8
TABLE 32-5:
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
Program Memory
Programming Specifications
D110
VIHH
8.0
9.0
D111
IDDP
10
mA
D112
VBE
2.7
VDDMAX
D113
VPEW
VDDMIN
VDDMAX
D114
1.0
mA
D115
5.0
mA
D121
EP
Cell Endurance
10K
E/W
D122
VPRW
VDDMIN
VDDMAX
D123
TIW
2.5
ms
D124
TRETD
Characteristic Retention
40
Year
Provided no other
specifications are violated
D125
EHEFC
100K
E/W
(Note 2)
-40C TA +85C
(Note 1)
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.
Preliminary
DS40001715B-page 395
PIC16(L)F1704/8
TABLE 32-6:
THERMAL CHARACTERISTICS
TH01
TH02
TH03
TH04
TH05
Sym.
Characteristic
Typ.
Units
JA
70.0
C/W
95.3
C/W
100.0
C/W
51.5
C/W
62.2
C/W
87.3
C/W
20-pin SSOP
77.7
C/W
JC
TJMAX
PD
Conditions
43.0
C/W
32.75
C/W
31.0
C/W
24.4
C/W
5.4
C/W
27.5
C/W
31.1
C/W
20-pin SSOP
23.1
C/W
5.3
C/W
150
PD = PINTERNAL + PI/O
TH06
PI/O
TH07
PDER
Derated Power
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature
DS40001715B-page 396
Preliminary
PIC16(L)F1704/8
32.4
AC Characteristics
Timing Parameter Symbology has been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O PORT
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
FIGURE 32-4:
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Preliminary
DS40001715B-page 397
PIC16(L)F1704/8
FIGURE 32-5:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
CLKIN
OS12
OS02
OS11
OS03
CLKOUT
(CLKOUT Mode)
Note
1:
TABLE 32-7:
OS01
Sym.
FOSC
Characteristic
Oscillator Frequency(1)
OS02
TOSC
Oscillator Period(1)
OS03
TCY
OS04*
TosH,
TosL
OS05*
TosR,
TosF
Min.
Typ
Max.
Units
Conditions
DC
0.5
MHz
DC
MHz
DC
20
MHz
32.768
kHz
LP Oscillator
0.1
MHz
XT Oscillator
MHz
HS Oscillator
20
MHz
DC
MHz
27
250
ns
XT Oscillator
50
ns
HS Oscillator
LP Oscillator
50
ns
30.5
LP Oscillator
250
10,000
ns
XT Oscillator
50
1,000
ns
HS Oscillator
250
ns
EXTRC
125
TCY
DC
ns
TCY = 4/FOSC
LP Oscillator
100
ns
XT Oscillator
20
ns
HS Oscillator
ns
LP Oscillator
ns
XT Oscillator
ns
HS Oscillator
DS40001715B-page 398
Preliminary
PIC16(L)F1704/8
TABLE 32-8:
OSCILLATOR PARAMETERS
Sym.
Characteristic
Freq.
Tolerance
Min.
Typ
Max.
Units
Conditions
OS08
HFOSC
2%
16.0
MHz
OS08A
MFOSC
2%
500
kHz
OS09
LFOSC
31
kHz
-40C TA +125C
OS10*
TIOSC ST
HFINTOSC
Wake-up from Sleep Start-up Time
MFINTOSC
Wake-up from Sleep Start-up Time
3.2
24
35
0.5
ms
OS10A* TLFOSC ST
*
LFINTOSC
Wake-up from Sleep Start-up Time
-40C TA +125C
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 32-6: HFINTOSC Frequency Accuracy Over Device VDD and Temperature,
Figure 33-22: HFINTOSC Accuracy Over Temperature, VDD = 1.8V, PIC16LF1704/8 Only, and
Figure 33-23: HFINTOSC Accuracy Over Temperature, 2.3V VDD 5.5V.
3: See Figure 33-20: LFINTOSC Frequency Over VDD and Temperature, PIC16LF1704/8 Only, and
Figure 33-21: LFINTOSC Frequency Over VDD and Temperature, PIC16F1704/8 Only.
FIGURE 32-6:
125
5%
85
Temperature (C)
3%
60
2%
25
0
-20
-40
1.8
5%
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
Preliminary
DS40001715B-page 399
PIC16(L)F1704/8
TABLE 32-9:
Sym.
F10
Characteristic
Min.
Typ
Max.
Units
MHz
F11
FSYS
16
32
MHz
F12
TRC
F13*
CLK
ms
-0.25%
+0.25%
Conditions
DS40001715B-page 400
Preliminary
PIC16(L)F1704/8
FIGURE 32-7:
Cycle
Fetch
Q1
Q4
Read
Execute
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS18
OS16
OS13
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
OS11
TosH2ckL
70
ns
OS12
TosH2ckH
72
ns
ns
(1)
OS13
TckL2ioV
OS14
TioV2ckH
OS15
TosH2ioV
OS16
20
TOSC + 200 ns
ns
50
70*
ns
TosH2ioI
50
ns
OS17
TioV2osH
20
ns
OS18*
TioR
40
15
72
32
ns
VDD = 1.8V
3.3V VDD 5.0V
OS19*
TioF
28
15
55
30
ns
VDD = 1.8V
3.3V VDD 5.0V
OS20*
Tinp
25
ns
OS21*
Tioc
25
ns
Preliminary
DS40001715B-page 401
PIC16(L)F1704/8
FIGURE 32-8:
VDD
MCLR
30
Internal
POR
PWRT
Time-out
33
32
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
34
31
34
I/O pins
Note 1: Asserted low.
DS40001715B-page 402
Preliminary
PIC16(L)F1704/8
TABLE 32-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
Min.
Typ
Max.
Units
10
16
27
ms
Conditions
30
TMCL
31
32
TOST
1024
Tosc
33*
TPWRT
40
65
140
ms
34*
TIOZ
2.0
35
VBOR
2.55
2.70
2.85
BORV = 0
2.30
1.80
2.45
1.90
2.60
2.10
V
V
BORV = 1 (PIC16F1704/8)
BORV = 1 (PIC16LF1704/8)
1.8
2.1
2.5
LPBOR = 1
25
75
mV
-40C TA +85C
35
VDD VBOR
35A
36*
VHYST
37*
VDD = 3.3V-5V
1:16 Prescaler used
Preliminary
DS40001715B-page 403
PIC16(L)F1704/8
FIGURE 32-9:
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
FIGURE 32-10:
VDD
VBOR and VHYST
VBOR
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to 0.
2 ms delay if PWRTE = 0.
DS40001715B-page 404
Preliminary
PIC16(L)F1704/8
TABLE 32-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40C TA +125C
Param
No.
40*
Sym.
TT0H
Characteristic
Min.
No Prescaler
TT0L
No Prescaler
TT0P
T0CKI Period
45*
TT1H
ns
ns
0.5 TCY + 20
ns
10
ns
Greater of:
20 or TCY + 40
N
ns
0.5 TCY + 20
ns
15
ns
Asynchronous
46*
TT1L
T1CKI Low
Time
30
ns
Synchronous, No Prescaler
0.5 TCY + 20
ns
15
ns
Asynchronous
30
ns
Greater of:
30 or TCY + 40
N
ns
47*
TT1P
48
FT1
49*
Asynchronous
Units
10
With Prescaler
42*
Max.
0.5 TCY + 20
With Prescaler
41*
Typ
60
ns
32.4
32.768
33.1
kHz
2 TOSC
7 TOSC
Conditions
N = prescale value
N = prescale value
Timers in Sync
mode
Preliminary
DS40001715B-page 405
PIC16(L)F1704/8
FIGURE 32-11:
CCPx
(Capture mode)
CC01
CC02
CC03
Note:
Characteristic
CC01* TccL
No Prescaler
CC02* TccH
No Prescaler
With Prescaler
With Prescaler
CC03* TccP
*
Min.
Typ
Max.
Units
0.5TCY + 20
ns
ns
20
0.5TCY + 20
ns
20
ns
3TCY + 40
N
ns
Conditions
N = prescale value
DS40001715B-page 406
Preliminary
PIC16(L)F1704/8
FIGURE 32-12:
CLCxINn
CLC
Input time
CLCxINn
CLC
Input time
LCx_in[n](1)
LCx_in[n](1)
CLC
Module
LCx_out(1)
CLC
Output time
CLCx
CLC
Module
LCx_out(1)
CLC
Output time
CLCx
CLC01
Note 1:
CLC02
CLC03
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
CLC01* TCLCIN
OS17
ns
(Note 1)
CLC02* TCLC
24
12
ns
ns
VDD = 1.8V
VDD > 3.6V
OS18
(Note 1)
OS19
(Note 1)
45
MHz
Rise Time
Fall Time
Preliminary
DS40001715B-page 407
PIC16(L)F1704/8
TABLE 32-15:
Characteristic
Min.
Typ
Max.
Units
Conditions
AD01
NR
Resolution
10
AD02
EIL
Integral Error
1.7
AD03
EDL
Differential Error
AD04
2.5
AD05
EGN
Gain Error
2.0
AD06
1.8
VDD
VSS
VREF
10
AD07
VAIN
Full-Scale Range
AD08
ZAIN
Recommended Impedance of
Analog Voltage Source
Note 1:
2:
3:
4:
bit
LSb VREF = 3.0V
LSb No missing codes, VREF = 3.0V
AD130* TAD
AD131 TCNV
Characteristic
Min.
Typ
Max.
Units
Conditions
1.0
9.0
FOSC-based
1.0
2.5
6.0
13
TAD
5.0
1/2 TAD
DS40001715B-page 408
Preliminary
PIC16(L)F1704/8
FIGURE 32-13:
BSF ADCON0, GO
AD133
1 TCY
AD131
Q4
AD130
ADC_clk
9
ADC Data
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
Sample
DONE
Sampling Stopped
AD132
FIGURE 32-14:
BSF ADCON0, GO
AD133
1 TCY
AD131
Q4
AD130
ADC_clk
9
ADC Data
OLD_DATA
ADRES
0
NEW_DATA
1 TCY
ADIF
GO
Sample
DONE
AD132
Sampling Stopped
Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the
SLEEP instruction to be executed.
Preliminary
DS40001715B-page 409
PIC16(L)F1704/8
TABLE 32-17: OPERATIONAL AMPLIFIER (OPA)
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25C, OPAxSP = 1 (High GBWP mode)
Param
No.
Symbol
OPA01*
GBWP
Parameters
Min.
Typ.
Max.
Units
MHz
OPA02*
TON
Turn on Time
10
OPA03*
PM
Phase Margin
40
degrees
OPA04*
SR
Slew Rate
V/s
OPA05
OFF
Offset
mV
OPA06
CMRR
52
70
dB
OPA07*
AOL
90
dB
OPA08
VICM
VDD
OPA09*
PSRR
80
dB
Conditions
Sym.
Characteristics
Min.
Typ.
Max.
Units
Comments
CM01
VIOFF
2.5
mV
CM02
VICM
VDD
CM03
CMRR
40
50
dB
60
85
ns
CxSP = 1
CM04A
CM04B
CM04C
TRESP(1)
CM04D
CxSP = 1,
VICM = VDD/2
60
90
ns
CxSP = 1
85
ns
CxSP = 0
85
ns
CxSP = 0
10
20
45
75
mV
CM05*
TMC2OV
CM06
*
Note 1:
DS40001715B-page 410
Preliminary
CxHYS = 1,
CxSP = 1
PIC16(L)F1704/8
TABLE 32-19: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25C
See Section 33.0 DC and AC Characteristics Graphs and Charts for operating characterization.
Param
No.
Sym.
Characteristics
Min.
Typ.
Max.
Units
VDD/256
DAC01*
CLSB
Step Size
DAC02*
CACC
Absolute Accuracy
1.5
LSb
DAC03*
CR
600
10
DAC04*
*
Note 1:
CST
Settling Time
(1)
Comments
Sym.
Characteristics
Min.
Typ.
Max.
Units
ZC01
ZCPINV
ZC02
ZCSRC
Source current
300
ZC03
ZCSNK
Sink current
300
ZC04
ZCISW
ZC05
ZCOUT
Comments
Preliminary
DS40001715B-page 411
PIC16(L)F1704/8
FIGURE 32-15:
CK
US121
US121
DT
US122
US120
Note:
Symbol
US120
TCKH2DTV
US121
US122
Characteristic
TCKRF
TDTRF
FIGURE 32-16:
Min.
Max.
Units
Conditions
80
ns
100
ns
45
ns
50
ns
45
ns
50
ns
US125
DT
US126
Note: Refer to Figure 32-4 for load conditions.
Symbol
Characteristic
DS40001715B-page 412
Preliminary
Min.
Max.
Units
10
ns
15
ns
Conditions
PIC16(L)F1704/8
FIGURE 32-17:
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
bit 6 - - - - - -1
MSb
SDO
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 32-4 for load conditions.
FIGURE 32-18:
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SDO
MSb
SP78
bit 6 - - - - - -1
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 32-4 for load conditions.
Preliminary
DS40001715B-page 413
PIC16(L)F1704/8
FIGURE 32-19:
SS
SP70
SCK
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
MSb
SDO
LSb
bit 6 - - - - - -1
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 32-4 for load conditions.
FIGURE 32-20:
SS
SCK
(CKP = 0)
SP71
SP72
SCK
(CKP = 1)
SP80
SDO
MSb
bit 6 - - - - - -1
LSb
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 32-4 for load conditions.
DS40001715B-page 414
Preliminary
PIC16(L)F1704/8
TABLE 32-23: SPI MODE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min.
Typ
Max. Units
TCY
ns
SP70* TSSL2SCH,
TSSL2SCL
SP71* TSCH
TCY + 20
ns
TCY + 20
ns
SP72*
TSCL
Conditions
SP73* TDIV2SCH,
TDIV2SCL
100
ns
SP74* TSCH2DIL,
TSCL2DIL
100
ns
SP75* TDOR
10
25
ns
25
50
ns
SP76* TDOF
10
25
ns
SP77* TSSH2DOZ
10
50
ns
SP78* TSCR
10
25
ns
25
50
ns
SP79* TSCF
10
25
ns
SP80* TSCH2DOV,
TSCL2DOV
50
ns
SP83* TSCH2SSH,
TSCL2SSH
145
ns
1 Tcy
ns
50
ns
1.5 TCY + 40
ns
Preliminary
DS40001715B-page 415
PIC16(L)F1704/8
I2C BUS START/STOP BITS TIMING
FIGURE 32-21:
SCL
SP93
SP91
SP90
SP92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 32-4 for load conditions.
Symbol
Characteristic
SP90*
TSU:STA
Start condition
SP91*
THD:STA
SP92*
TSU:STO
SP93
Typ
4700
Max. Units
Setup time
600
Start condition
4000
Hold time
600
Stop condition
4700
Setup time
Hold time
*
Min.
600
4000
600
Conditions
ns
ns
ns
ns
FIGURE 32-22:
SCL
SP100
SP90
SP102
SP101
SP106
SP107
SP91
SDA
In
SP92
SP110
SP109
SP109
SDA
Out
Note: Refer to Figure 32-4 for load conditions.
DS40001715B-page 416
Preliminary
PIC16(L)F1704/8
TABLE 32-25: I2C BUS DATA REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
SP100* THIGH
Characteristic
Clock high time
Min.
Max.
Units
4.0
0.6
1.5TCY
4.7
1.3
1.5TCY
SSP module
SP101*
TLOW
SSP module
SP102* TR
SP103* TF
1000
ns
20 + 0.1CB
300
ns
250
ns
20 + 0.1CB
250
ns
ns
SP106* THD:DAT
0.9
SP107* TSU:DAT
250
ns
100
ns
SP109* TAA
3500
ns
ns
SP110*
4.7
1.3
400
pF
SP111
*
Note 1:
2:
TBUF
CB
Conditions
CB is specified to be from
10-400 pF
CB is specified to be from
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
Preliminary
DS40001715B-page 417
PIC16(L)F1704/8
NOTES:
DS40001715B-page 418
Preliminary
PIC16(L)F1704/8
33.0
DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Unless otherwise noted, all graphs apply to both the L and LF devices.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Typical represents the mean of the distribution at 25C. MAXIMUM, Max., MINIMUM or Min.
represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each
temperature range.
Preliminary
DS40001715B-page 419
PIC16(L)F1704/8
FIGURE 33-1:
6
Max: 125C + 3
Typical: 25C
Min: -40C - 3
VOH (V)
4
Min. (-40C)
3
Typical (25C)
2
Max. (125C)
1
0
-45
-40
-35
-30
-25
-20
-15
-10
-5
IOH (mA)
FIGURE 33-2:
5
Max: 125C + 3
Typical: 25C
Min: -40C - 3
Max. (125C)
VOL (V)
Typical (25C)
3
Min. (-40C)
0
0
10
DS40001715B-page 420
20
30
40
50
IOL (mA)
Preliminary
60
70
80
90
100
PIC16(L)F1704/8
FIGURE 33-3:
3.5
Max: 125C + 3
Typical: 25C
Min: -40C - 3
3.0
VOH (V)
2.5
2.0
1.5
1.0
Min. (-40C)
Typical (25C)
Max. (125C)
0.5
0.0
-15
-13
-11
-9
-7
-5
-3
-1
IOH (mA)
FIGURE 33-4:
5
Max: 125C + 3
Typical: 25C
Min: -40C - 3
Max. (125C)
VOL (V)
Typical (25C)
3
Min. (-40C)
0
0
10
20
30
40
50
IOL (mA)
Preliminary
60
70
80
90
100
DS40001715B-page 421
PIC16(L)F1704/8
FIGURE 33-5:
2.0
1.8
Max: 125C + 3
Typical: 25C
Min: -40C - 3
1.6
VOH (V)
1.4
1.2
Min. (-40C)
Max. (125C)
Typical (25C)
1.0
0.8
0.6
0.4
0.2
0.0
-4.5
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
IOH (mA)
FIGURE 33-6:
1.8
Max: 125C + 3
Typical: 25C
Min: -40C - 3
1.6
1.4
VOL (V)
1.2
1.0
0.8
Max. (125C)
Min. (-40C)
Typical (25C)
0.6
0.4
0.2
0.0
0
10
IOL (mA)
DS40001715B-page 422
Preliminary
PIC16(L)F1704/8
FIGURE 33-7:
1.70
1.68
Max.
1.66
Voltage (V)
1.64
Typical
1.62
Min.
1.60
1.58
1.56
Max: Typical + 3
Typical: 25C
Min: Typical - 3
1.54
1.52
1.50
-60
-40
-20
20
40
60
80
100
120
140
120
140
Temperature (C)
FIGURE 33-8:
1.54
Max: Typical + 3
Typical: 25C
Min: Typical - 3
1.52
1.50
Max.
Voltage (V)
1.48
1.46
1.44
Typical
1.42
1.40
Min.
1.38
1.36
1.34
-60
-40
-20
20
40
60
80
100
Temperature (C)
Preliminary
DS40001715B-page 423
PIC16(L)F1704/8
FIGURE 33-9:
2.00
Max.
Voltage (V)
1.95
Typical
1.90
1.85
Min.
Max: Typical + 3
Min: Typical - 3
1.80
-60
-40
-20
20
40
60
80
100
120
140
Temperature (C)
FIGURE 33-10:
60
50
Max.
Max: Typical + 3
Typical: 25C
Min: Typical - 3
Voltage (mV)
40
Typical
30
20
Min.
10
0
-60
-40
-20
20
40
60
80
100
120
140
Temperature (C)
DS40001715B-page 424
Preliminary
PIC16(L)F1704/8
FIGURE 33-11:
2.60
Max.
2.55
Voltage (V)
2.50
Typical
2.45
Min.
2.40
Max: Typical + 3
Min: Typical - 3
2.35
2.30
-60
-40
-20
20
40
60
80
100
120
140
Temperature (C)
FIGURE 33-12:
70
Max.
60
Max: Typical + 3
Typical: 25C
Min: Typical - 3
Voltage (mV)
50
40
Typical
30
20
Min.
10
0
-60
-40
-20
20
40
60
80
100
120
140
Temperature (C)
Preliminary
DS40001715B-page 425
PIC16(L)F1704/8
FIGURE 33-13:
2.80
2.75
Voltage (V)
Max.
2.70
Typical
2.65
Min.
Max: Typical + 3
Min: Typical - 3
2.60
2.55
-60
-40
-20
20
40
60
80
100
120
140
120
140
Temperature (C)
FIGURE 33-14:
90
80
Min.
70
Voltage (mV)
60
Typical
50
40
Max: Typical + 3
Typical: 25C
Min: Typical - 3
30
20
Max.
10
0
-60
-40
-20
20
40
60
80
100
Temperature (C)
DS40001715B-page 426
Preliminary
PIC16(L)F1704/8
FIGURE 33-15:
2.50
Max.
Max: Typical + 3
Min: Typical - 3
2.40
Voltage (V)
2.30
Typical
2.20
2.10
2.00
Min.
1.90
1.80
-60
-40
-20
20
40
60
80
100
120
140
120
140
Temperature (C)
FIGURE 33-16:
45
Max: Typical + 3
Typical: 25C
Min: Typical - 3
40
35
Max.
Typical
Voltage (mV)
30
25
Min.
20
15
10
5
0
-60
-40
-20
20
40
60
80
100
Temperature (C)
Preliminary
DS40001715B-page 427
PIC16(L)F1704/8
FIGURE 33-17:
24
22
Max.
Time (ms)
20
18
Typical
16
Min.
14
Max: Typical + 3 (-40C to +125C)
Typical: statistical mean @ 25C
Min: Typical - 3 (-40C to +125C)
12
10
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-18:
PWRT PERIOD
100
Max: Typical + 3 (-40C to +125C)
Typical: statistical mean @ 25C
Min: Typical - 3 (-40C to +125C)
90
Max.
Time (ms)
80
70
Typical
60
Min.
50
40
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001715B-page 428
Preliminary
PIC16(L)F1704/8
FIGURE 33-19:
60
Max: Typical + 3
Typical: statistical mean @ 25C
50
Max.
Time (us)
40
Typical
30
20
Note:
The FVR Stabilization Period applies when:
1) coming out of Reset or exiting Sleep mode for PIC12/16LFxxxx devices.
2) when exiting Sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices
In all other cases, the FVR is stable when released from Reset.
10
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
Preliminary
DS40001715B-page 429
PIC16(L)F1704/8
FIGURE 33-20:
36
34
Max.
Frequency (kHz)
32
30
Typical
28
Min.
26
24
Max: Typical + 3 (-40C to +125C)
Typical: statistical mean @ 25C
Min: Typical - 3 (-40C to +125C)
22
20
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 33-21:
36
34
Max.
Frequency (kHz)
32
30
Typical
28
26
Min.
24
Max: Typical + 3 (-40C to +125C)
Typical: statistical mean @ 25C
Min: Typical - 3 (-40C to +125C)
22
20
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001715B-page 430
Preliminary
PIC16(L)F1704/8
FIGURE 33-22:
8%
6%
Max: Typical + 3
Typical: statistical mean
Min: Typical - 3
Accuracy (%)
4%
Max.
2%
0%
Typical
-2%
-4%
Min.
-6%
-8%
-10%
-60
-40
-20
20
40
60
80
100
120
140
Temperature (C)
FIGURE 33-23:
8%
6%
Max: Typical + 3
Typical: statistical mean
Min: Typical - 3
Accuracy (%)
4%
Max.
2%
Typical
0%
-2%
Min.
-4%
-6%
-8%
-10%
-60
-40
-20
20
40
60
80
100
120
140
Temperature (C)
Preliminary
DS40001715B-page 431
PIC16(L)F1704/8
FIGURE 33-24:
5.0
4.5
Max.
4.0
Time (us)
3.5
Typical
3.0
2.5
2.0
1.5
Max: 85C + 3
Typical: 25C
1.0
0.5
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
DS40001715B-page 432
Preliminary
PIC16(L)F1704/8
FIGURE 33-25:
35
Max.
30
Typical
Time (us)
25
20
15
10
Max: 85C + 3
Typical: 25C
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 33-26:
12
Max.
10
Time (us)
8
Typical
6
4
Max: 85C + 3
Typical: 25C
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
Preliminary
DS40001715B-page 433
PIC16(L)F1704/8
NOTES:
DS40001715B-page 434
Preliminary
PIC16(L)F1704/8
34.0
DEVELOPMENT SUPPORT
34.1
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
Preliminary
DS40001715B-page 435
PIC16(L)F1704/8
34.2
MPLAB XC Compilers
34.4
34.3
MPASM Assembler
34.5
DS40001715B-page 436
Preliminary
PIC16(L)F1704/8
34.6
34.7
34.8
34.9
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineers PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming (ICSP).
Preliminary
DS40001715B-page 437
PIC16(L)F1704/8
34.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
DS40001715B-page 438
Preliminary
PIC16(L)F1704/8
35.0
PACKAGING INFORMATION
35.1
Example
PIC16F1704
-I/P e3
1304017
28-Lead SOIC (7.50 mm)
Example
Example
PIC16F1704
-I/SO e3
1304017
Example
16F1704
1304
017
XXXXXXXX
YYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Preliminary
DS40001715B-page 439
PIC16(L)F1704/8
Package Marking Information (Continued)
16-Lead QFN (4x4x0.9 mm)
Example
PIN 1
PIN 1
PIC16
F1704
-I/MV
130417
e3
Example
PIC16F1708
-E/ML e3
130417
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F1708
-E/PT e3
130417
Example
PIC16F1708
-E/PT e3
130417
DS40001715B-page 440
Preliminary
PIC16(L)F1704/8
Package Marking Information (Continued)
Example
PIN 1
PIN 1
PIC16
F1708
-I/MV
130417
e3
Preliminary
DS40001715B-page 441
PIC16(L)F1704/8
35.2
Package Details
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DS40001715B-page 442
Preliminary
PIC16(L)F1704/8
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Preliminary
DS40001715B-page 443
PIC16(L)F1704/8
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001715B-page 444
Preliminary
PIC16(L)F1704/8
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DS40001715B-page 445
PIC16(L)F1704/8
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001715B-page 446
Preliminary
PIC16(L)F1704/8
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Preliminary
DS40001715B-page 447
PIC16(L)F1704/8
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DS40001715B-page 448
Preliminary
PIC16(L)F1704/8
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Preliminary
DS40001715B-page 449
PIC16(L)F1704/8
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DS40001715B-page 450
Preliminary
PIC16(L)F1704/8
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Preliminary
DS40001715B-page 451
PIC16(L)F1704/8
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001715B-page 452
Preliminary
PIC16(L)F1704/8
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Preliminary
DS40001715B-page 453
PIC16(L)F1704/8
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001715B-page 454
Preliminary
PIC16(L)F1704/8
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Preliminary
DS40001715B-page 455
PIC16(L)F1704/8
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Preliminary
PIC16(L)F1704/8
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DS40001715B-page 457
PIC16(L)F1704/8
NOTES:
DS40001715B-page 458
Preliminary
PIC16(L)F1704/8
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A (07/2013)
Initial release.
Revision B (09/2013)
Moved Note 1 from Table 3-10 to Table 3-9; Register
4-2, Removed overbar from bit 7; Table 8-1, removed
IOCBF, IOCBN, IOCBP; Register 12-3, revised bit 4-0;
Revised Table 32-1, Param. D003; Revised Table 32-2,
added Note 5 to D015, revised Note 5; Revised Table
32-7, OS03 Min.; Revised Table 32-17, OPA06, Min.;
Revised Register 21-1, bit 6 description.
Preliminary
DS40001715B-page 459
PIC16(L)F1704/8
NOTES:
DS40001715B-page 460
Preliminary
PIC16(L)F1704/8
INDEX
Numerics
8-Bit Digital-to-Analog Converter (DAC1) ......................... 241
8-bit Digital-to-Analog Converter (DAC1)
Effects of a Reset...................................................... 242
A
A/D
Analog-to-Digital Converter....................................... 269
Absolute Maximum Ratings .............................................. 385
AC Characteristics
Load Conditions ........................................................ 397
ACKSTAT ......................................................................... 317
ACKSTAT Status Flag ...................................................... 317
ADC .................................................................................. 223
Acquisition Requirements ......................................... 234
Associated registers.................................................. 236
Block Diagram........................................................... 223
Calculating Acquisition Time..................................... 234
Channel Selection..................................................... 224
Configuration............................................................. 224
Configuring Interrupt ................................................. 228
Conversion Clock...................................................... 224
Conversion Procedure .............................................. 228
Internal Sampling Switch (RSS) Impedance.............. 234
Interrupts................................................................... 226
Operation .................................................................. 227
Operation During Sleep ............................................ 227
Port Configuration ..................................................... 224
Reference Voltage (VREF)......................................... 224
Source Impedance.................................................... 234
Special Event Trigger................................................ 227
Specifications.................................................... 407, 408
Starting an ADC Conversion..................................... 226
ADCON0 Register....................................................... 32, 229
ADCON1 Register....................................................... 32, 230
ADCON2 Register............................................................. 231
ADDFSR ........................................................................... 375
ADDWFC .......................................................................... 375
ADRESH Register............................................................... 32
ADRESH Register (ADFM = 0) ......................................... 232
ADRESH Register (ADFM = 1) ......................................... 233
ADRESL Register ............................................................... 32
ADRESL Register (ADFM = 0).......................................... 232
ADRESL Register (ADFM = 1).......................................... 233
Analog-to-Digital Converter. See ADC
Assembler
MPASM Assembler................................................... 436
B
Bank 0 ................................................................................. 32
Bank 1 ................................................................................. 32
Bank 10 ............................................................................... 35
Bank 11 ............................................................................... 36
Bank 12 ............................................................................... 36
Bank 13 ............................................................................... 36
Bank 14-27.......................................................................... 36
Bank 2 ................................................................................. 33
Bank 28 ............................................................................... 37
Bank 29 ............................................................................... 38
Bank 3 ................................................................................. 33
Bank 30 ............................................................................... 39
Bank 4 ................................................................................. 34
Bank 5 ................................................................................. 34
Bank 6 ................................................................................ 34
Bank 7 ................................................................................ 35
Bank 8 ................................................................................ 35
Bank 9 ................................................................................ 35
BAUD1CON Register ....................................................... 349
BF ............................................................................. 317, 319
BF Status Flag .......................................................... 317, 319
Block Diagrams
(CCP) Capture Mode Operation ............................... 272
ADC .......................................................................... 223
ADC Transfer Function............................................. 235
Analog Input Model................................................... 235
CCP PWM ................................................................ 276
Compare................................................................... 274
Digital-to-Analog Converter (DAC1) ......................... 242
EUSART Receive ..................................................... 338
EUSART Transmit .................................................... 337
OPA Module ............................................................. 237
Timer0 ...................................................................... 249
Timer1 ...................................................................... 253
Timer1 Gate.............................................. 258, 259, 260
Timer2 ...................................................................... 265
Voltage Reference Output Buffer Example .............. 242
Zero Cross Detection (ZCD)..................................... 245
BRA .................................................................................. 376
Break Character (12-bit) Transmit and Receive ............... 358
Brown-out Reset (BOR)
Specifications ........................................................... 403
Timing and Characteristics ....................................... 404
C
C Compilers
MPLAB C18.............................................................. 436
CALL................................................................................. 377
CALLW ............................................................................. 377
Capture Module. See Capture/Compare/PWM(CCP)
Capture/Compare/PWM ................................................... 271
Capture/Compare/PWM (CCP) ........................................ 272
Associated Registers w/ PWM ................................. 279
Capture Mode........................................................... 272
CCPx Pin Configuration............................................ 272
Compare Mode......................................................... 274
CCPx Pin Configuration.................................... 274
Software Interrupt Mode ........................... 272, 274
Special Event Trigger ....................................... 274
Timer1 Mode Resource ............................ 272, 274
Prescaler .................................................................. 272
PWM Mode
Duty Cycle ........................................................ 277
Effects of Reset ................................................ 279
Example PWM Frequencies and
Resolutions, 20 MHZ................................ 278
Example PWM Frequencies and
Resolutions, 8 MHz .................................. 278
Operation in Sleep Mode.................................. 279
Resolution ........................................................ 278
System Clock Frequency Changes .................. 279
PWM Operation ........................................................ 276
PWM Overview......................................................... 276
PWM Period ............................................................. 277
PWM Setup .............................................................. 277
Specifications ........................................................... 406
CCP. See Capture/Compare/PWM
CCPTMRS Register.......................................................... 269
Preliminary
DS40001715B-page 461
PIC16(L)F1704/8
CCPTMRS0 Register ........................................................ 269
CCPxCON (CCPx) Register.............................................. 280
CLCDATA Register ........................................................... 220
CLCxCON Register........................................................... 213
CLCxGLS0 Register.......................................................... 216
CLCxGLS1 Register.......................................................... 217
CLCxGLS2 Register.......................................................... 218
CLCxGLS3 Register.......................................................... 219
CLCxPOL Register............................................................ 214
CLCxSEL0 Register .......................................................... 215
CLCxSEL1 Register .......................................................... 215
CLCxSEL2 Register .......................................................... 215
CLCxSEL3 Register .......................................................... 215
Clock Accuracy with Asynchronous Operation ................. 346
Code Examples
ADC Conversion ....................................................... 228
Changing Between Capture Prescalers .................... 272
Comparator Specifications ........................................ 410, 411
Comparators
C2OUT as T1 Gate ................................................... 255
Compare Module. See Capture/Compare/PWM (CCP)
Configuration as OPAMP or Comparator.......................... 238
Core Function Register ....................................................... 31
Customer Change Notification Service ............................. 467
Customer Notification Service........................................... 467
Customer Support ............................................................. 467
D
DAC1CON0 (DAC1 Converter Control 0) Register........... 244
DAC1CON1 (DAC1 Converter Control 1) Register........... 244
Data Memory....................................................................... 22
DC and AC Characteristics ............................................... 419
Graphs and Tables ................................................... 419
DC Characteristics
Extended and Industrial ............................................ 394
Industrial and Extended ............................................ 388
Development Support ....................................................... 435
Digital-to-Analog Converter (DAC)
Specifications ............................................................ 411
Digital-to-Analog Converter (DAC1)
Associated Registers ................................................ 244
E
Effects of Reset
PWM mode ............................................................... 279
Electrical Specifications .................................................... 385
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)............................... 337
EUSART............................................................................ 337
Associated Registers
Baud Rate Generator........................................ 351
Asynchronous Mode ................................................. 339
12-bit Break Transmit and Receive................... 358
Associated Registers
Receive ..................................................... 345
Transmit .................................................... 341
Auto-Wake-up on Break.................................... 356
Baud Rate Generator (BRG)............................. 350
Clock Accuracy ................................................. 346
Receiver............................................................ 342
Setting up 9-bit Mode with Address Detect....... 344
Transmitter........................................................ 339
Baud Rate Generator (BRG)
Auto Baud Rate Detect ..................................... 355
Baud Rate Error, Calculating ............................ 350
Baud Rates, Asynchronous Modes................... 352
DS40001715B-page 462
Formulas........................................................... 351
High Baud Rate Select (BRGH Bit) .................. 350
Synchronous Master Mode............................... 359, 364
Associated Registers
Receive .................................................... 363
Transmit.................................................... 361
Reception ......................................................... 362
Transmission .................................................... 359
Synchronous Slave Mode
Associated Registers
Receive .................................................... 366
Transmit.................................................... 365
Reception ......................................................... 366
Transmission .................................................... 364
Extended Instruction Set
ADDFSR ................................................................... 375
F
Firmware Instructions ....................................................... 371
FSR0H Register.................................................................. 31
FSR0L Register .................................................................. 31
FSR1H Register.................................................................. 31
FSR1L Register .................................................................. 31
I
I2C Mode (MSSP)
Acknowledge Sequence Timing ............................... 321
Bus Collision
During a Repeated Start Condition................... 325
During a Stop Condition ................................... 326
Effects of a Reset ..................................................... 322
I2C Clock Rate w/BRG.............................................. 328
Master Mode
Operation.......................................................... 313
Reception ......................................................... 319
Start Condition Timing .............................. 315, 316
Transmission .................................................... 317
Multi-Master Communication, Bus Collision and
Arbitration ......................................................... 322
Multi-Master Mode .................................................... 322
Read/Write Bit Information (R/W Bit) ........................ 298
Slave Mode
Transmission .................................................... 303
Sleep Operation........................................................ 322
Stop Condition Timing .............................................. 321
INDF0 Register ................................................................... 31
INDF1 Register ................................................................... 31
Indirect Addressing ............................................................. 44
Instruction Format............................................................. 372
Instruction Set................................................................... 371
ADDLW..................................................................... 375
ADDWF..................................................................... 375
ADDWFC .................................................................. 375
ANDLW..................................................................... 375
ANDWF..................................................................... 375
BCF .......................................................................... 376
BRA .......................................................................... 376
BSF........................................................................... 376
BTFSC ...................................................................... 376
BTFSS ...................................................................... 376
CALL......................................................................... 377
CALLW ..................................................................... 377
CLRF ........................................................................ 377
CLRW ....................................................................... 377
CLRWDT .................................................................. 377
COMF ....................................................................... 377
Preliminary
PIC16(L)F1704/8
DECF ........................................................................ 377
DECFSZ.................................................................... 378
GOTO ....................................................................... 378
INCF.......................................................................... 378
INCFSZ ..................................................................... 378
IORLW ...................................................................... 378
IORWF ...................................................................... 378
LSLF ......................................................................... 379
LSRF......................................................................... 379
MOVF........................................................................ 379
MOVIW ..................................................................... 380
MOVLB ..................................................................... 380
MOVLW .................................................................... 380
MOVWF .................................................................... 380
MOVWI ..................................................................... 381
NOP .......................................................................... 381
OPTION .................................................................... 381
RESET ...................................................................... 381
RETFIE ..................................................................... 382
RETLW ..................................................................... 382
RETURN ................................................................... 382
RLF ........................................................................... 382
RRF........................................................................... 383
SLEEP ...................................................................... 383
SUBLW ..................................................................... 383
SUBWF ..................................................................... 383
SUBWFB................................................................... 383
SWAPF ..................................................................... 384
TRIS.......................................................................... 384
XORLW..................................................................... 384
XORWF..................................................................... 384
Internal Oscillator Block
INTOSC
Specifications.................................................... 399
Internal Sampling Switch (RSS) Impedance ...................... 234
Internet Address................................................................ 467
Interrupts
ADC .......................................................................... 228
TMR1 ........................................................................ 257
INTOSC Specifications ..................................................... 399
L
Load Conditions ................................................................ 397
LSLF ................................................................................. 379
LSRF ................................................................................. 379
M
Master Synchronous Serial Port. See MSSP
Memory Organization
Data ............................................................................ 22
Program ...................................................................... 19
Microchip Internet Web Site .............................................. 467
MOVIW ............................................................................. 380
MOVLB ............................................................................. 380
MOVWI ............................................................................. 381
MPLAB ASM30 Assembler, Linker, Librarian ................... 436
MPLAB Integrated Development Environment Software .. 435
MPLAB PM3 Device Programmer .................................... 437
MPLAB REAL ICE In-Circuit Emulator System................. 437
MPLINK Object Linker/MPLIB Object Librarian ................ 436
MSSP ................................................................................ 281
SPI Mode .................................................................. 284
SSP1BUF Register ................................................... 288
SSP1SR Register ..................................................... 288
MSSPx
I2C Mode................................................................... 293
O
OPA Module
Associated Registers................................................ 239
Common Mode Voltage Range ................................ 238
Effects of a Reset ..................................................... 238
Gain Bandwidth Product........................................... 238
Input Offset Voltage.................................................. 238
Leakage Current....................................................... 238
Open Loop Gain ....................................................... 238
OPAxCON Register .......................................................... 239
OPCODE Field Descriptions............................................. 371
Operational Amplifier (OPA) Module ................................ 237
OPTION ............................................................................ 381
OPTION Register.............................................................. 251
Oscillator Parameters ....................................................... 399
Oscillator Specifications.................................................... 398
Oscillator Start-up Timer (OST)
Specifications ........................................................... 403
P
Packaging ......................................................................... 439
Marking..................................................... 439, 440, 441
PDIP Details ............................................................. 441
PCL Register ...................................................................... 31
PCLATH Register ............................................................... 31
PCON Register ................................................................... 32
PIE1 Register ..................................................................... 32
PIE2 Register ..................................................................... 32
PIE3 Register ..................................................................... 32
PIR1 Register ..................................................................... 32
PIR2 Register ..................................................................... 32
PIR3 Register ..................................................................... 32
PORTA
Configuration Word w/ PORTA................................. 247
LATA Register ............................................................ 33
PORTA Register......................................................... 32
Specifications ........................................................... 401
PORTB
LATB Register ............................................................ 33
PORTB Register......................................................... 32
PORTC
LATC Register ............................................................ 33
PORTC Register......................................................... 32
Specifications ........................................................... 401
Power-up Timer (PWRT)
Specifications ........................................................... 403
Precision Internal Oscillator Parameters .......................... 399
Program Memory ................................................................ 19
Map and Stack (Banks 0-7)(PIC16(L)F1704) ............. 25
Map and Stack (Banks 0-7)(PIC16(L)F1708) ............. 26
Reading Memory ........................................................ 20
Programming, Device Instructions.................................... 371
R
RC1REG Register .............................................................. 33
RC1STA Register ....................................................... 33, 348
RCREG............................................................................. 344
Read-Modify-Write Operations ......................................... 371
Registers
ADCON0 (ADC Control 0) ........................................ 229
ADCON1 (ADC Control 1) ........................................ 230
ADCON2 (ADC Control 2) ........................................ 231
ADRESH (ADC Result High) with ADFM = 0) .......... 232
ADRESH (ADC Result High) with ADFM = 1) .......... 233
Preliminary
DS40001715B-page 463
PIC16(L)F1704/8
ADRESL (ADC Result Low) with ADFM = 0) ............ 232
ADRESL (ADC Result Low) with ADFM = 1) ............ 233
BAUD1CON (Baud Rate Control) ............................. 349
CCPTMRS (CCP/PWM Timers Control) ................... 269
CCPTMRS0 (PWM Timer Selection Control 0)......... 269
CCPxCON (CCPx Control) ....................................... 280
CLCDATA (Data Output) .......................................... 220
CLCxCON (CLCx Control) ........................................ 213
CLCxGLS0 (Gate 1 Logic Select) ............................. 216
CLCxGLS1 (Gate 2 Logic Select) ............................. 217
CLCxGLS2 (Gate 3 Logic Select) ............................. 218
CLCxGLS3 (Gate 4 Logic Select) ............................. 219
CLCxPOL (Signal Polarity Control) ........................... 214
CLCxSEL0 (Generic CLCx Data 0 Select)................ 215
CLCxSEL1 (Generic CLCx Data 1 Select)................ 215
CLCxSEL2 (Generic CLCx Data 2 Select)................ 215
CLCxSEL3 (Generic CLCx Data 3 Select)................ 215
Core Function, Summary ............................................ 31
DAC1CON0 .............................................................. 244
DAC1CON1 .............................................................. 244
OPAMP Control Registers (OPAxCON) ................... 239
OPTION_REG (OPTION) ......................................... 251
RC1REG ................................................................... 355
RC1STA (Receive Status and Control)..................... 348
SP1BRGH ................................................................. 350
SP1BRGL ................................................................. 350
Special Function, Summary ........................................ 32
SSP1ADD (MSSP Address and Baud Rate,
I2C Mode).......................................................... 334
SSP1CON1 (MSSP Control 1).................................. 331
SSP1CON2 (SSP Control 2)..................................... 332
SSP1CON3 (SSP Control 3)..................................... 333
SSP1MSK (SSP Mask) ............................................. 334
SSP1STAT (SSP Status) .......................................... 329
STATUS ...................................................................... 23
T1CON (Timer1 Control)........................................... 261
T1GCON (Timer1 Gate Control) ............................... 262
T2CON ...................................................................... 267
TX1STA (Transmit Status and Control) .................... 347
ZCDxCON ................................................................. 247
RESET .............................................................................. 381
Revision History ................................................................ 459
S
Software Simulator (MPLAB SIM)..................................... 437
SP1BRG Register ............................................................... 33
SP1BRGH Register........................................................... 350
SP1BRGL Register ........................................................... 350
Special Event Trigger........................................................ 227
Special Function Registers (SFRs) ..................................... 32
SPI Mode (MSSP)
Associated Registers ................................................ 292
SPI Clock .................................................................. 288
SSP1ADD Register ..................................................... 34, 334
SSP1BUF Register ............................................................. 34
SSP1CON Register............................................................. 34
SSP1CON1 Register......................................................... 331
SSP1CON2 Register......................................................... 332
SSP1CON3 Register......................................................... 333
SSP1MSK Register........................................................... 334
SSP1STAT Register ................................................... 34, 329
R/W Bit ...................................................................... 298
SSPOV.............................................................................. 319
SSPOV Status Flag........................................................... 319
Stack ................................................................................... 42
Accessing.................................................................... 42
DS40001715B-page 464
Reset .......................................................................... 44
Standard Operating Conditions ........................................ 386
STATUS Register ............................................................... 23
SUBWFB .......................................................................... 383
T
T1CON Register ......................................................... 32, 261
T1GCON Register ............................................................ 262
T2CON (Timer2) Register................................................. 267
Thermal Considerations.................................................... 396
Timer0............................................................................... 249
Associated Registers ................................................ 251
Operation .................................................................. 249
Specifications ........................................................... 405
Timer1............................................................................... 253
Associated registers ................................................. 263
Asynchronous Counter Mode ................................... 255
Reading and Writing ......................................... 255
Clock Source Selection............................................. 254
Interrupt .................................................................... 257
Operation .................................................................. 254
Operation During Sleep ............................................ 257
Prescaler .................................................................. 255
Secondary Oscillator................................................. 255
Specifications ........................................................... 405
Timer1 Gate
Selecting Source .............................................. 255
TMR1H Register ....................................................... 253
TMR1L Register........................................................ 253
Timer2
Associated registers ................................................. 268
Timer2/4/6......................................................................... 265
Timers
Timer1
T1CON ............................................................. 261
T1GCON........................................................... 262
Timer2
T2CON ............................................................. 267
Timing Diagrams
Acknowledge Sequence ........................................... 321
ADC Conversion ....................................................... 409
Asynchronous Reception.......................................... 344
Asynchronous Transmission..................................... 340
Asynchronous Transmission (Back to Back) ............ 341
Auto Wake-up Bit (WUE) During Normal Operation . 357
Auto Wake-up Bit (WUE) During Sleep .................... 357
Automatic Baud Rate Calibration.............................. 355
Baud Rate Generator with Clock Arbitration............. 314
BRG Reset Due to SDA Arbitration During
Start Condition.................................................. 324
Brown-out Reset (BOR)............................................ 404
Bus Collision During a Repeated Start Condition
(Case 1)............................................................ 325
Bus Collision During a Repeated Start Condition
(Case 2)............................................................ 325
Bus Collision During a Start Condition (SCL = 0) ..... 324
Bus Collision During a Stop Condition (Case 1) ....... 326
Bus Collision During a Stop Condition (Case 2) ....... 326
Bus Collision During Start Condition (SDA only) ...... 323
Bus Collision for Transmit and Acknowledge ........... 322
Capture/Compare/PWM (CCP) ................................ 406
CLC Propagation Timing .......................................... 407
CLKOUT and I/O ...................................................... 401
Clock Synchronization .............................................. 311
Clock Timing ............................................................. 398
First Start Bit Timing ................................................. 315
Preliminary
PIC16(L)F1704/8
I2C Bus Data ............................................................. 416
I2C Bus Start/Stop Bits.............................................. 416
I2C Master Mode (7 or 10-Bit Transmission) ............ 318
I2C Master Mode (7-Bit Reception)........................... 320
I2C Stop Condition Receive or Transmit Mode ......... 321
Repeated Start Condition.......................................... 316
Reset, WDT, OST and Power-up Timer ................... 402
Send Break Character Sequence ............................. 358
SPI Master Mode (CKE = 1, SMP = 1) ..................... 413
SPI Mode (Master Mode).......................................... 288
SPI Slave Mode (CKE = 0) ....................................... 414
SPI Slave Mode (CKE = 1) ....................................... 414
Synchronous Reception (Master Mode, SREN) ....... 363
Synchronous Transmission....................................... 360
Synchronous Transmission (Through TXEN) ........... 360
Timer0 and Timer1 External Clock ........................... 404
Timer1 Incrementing Edge........................................ 257
USART Synchronous Receive (Master/Slave) ......... 412
USART Synchronous Transmission (Master/Slave) . 412
Timing Diagrams and Specifications
PLL Clock.................................................................. 400
Timing Parameter Symbology........................................... 397
Timing Requirements
I2C Bus Data ............................................................. 417
I2C Bus Start/Stop Bits ............................................. 416
SPI Mode .................................................................. 415
TMR0 Register .................................................................... 32
TMR1H Register ................................................................. 32
TMR1L Register .................................................................. 32
TRIS.................................................................................. 384
TRISA Register ................................................................... 32
TRISB Register ................................................................... 32
TRISC Register ................................................................... 32
TX1REG Register ............................................................... 33
TX1STA Register ........................................................ 33, 347
BRGH Bit .................................................................. 350
TXREG.............................................................................. 339
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 412
Requirements, Synchronous Transmission ...... 412
Timing Diagram, Synchronous Receive ........... 412
Timing Diagram, Synchronous Transmission ... 412
V
VREF. SEE ADC Reference Voltage
W
Wake-up on Break ............................................................ 356
Watchdog Timer (WDT)
Specifications............................................................ 403
WCOL ....................................................... 314, 317, 319, 321
WCOL Status Flag .................................... 314, 317, 319, 321
WWW Address.................................................................. 467
Z
ZCDxCON (Zero Cross Detection) Register ..................... 247
Zero Cross Detection (ZCD)
Associated Registers ................................................ 247
Configuration Word w/ ZCD ...................................... 247
Specifications............................................................ 411
Zero-Cross Detection (ZCD) ............................................. 245
Preliminary
DS40001715B-page 465
PIC16(L)F1704/8
NOTES:
DS40001715B-page 466
Preliminary
PIC16(L)F1704/8
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
DS40001715B-page 467
PIC16(L)F1704/8
NOTES:
DS40001715B-page 468
PIC16(L)F1704/8
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office .
[X](1)
PART NO.
Device
/XX
XXX
Package
Pattern
Examples:
a)
b)
Device:
PIC16F1704, PIC16LF1704,
PIC16F1708, PIC16LF1708
Blank
T
Temperature
Range:
I
E
= -40C to +85C
= -40C to +125C
Package:(2)
ML
P
SP
ST
SL
SO
SS
=
=
=
=
=
=
=
Pattern:
(Industrial)
(Extended)
QFN
PDIP
SPDIP
TSSOP
SOIC
SOIC
SSOP
Note
PIC16LF1704- I/P
Industrial temperature
PDIP package
PIC16F1708- E/SS
Extended temperature,
SSOP package
Preliminary
1:
2:
DS40001715B-page 469
PIC16(L)F1704/8
NOTES:
DS40001715B-page 470
Preliminary
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
== ISO/TS 16949 ==
2013 Microchip Technology Inc.
Preliminary
DS40001715B-page 471
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DS40001715B-page 472
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08/20/13
Preliminary