a
Fig. 1.11 Activities for software design during an embedded software-development process
1.8.1 Design Metrics
‘A design process akesito account design mews. There ar several design mestcs for an embedded system,
nd these are listed in Table 1.3
1.8.2 Abstraction of Steps in the Design Process
{A design process i called botom4o-top design i it builds by starting from the cormponents. A design process
1 called top-to-down design if it first starts with abstraction of the process and then after abstraction the
details are created. Topto-down design approach isthe most favoured approach. The following lists the five
levels of abstraction from top to botom inthe design process:
Design Mei
Power Disipaion
| reformance
Proces deadlines
Emgincerng cost
Manufacturing cast
Hsiitiy
| preter
evelopment ime
Time-to-marke
System and wser
safe
|
Moinrnance
Invoducton to Embedded Systems
Table L8 Design metrics used in the embedded systems
—_——
Deseripion
For many systems, paca baery operated syste, suchas mobile pone o digital
‘ama the power consmed by the system i an important fxr. The batery aed to be
recharged les fequety if power dissipation is small
Instone exeetion ine ia the system measures the perfomance. Smaller exeeton|
time means higher peformence. For exile, 4 mile pore vice signals processed
between antenna and speaker in O.s shows pone perfomance. Consider another. For
frample, 4 igs camers, shooting 4 4M pac sil image in Os shows the camera
performance.
Thee are numberof processes ia the syste, fr example, keypad input processing. graphic
isla etesh oto signal processing and video sera processing. Ths ave deadlines
‘iin which each of them may Be eqired 0 fsh computations ard give resus
‘hes nce keypad GUIs and VU
Sie ofthe system is meseured in terms of (phys! space reuied,Gi) RAM in KB and
internal flash memory requirements fn MB of GB fr eaaring the software and for dat
Storage and i umber of millon lope gle io be hada.
Int cost of developing, debugging and testing the hardware and sofware sealed
ceinering cos and onetime ecg cos.
(Cost of manufacturing cach nit
Fesiblity in design enables, witout any significant engineering cot development of|
Gieret version of» product and advanced versions later on. For example, sofware
fntancenedt by adding entra fonction necessiated by changing enviroment and software
reenginesing.
time taken in ays or months fr developing the prottype ad nous esting for sstem
funcinlites I inclads engineering ime and maklag he prototype ine
“Time taken in days or months afer protorype development to put a product or wets and
Sysem safety in terms of cel fl from hand or able, the (ea phooe loking
bly and tracing bi) and ia terns of user safety when sing a product (or example,
utomobile Brake or ego).
Maintenance means anges and abtons te system: for example, dingo oping
softwar ita and harewre. Example of software rience i oa see or
functionality software. Example of datz maintenance is addons Angi, wallpapers,
‘ideo ips in ob phone of extnting card expiry dt a cse of smartcard ample of
arate mainfenanosisaddlonl memory o changing the memory sick nail computer
sd digital camera
(1) Requirements: Definition and analysis of sytem requirement, Is only by 2 complete clarity of
the equred purpose, inputs. outputs, uncioning, design metrics (Table 18) and validation requiremen's
for finally developed systems specifications that well designed sytem canbe crested. Tere has to
be consistency in the equiremedts.40 Emboddod Systems
(2) Specifications: Clear specifications ofthe cequzed system are sunt. Specifications ace «be
precise. Specifications guide customer expectatwns from the product. They also guide system
architecture. The designer needs specitiatons fr i) hardware, for extmple, peripherals. devices
processor and memory specification, i) dat types and processing specications, ii) expecte system
‘behaviour specifications iv) constrains of design, and («expected hie eyele specifications. Press
specifications are analysed by making sso inputs on eves outputs on cventsand how the processes
activate on each event (inept).
(G) Architecture: Data modeling designs of atibutes of dala structure, data ow graphs (Section 62),
program models (Section 6.1), software architecture layers and hatUware architecture are defined
Software architectural layers areas follows
1. The first layer isan architectural design. Mere, a desig for system architecture is developed. The
question arises a8 to how the different elements—data structures, databases, algorithms, contol
functions, state transition funtion, proces, dala and program flow-—are to be organised
2. ‘The second layer consists of data-dsign. Questions «this stage areas follows. What desig of
data structures and databases would be most appropiate forthe given problem? Whether data
organised asa tee ike sruture will ke appropiate? What wil be the design ofthe components
in the data? [For example, video information wil have two compenens, image and sound
3. ‘The third layer consists of imerface design Important questions at this tage areas follows. Wht
shall be the interfaces to integrate the components? What isthe design fec sytem intreation?
‘What shall be design of interfaces wsed for taking inputs Fom the data objec, stetures and
databases and for delivering outputs? What willbe the port structure for eecevirg inputs and
transmitting outputs?
Components: The foun tayer sa component level design. The question a this stage isa ftaws,
‘What sal be the design ofach component? Thee national requicement inthe design of embeded
system, thateach component shouldbe optimised lor memory usige and poser dissipation, Components
of hardware, processes, interfaces and algorithms, The following iss the common hardware compenents
1. Processor, ASIP and single purpose procesors in te system
2. Memory RAM, ROM or intemal and externa sh or secondary memory inthe system
3. Peripherals and devices internal and exter othe system
4. Ports and buses inthe system
5. Power source o battery inthe system
During software development proorss we can model the components a object-oriented, Table 1. list the
stages as component-based objesoriented software development process
(5) System Integration: Built components are integrated in the system, Components may work fine
independently, but when integrated tay nt fulfil the design mets, The system is made o function
and validated. Appropriate ests ae chosen, Debugging tools are used to corect eroneous functioning,
Each component and is interface system integrated after te design stage. Program implementation in
«language and may use an integrated developmen envionment (IDE), and source code engineering tos,
Which shoul follow the model, software architecture and design specifications. Prograin simplicity should
tbe maintained during the implementation process.
«
‘The design stages range from abstrtion A» detiled designing to verification activites. Continuous
‘refinement in design can be made by effective communication between designers and implementers. Soflvare
design can be assumed to consist of four layers: architecture design, dala design, interfaces design and
‘component level design.
lnvodton Embedded Syste («)
Table 1.9 Components-based object-oriented software development process
‘Actes
ior Model Deficiency
Suge | Component tht could be wed in software development identi
Suge? Selection of availabe clases (single logically bonded 70098) OM Ke or bust nxn
sottare component rier ary eee
Sips} Sertcomponets, wich ar avalable and eusable by re-engvcering and case the ele
eich ae onsale components ae at
avaiable in regu
Stage 4 Re-ngincer components and crete ueavalbe components weit
Stage S Couset software fom te components and tes them
| sa
lee
Actions at each step Research by software engineering experts have shown that on an average, a
designer needs to spend about 50% of the time for planning analysis and design, 40% for testing, validation
and debugging and 10-15% on coding. Action required tobe taken a each step inthe design process sisted
in Table 1.10
6 eave conte il fl validation of software
Table 1.10 Action to be taken at each step of design process
‘Benga Wate
Desripion
Anatyis, Design i arly
“The ces of sali i aed to improve design to moet specications and mets
Step for improvement
Verification Sysem design must be veiedw ena that mets the design mts gven in Table 1.8
1.8.3 Challenges in Embedded System Design: Optimizing Design Metrics
Following are he challenges tha arse during the design process.
Amount and type of hardware needed: Optimizing the requirement of microprocessors, ASIPS und
single purpose processors in the system on the bass of performance, power dissipation cost and other design
metres are the challenges ina system design. A designer also chooses the appropriste hardware (meniory
RAM, ROM or internal and extra flash o secondary menor. peripherals and devices intemal and external
ports and buses and power source or battery) taking into account the design metrics given in Table 1.8: for
‘example, power dissipation, physical size, number of gates and the engnecring, provtype development und
manufacturing costs
‘Optimizing Power Dissipation and Consummpion: Power, consumption ding the eperaionl and ile
sate of system shouldbe optimal. The following metheds are used to meet the design challenges,
Clock Rate Reduction Power disipation typically reves 2.5 pW per 100 kz of reduce tock rate
So reduction from 8000 kHz to 100 kHz reduces power dissipation by about 200 IW, which ic nary similar
to-when the clock is nonfunctional. (Remember, total power dissipated (energy required) may not reduce.
This is because on ducing the clock rate, the computations will ake alongs tme nd total energy required
equals the power dissipation per second multiplied by computation ine}fa] Emboted Systems
bad
Te power25 Wt typical te esl dspaton ded o pea ins nd few ter ais By
psa eck a ler fetency odin the powerdown noth pcs th drapes
Sra) Power rd teat genre de) Kai gue nlc oes
{beveled owe sion wine ats Wadatd RF (Rade Fcc) power defends on he RF
Sone ne gn ih ede oe ona in“ON" stress vee asa neo
SENMOSPET uanior and Oat ede eat goraion
Voltage Reduction Inportable or hand-heddevics such as acellular phone, comparedto 5 V operation,
‘aCMOS ercuit power dissipation reduces by one sath, ~(2V/SV},in2.0 V operation. Thusthe time intsvals
reeded for recharging the batlery increase by afactor of six.
Wait, Stop and Cache Disable Instructicns An embedded syste may ned tobe run continuously,
‘without being switched ofthe sytem design, Uerefoe, is constrained by the need to limit power dissipation
‘while itis ON but sin idle state. Total power consumption by the system while in eunning, waiting and ile
states should be limited. A microcontoller must provide for executing Wait and Stop instructions forthe
power down mode. One way to reduce power dissipation ito cleverly incorporate into software the Wait and
Sop instrtions. Another i to operate the sytem at the lowest voltage levels inthe ile state and selecting,
power down mode in that state. Yet another method ito disable use of ein structural Units ofthe processor
for example, caches—when not necessary and to keepin disconnected sate those structure units that are not
needed during «particular software execution, fr example timers or 10 units.
Operations canbe perfrmed at low volage of educed clock rate in order to contol power dissipation. For
‘ebeded system software, performance analysis during its design phase must ala inclode the analysis of
power dissipation during program execution and during standby. An embedled system has to perform
tasks continuously From power up to power-off and may even be kept “ON” continuously. Clever eal-time
‘programing by using "Wait and ‘Stop insirections and disabling certain units when not neded is cme
‘met of saving power during program execttion
Process Deadlines Meeting the deadline of all processes in the system while keeping the memory,
power dissipation, processor clock rate and cost at minimum is a challenge
Flexibility and Upgrade ability Flexibility and uperede ability in design while Keeping the cost
‘minim and without any significant engineering cos isa challenge. Flexibility and upgrade sbiity slow
different and advanced versions ofa product ote inroduced in the market later on
Reliability Designing a relble product by appropriate design, testing and thorough verifeation is
ctallege. Te goal of testing is to find eros and o validate that the implemented software sas pr the
Specifcion and eqiement Verification fest an activity to ensure pei function ae eorecty
‘mpeneated.Vaaton refers to an activity wo ene tha the system hat hasbeen created is a per the
requirement ageed upon tthe analysis phase, an to ensure is ait.
“1.9 “FORMALIZATION OF SYSTEM DESIGN
Farmalizaton of system design i done using a top-down approach by abstraction (Section 1.82) and by
+ Detling equirements and specifications of hardware and software
Introduction to Embedded Systoms
‘+ Dotining architectures of hardware and software
+ Covdmg and impemsntaton a per architocture
{Testing validation and verification of system
Since a diagrammatic mode! clears the design conceps beter than abstraction, 2 modeling language, foc
formalization ean be used, The Universal Modeling Language (UML) is used. In UML. a designer deveribes
the following
1. "User Diagram’, “Object Diagram’, ‘Sequence Diagram, ‘State Diagram’. “Class Diagram and
“Activity Diagram
2. Clases and Objects, which describe dently, atrbutes, components and behaviour
3. Inertances of the clases and objects
44 Interfaces of the objcs ad their implementation atthe objects
5. Strvetural deweription of the dexign components
6. Behavioral description in toms of sate, sate machine and signals (Section 6.3)
7
Se
Evens desertion
ton 65 will describe UML in detail. Chapters 1 and 12 will describe the model design examples detail,
“1.10 “DESIGN PROCESS AND DESIGN EXAMPLES
1.10.1 System Design Process Examples
Chapters 11 and 12 wil deseribe design examples in det
1.10.2 Automatic Chocolate Vending Machine (ACVM)
Lets consider an automatic chocoite vending machine. This interesting example given here helps reader
to understand several concepts of programming an enbeided system as 3 muliasking system
Figure 1-12 shows the diagrammatic representation of ACYM, Assume that ACVM has following
ceomponent:
[thas Keypad on thetop ofthe machine. That enables child to interac witht when buying a chocolate
“The owner can also command and intract wit the machine
2. Ithavan LCD display nit on the op of the icine, It displays menus, text entered into the ACVM.
‘nd pitograms, welcome, thank you and other messages. Ic enables the child as well asthe ACYM,
‘owner to paphically interact with the machine. Ils displays time and date. (For GUIs, he keypad
land LCD display units or uch seen are basic units.)
3. Ithas coin insertion stot anda mechanical coin sorter so that child can insert coins to buy a chocolate.
Tthas a delivery slot 50 tht cld can collect the chocolate and cons, if refunded
5. Ithas an lnteret connection port sing a USB based wireless modem so that owner can know stats
‘ofthe ACYM sales fom aremee location
‘ACV Functions Assume that ACYM functions areas follows:
|. The ACVM displays the GU anf the child wishes to enter conactinformation, birthday information
‘or get answer to FAQS; it splays the appropriate menu
2. Tedisplays a weleome messege when in ide state, I also continously displays time and date atthe
Fight botiom corner of display seree. It can also intermittently display news, weather data or
‘advertisements or important information of interest daring ide state(«] emoesia Syston
s
4
‘When firs coin i inserted. a timer also stars. The child iv experted ts insert sl requiee! eins in
2 minus.
Alter? minutesthe ACV will display a query to the chil if the child docs not insert salfclent coins.
Te the query is not anywered the coins ate refunded.
Within 2 minutes if sufficient coins are collected, it displays the message. “Thanks, wat for few
‘moments plese", daliversthe chocolate through the delivery sll and displays message. “Collect the
chocolate snd visit again, please”
Hardware units _ACVM embeds the following hardware units
3
4
Microcontroller or ASIP (Application Specific Instruction Set Proces-or)
RAM for storing temporary variables and stack
ROM for application codes and RTOS codes fr scheduling the tasks
Flash memory for storing user preferences, contact data, user address, user date of birth, user
iemiticaton code, answers of FAQs
“Timer and interrupt controler
A TCPAP port (Iniemet broadband connection) tothe ACVM for remote conto and forthe ownee to
ei ACYM status reports
ACM specific hardware to sor cons of different denominations. Bach denusninatio coin generates
‘se of stats and input is and port-incerrypss. Using an ISR for that port, the ACYM process eas
the port status and input bits. Te bits give the information about which coin has en inane. ter
cach read operation, the satus bits are veset by the routine
Power supply
a=)
{Use _wweeiess_}
Moser
[tester
[eerste
Fig. 1.12 Diagrammatic representation of the ACVM
Software components ACVM embeds the following soltware components
1
3
4
s.
6
Keypad input red task
Display sk
Road coins ask for find
Deliver chocolate task
TCPNP stack processing task
TTCPIIP stack communication task
ins sted
1.10.3 Smart Card nN
‘Smart card is one othe most used embedded system today Is used for evedit-eit bankcard, ATM card,
e-purse or e-Wallet card, identifeaton card, medical card (Tor istry and diagnosis details) and ead for @
Irroducton to Embedded Systems 45
number of new innovative applications. [Reader may refer to a frequently updated website. tpi!
wor sguthery @ia.ne fr the answers of Fequentl asked question about card. |The security aspect of
‘paramount importance for swurt card use. when used for financial and banking-elaed vansictions TRcoder
‘may cefer to huip//wworhome hkstarcomalanchan!papertsmartCardSecurty! and hip.J/www rescarch,
ipmcomsecure_systemssard hum fur details ofthe card-securty requirements |
‘The smart cai is a plasie ear ISO standard dimensions, 85,60 x 53:98 x 0.80 mm. [isan embedded
‘system on acard SoC (System-On-Chip 150 recomnmended standards are IS07816( 0 4) fr host-rauchine
‘contact-based cards and 18014443 (Part A or B) lor the contactless cards, The silicon chip is just few
‘multimeter in sie and is concealed in-between the layers ts very small size prec the cad from bending
Figure 1.13 shows embedded-system hardware components for a contactless smartcard
‘A Embedded Systm
Contsel.ies St ard Components
eer
ems
(erase!
aA ta ratio aoe
ee one 77 le
[eer
1p Tima
[ime na | mptece |
ret Cansoter ‘snc’ |
ones Key Weasor |
‘Crest
‘System Power Sirly
onca
Fig. 113 Embedded hardware components ina contactless smart card
Embedded Hardware ‘The embuided hardware components areas follows
‘+ Microconieoller or ASIP
RAM for temporary variables and sack
(One time programnchle ROM for application codes and RTOS codes for scheduling the asks
Fash fr storing user data, ser aes. user identification codes, card umber and expiry at
“Times and intapt contol
‘carieeqoncy 16 Mie goneting cuit and Amphi
Interfacing cite forthe 10s
Charge pump fr delivering power othe ante for ransmision and for syst iris. The charge
pp tres chage fom recived RF (rai frequency) a the card antenna in its vicinity. [The charge
ump sasimpecicithat consis ofthe diode and bigh vale feraelecics materi based capacitor
“The dels ofthe basic hardware units rs follows:
sd Shifted Key (ASK) modulator4% Embedded Systems
1. The Microcontroller used can be MC5SHCIIDI or PICIECRS or a smartcard process Philips
Smart XA ora similar ASIP Processor, MCSSHCIIDO has 8 KB intemal RAM and 32 ks EPROM
and 273 wire protected memory. Most cards we 8-bit CPUs. The recent introduction inthe cards is of
{1 32-it RISC CPU. A smartcard CPU should have special features, fr example, security lock. The
Tock is fora certain sections ofthe memery. A protection bit atthe mirooontolle may protect | KIS
‘or more dats From maification and access by sn extemal source or instractios outside that memory
‘Once the protection bit is placed at the maskable ROM in te mierocontoley, the instructions or data
‘within that part ofthe memory are accessible fom instructions in that part only Ginter) aed not
accesible from the extemal insrutions or insrctions ouside that part. The CPU may disable wecess
by blocking the write cycle placement a he data its onthe buses For instructions and data protection
at the physical memory ater cetin phases of card iniializaion and before issuing the card to the
User Another way of protecting iss Follows: The CPU may access by using the physical addresses,
which re diferent fom the logical address used in the program,
2. ROM is used i the card. The usual size is 8 oF 8 KB Fr usual or advanced cryptographic features in
the card, respectively, Full or put of ROM bus activates only after a security check. The processor
protects apa of the memory from access. The ROM stores the flfowing.
i. Fabrication key, which is unique secret key fr each ca. It is inserted durin fabrication.
ii. Personalization te, whichis inserted after the chip is tested on a printed circuit board. Physical,
axdeesses are used in the testing phase. The key preserves the fabrication key and this key insertion
preserves the ex personaliation, Aller insertion of this key, RTOS and applications use only
logical adicesses
ii, RTOS codes
is. Application codes
¥_Avulilization Tock to prevent madiication of two PINs and to prevent access to the OS and
pplication instntions, It stoes afl the card enters the utilization pha,
3, BEPROM or Fash scalable. These means that onl that put ofthe memory required fra particular
operation will unlock for use. The auhorier wil use the required part: the application will we the
other part. I is protected by the access conditions stored therein. lt toes the following:
{. PIN Personal Identification Number. the allotment and writing of which is bythe authorize for
ample, abank)andits seis posible ty the late only by using the pesonaliationand fabrication
keys. It for identifying the ead user in Future transactions. Card user is given this key
Altematvely, nifiable password is given tothe user and password opens the PIN Key.
ii, An unblocking PIN for use by the authorizer (say the bank). Through ths ey. the card iret
‘entities the auhorizer before unblocking. Dats ofthe user unblocks forthe authorizer and
Storing of information onthe card is posible bythe authorizer through the host
ii, Access conditiors for various hierarchically aranged da ile,
iy. Cand wer dat, for example, name, bank and branch identfiaton number and account number
(or health insurance details
vs Data post issue thatthe application generates. For example, in case of e-purse, the details of
previous wansacions and curent balance. Medical hisiory and diagross dtalls andor previ
insurance claims and pending insurance claims record in ease of a medical car
vi also stores the application's non-volatile data
vil Invalidaion lock sent by the hos after the expiry period or ea misuse and user account closing
rexucat I hacks le data files ofthe nsx or ekencitay individual ile or both,
4, RAM stores the temporary variables and stack during eard operations by cunning the OS and the
applicaion
Introduction to Embedded Systems. far J
5. Chip power supply voltage exact by scare pump eitcut The pump extracts the eae fran the
‘signal rom the host analogous to what mouse desi a computer and delivers the regulated voltage
tothe aid chip, memory and 10 systom, Signals cas be Frm antcana or rom lock pin. na typical
curd operation axing 0.18 technolo. 1.65.5 V isthe teshold init and for. pn ieenology,
271055.
6, 10 System of chip and host interact thewugh asynchronous svial UART (Section 32.3) a 9.6 k or
1116 of 115.2 k baud. The chip inerconmics to card hosting sjstom (reader and writer) etter
Through the gold contacts oF though a centinster sized antnaa on each side. Te later provides
‘contactless inerconnection between the 10 pins which are mean or contact based interaction, RST
{Reset Signal fom hast) and Clock (Hem hos)
17, Wireless Communication foc 10 interaction i hy rations dough the antenna coils fr coat
interaction. The card and host interact tough a card modem and a ost modem, The aplication
rococo data unit (APDU) isa standad for communication betwen the ear and hest computer
‘Modulation is with 10% index amplitide modulating carrier of 13.66-13.56 Mbps ASK (amplitude
shied keying) suse forcontactess communication at dts ratesot~1 Mbps. One-sixtenth frequency
subeatier modulates though BPSK (Binary Phase Shifted Keying
Embedded Software Smart card eters ihe folio
1. Boot, initsisstion and OS peograns
2 Sit card seve fle system
3. Connection establishment and verination
| Conimaication with host
5. Cryptography algorithm
6.
7
softwite components:
Host authentication
Cand authentication
dion paraneers of rvent new data sen by the bot (or example, present balance let)
“The sinart card is an exeimplry secure embedded system with security Softvare. The card eth.
cryptoprapic soiware, Embedded software inthe card neous special Features in its operating system ove
and above the MS DOS or UNIX system features. Special features needed areas fllows
1. Proicted envivnnen.H-mcans vtiware should be stored in he proteted pat oF the ROM,
2. Restricted! rosie ensrnament
A. IOS, every method, class and rn time idea soul e sealable
4S Code-sive termed unl be epitnun, The system needs shoud mo exceed 64 KB memory.
5. Limited use of datatypes: multidimensional arays. kone Gb inegcr and eating points ad very
limited use of the roe handlers, exceptions (Section 4.22), sigals (Sections 6 Sand. 10), stialization,
debugging und profiling [Serialization i the process of converting an objet ino dat stream (oe
transfering itt network or From one proces 10 snther. Te deserialize dat arc the receiver end}.
6, A three-layered file sytem forthe dats. One file forthe maser flew toe al ile headers. header
ens File status, access conditions andthe ile lok. The second file is a dedicated file to hold file
frouping and headers ofthe immedi sucessor elementary files ofthe group. The third file isthe
elementary file hold he file header and its le data,
1. Ther is eter a fixed length fle management ora variable length fle management with each file
im __ having a predefined offct
8. Clases Forte network, sockets, connections, data grams, characte input output and steams, security
management, digital-cenificaton, symmetne and asymmetric keysbased cryptography and digital
signatures ’Emboddod Systoms,
1.10.4 Digital Camera
Digital cameras may have 4 1 6 M pine! sil images, clear visual diplay (ClearVid) CMOS sensor. 7 cin
wide LCD photo display screen, enhanced imaging processor, double anti blue solution and high-speed
provesting cine, 10X optical and 20X digital zooms and can also record high definition videoclips. It
therelowe has speaker microphone(s) fer bigh quality recorded sound. I is an auiivideo out port for
conrectng to a TV/DVD player or compute.
Letus assume that the camera is sill jas a camera. Figures 1, 14a) and (b) sow hardwae and software
ponents in simple digital eamera, Assume thal the camera has the following Components
| [tebarteaecsentartone ven] [Kor oo |
| =m
ee
| [Dee ——-
Fig. 1.14 (a) Digital camera hardware components (b) Digital camera software components
1. thas keys oa the camera. That enables a usr to operate the camera. thas navigation keys to mivigate
Uhrough the images back and Forth.
2. Shuter, lens and charge coupled device (CCD) array sensors for images in sizes 2992 x 1944 pixels =
5038848 pixels, YGA (E-mail) 640 480 = 307200 pixels, 2592» 1728 = 3.2 M pixels, 2088 x 1536
pixels = 3 M pitels.or 1280 x 960 pixels = 1 M pixel.
3, Tihas a good resolution photo quality LCD display unit onthe hack of camera to show photographs
‘recorded video-lips. It displays text suchas image, shooting data and ie and serial number.
In isplays messages 1 displays the GUI menus when the user interacts with the came.
4. has agelf-timer lamp for fash
5, Intemnal memory lash to store OS and embedded software, and limited nutes of image files
6. Flash memory stick of 2 GB or more for large storage.
-
Introduction to Embedded Systeme [4
7. teh Universal Serial Bus (USB) por (Section 3.10.3 or Be
computer and printer,
ih interface. which cannes i toa
Camera Functions Assume tht the camera funetions is fll
|. teisplays the trame view on the LCD screen so that usce ci aj the camera inclination before
‘hooting the frame
2 Walsplays the saved images onthe LCD using navigation keys
3. When a key fr opening he shulter i presed, the Flash ann glows and the sf timer ciruit switches
of the lamp astomaticaly.
44. The rae ight fallson the CCD array, which wansmits tho bits foreach peli each row in the Fame
through an ADC. Bits from dark area pines in each row are sed for offset comections inthe CCD
signal fr light intensities in each rv.
‘The CCD bits ofeach psel in each row and column are offset crtected using a CCD signa processne
«CCDSP),
6, The procesed signa te compressed using 2 PEG CODEC and saved inne jp file foreach rams.
[A DSP does compression using the the discret cosine transformations (DCTs) and decompression by
inverse DCT. Thoreater.it also does Hulfman coding for JPEG compression.
A DAC send the inputs forthe display unit. The DAC gets the inp from the pixel pmecessor. which
et the inpus fom the JPEG files forthe saved images snd gets input diretly fom the CCDSP
Hough the pixel processor or the frame inthe present view”
igital Hardware units The camera embeds te following hardware units
|. Mierocontoller oF ASIP
2 Mltiple processors (CCDSP. DSP. pixel processor totes)
3. RAM for storing temporary vribles and stack
4. ROM lor application cades and RTOS codes Fr scheduling tasks
5. Tine fash memory Tor storing see preferences, contact dl, user adress. user date of hi. usce
idenieaton code. ADC, DAC and interut controller (Sections 1.3.3, 13.5. 147 and 13.11)
USB controller (Section 3.10.3)
Direct memvey access conrier (Section 4.8)
LCD contmller (Section 334)
Baery
Software components. The camera embeds the following software components
CCD sia geocensng for offset correction
2 JPEG coding
3. JPEG decoding
4: Pixel processing before display
5. Memory and file systems
6. Light. lash and display device drivers
1. COM, USB port and Bluetooth device divers for port operations for printer and computer
‘communication conto
on
1.10.5 Mobile Phone
The mobile phone today has a large number of features. I has sophisticated hardware and software.{9} Embedded Systems
Hardware units» mebile phone embeds an SoC (System-on-Chipy incense follwing hardware units
|. Microcontroller or ASIP JAn ASIP is configured to process enewtiny and deciphering and another
tes the vice compression, Third ASIC dal, modulates, demodulaes. interfaces the Keybosrd and
touch serecn or matte fine LCD graphie displays, and processes the data input and recall of data
Fro mesnoryh
2, DSP core. CCDSP, DSP, video, voice and pixel processors
3. Plash mentor stick, EEPROMS and SRAMS
44, Peripheral circuits, ADC, DAC and interrpt conolier
5. Ditect memary access controller (Section 48)
6
1
LCD contcller (Section 3.3.4)
Bauery
Software components The mobile phone sofware development tools are a follows:
1. OS (Windows Mobile, Palm, Symbian) oF BREW
2) Java 2 Micro Editon J2ME) along with KVM asa Java Viaual Machine Section 574)
3. Java Wireless toolkit with JDK (lava Development Kit)
“The mobile phone embeds the Following software component
TE Memory and filesystems
2. Keypad, LCD, serial, USB. 3G or 2G pont device drivers for port operations fr keypad, printer and
computer communication contol
3. SMS (Short Messaging Service) message creation and communicator. contact and PIM (personal
information manager, task-to-do manager and ena
‘Mobile imager for uploading pictures and MMS (multimedia mess
“Mobile braser for access 1 the Web
Downloader for Java games, ring fone gnes. wall papers
Simple camera with (Section |.10)
Bluetooth synchronization. IDA and WAP connetions support (Section 3.13)
ervey
1.10.6 Mobile Computer
“The mobile computer has Windows CE or Windows mobile as OS. [thas w touck sereen for GUL, The wer
uses sys to enter commands. Ithava vieual keypad (the keypad displayed en the screen and entries of text
and comimands is through te stylus.
In addition to phone, a mobile computer bas following software components
{. OS (Windows CE, Windows Mobile, PocketPC. Pali OS or Symbian OS)
Touch sereen GUIs, memory and file systems
‘Memory stick
Outlook. Internet explorer, Word, Excel, Powerpoint, and handwritten text processor
Applications or enterprise software
1.10.7 A Set of Robots
‘Consider a set of robots. One robots the master robot (music director) and seven ae slave robots conductor).
Assume that thestisused to ply an orchesta Figures 1.14) and (b) show hardware and software components
{nthe sot of robo. Assur: that the robot has the following component
1. The master robot signals the commands and slave robots play accordingly
Introauton to Embedsed Systoms
e)
Each mbt is asumed to have ive degrees of freedom. Each robes hava mochanical ystem of five
degrees of freedom. At each degree of freedom, thre is a servociotor A servomatar conto by
PWM methud (Seetion 1.7). Each motor fs controlled in squence tlt the robe pron the
esiced etn
3. sch root hava mierocontraller with expansion ports, Po. P8. Actually axngle ASIC cam perfonn
‘line port fonctions of a microcontroller, Howevesnce the engineering cst of ASIC development
is igh. «general purpose microcontroller 6BHCT2 or 8051 is use.
“The port eutpuls comect he metors snd PWM outputs dive the motors in cach robo
Each robot has eral 10 with EDA protocol (Section 3.13.1)
Tneral memory Mish to store the OS, embedded sofware and limited amount of music
There is a mas file processor Fo playing the music. Slave robots have speaker outputs fe playing
‘Master Robot Functions Assume that maser robot functioning iv a follows
|. Hreceives comands from s emote controle to stat and sop the rasic and the code forthe speviic
orchestra toe played
2. sends PWM signals othe pos for moving the sticks in oth hands as per the program,
3. Wesublishes and binds the sockets the vitua devices) connection with the slaves. I sends the signals
through rockets using DA protocols. The byte streams respons to the clients ae as pe the Music
File tobe played by the save
‘Slave Robot Functions Assume tat slave robe functioning i as follows:
1. establishes and binds the sockets (he viral devices) connection with the mast
2. Mt receives rom a miner socket the commands accep () and write (it alo receives commands 10
start and stop music ad the code forthe specific orehesta tobe played
receives the signals through sockets using IeDA protocols. The bye steams from the server areas
per the music ie being pled,
Hardware units Robots embed the following hardware uit
1. Microcontroller or ASIP
2 Masi file procesor
3. RAM for sexing temporary variables and stack
4. ROM for application codes and RTOS codes for scheduling bot setions and asks
5 Timer Mash meniory for storing wer preferences and musi Files
6 IeDA controller (Section 3.13.1)
7
8
Dincct memory access contllr (Section 48)
Powersupply source or battery
Software components Robots embed the fllowing sofware components
1, Socket functions
2. Music coding
3. Music decoding
4. Memory and ile systems
5. Light, flash and display device divers tam
6. IrDA and socket port device drivers
17. Motor devers
8 10 15Rs)
52 Embedded Systems
~iScoto,Tener
|_owac: Pune
| [se tseen i usuoh or rOAos es
Fig. 1.15 (o} Hardware components in the set of robots (b] software components in the set of
robots in which a master robots signals the commands and slave rabots play according
to the signals from the master
“1.11 “CLASSIFICATION OF EMBEDDED SYSTEMS
‘We ean elasify embedded systems into thre type as follows,
1. Small scale embedded systems: These systems ate designed with a single 8 or 16-bit
microcontale:
Fy have ite adware and softwar complies ad inset ene eign
They mayeven ebay ops When deeaping ened swash anc semble
dcr meted develomen envsanmen(IS8 ose the mica
or procevor ular te nai programming os Ying" lneue grams se compa io
the aebly and execuabe codes te ppromy located ne spent meray he setae ak
to whi the memory avalble and keep WO te need ty litt poverdaspaton when Ue
1. Medium scale embedded systems: These ssems ae uu designe with ingle or afew
16- or 32-bi micecontoner: DSPs RISC. Ths systems may aso employ the ready aaa
single perce proceso od IPs espind later Yor te ato anton for expe Ds
ineracing [ASSP« and IPs ay ao have to be appropri configured by he SskmSfate
before ing ints ino she sen] Media sealed syiems hae ot haar
sd sft competes For compe stare Sein.efelowin opammagolear sve
ices Cevtav RTOS, sore cove ensnsing ol ims dugg a at ieee
Aevelmestenvionneat Siar el so provide solaton 10 adware complesiies
5. Sophisticated embedded systems: Sopisieted embeded system hae enous barwae
anon compleisand ray ce sve IP, SIPs, sable posse congue pce
ti programmable less They ae wed fr eating ede aie tha ee Rarote and
Sotvarecodesign an compen ht ave oe netted ial stem The a eonsaine
by te prcesing sessment hart nts Cerin sofa tons ach neyptn
rroguction to Embodied Systems e
and deciphering algorithms, discs cosine tansformation and inverse rnsformation agoritnss TCP?
IP protocol stacking nd netor: rier functions are implemented in the harvaré to obain kita
speeds. The software implements some of the functions of the hardware resources in the ssn
‘Bevelopment tots fr these systems may not be readily available a a reasonable cost or may not be
valle all In some cases, « compiler oF eget compiler might have tobe developed for these
[A retagetable compiler is one that configures according the given target eafguraion in em
"1,12 “SKILLS REQUIRED FOR AN EMBEDDED SYSTEM DESIGNER
“Anembeded sytem designer has o develop product using tre aailable too within the given specifications,
cont and time free. (Chapters 6, 13 and 14 will cover the design aspects of embedded sysen.
1. Skills for Smal! Scale Embedded System Designer: Author Tim Wilmsinurs i his book
‘sats that the following skills are neded in the inividua::""1 or team thats developing small
Scale ymem: “ull understanding of microcontrollers witha basic knowledge of compute architecture,
digital electonie design, software engineering, data communication, contol engineering, motors and
ctuators, sensors and measurements. analog eleconic design and 1C design and manufacture” Specific
kills wil be needed in specifiesuations. For example, contol engineer knowledge will be eee
for design of contol systems, and analog electonic design knowledge willbe needed when design
the system interes. The basis aspects of the following tops will be described in this book eo
‘prepare the designes wha aleady hak & good knowledge ofthe microprocessor or microcontoller to
be used. (i) Computer architecture and orgarination. Ci) Memories. (ii) Memory allocation
(iv) Interfacing memories. (v) Burning (a term used for porting) the executable machine codes in
PROM or ROM. (v! Use of decoders snd demultiplexers. (vi) Direct memory access, (Vi) Pons.
(vi Device rivers in assembly (x) Simple and sophisticated buses. (x) Timers (xi Inteupt servicing
snctanism. (i) C programming elements. (aii) Memory opinnizaton. (xiv) Selection of hardware
and microcontole, {xv Use of ty Circuit Emulators ICE}, erose-usemblers and testing equipment
(ivi) Debugging the software and hardware bugs by using st vectors. Basic knowledge in other
reas—software engineering, da cosmmunication, contr enginesrng. notors and actuate
nd measurements, analog eletronic design and IC design and manvfacture—can be obtained
from the standard text books avslable. A designe interested in small-scale embedded systems
may nia need at ail concepts of interrupt latencies and deadlines and their handling, the RTOS
programming tons described in Cages: 9nd 10 andthe program models given in Chapter 6,
2. Skills for Medium Scale Embedded System Designer: ¥aeledge of *C'1C#+lhava
programming, RTOS programming snd program modeling sis are mst to design medium-scale
tmbedded-systein. Knowledge of he following are etal.) Tasks or threads and their scheduling by
RTOS. (i) Cooperative and preemptive scheduling. i) Iter processor communication functions. iv)
Use of shared dl. and programing the cca setions andre-entrant functions. (v) Use of semaphores,
mailboxes, queues, sockets and pipes. (vi) Handing of erat latencies and meeting task deans (i)
Use of various BTOS functions. (vi) Use of physical and virual device drivers. [Refer vo Sections 426,
7.10and7. 11] Chapters 4t0 1 give detailed deseriptoas ofthese seven along with examples and Cher
11 and 12 provide on understanding oftheir use with de hep of casestudies. A designer must haan:
to an R708 programming tool with Application Programming Interfaces (APIs) forthe specific
microcontroller to be used. Solutions 0 various Functions like memary allocation, timers, device divers
and interrupt handing mechanism ae readily availabe asthe APIs of hx RTOS, The designer needs toEmbedded Systems
‘now ony the hardware organizaviomand us of tes’ APIS. The microcontroller press thn epee
small sytem element for he designe ad ite Knowledge may suc,
3, Skills for Sophisticated Embedded System Designer: A wa is needed to e-design ant
solve the high level complexities of hardware and software design. Embedded system haste
engineers should have skills in hardware units and hasie knowledge of (C7AC+ and Java, RTOS snd
‘other programming tools. Sftwareengincer should have basic knowlege in hardware and ar
knowledge of. RTOS und ther programming tos A Final optimum design solu sthen cbtined
by system integration,
‘Summary
‘An embeded sytem is one thit hs embedded software it computer hawae, which makes it ayo
Software tots.N&2~ 2G BRK
SRR RORSL BO
In this chapter, we wil lear the following
1 8051 architecture in brief and its processor. memory. ports, Counterstimer
Seria 10 and interrupt handler wits
2. Real world wterfacing, and internal and external buses that interconnect the
rocessor with the system memories, 10 devies and all other system units
Imverfacing examples with keyboard, displays, ADC and DACS
‘Advanced processors x86, ARM and SHARC architectures
Processor and memory organization
‘Insarucion-level parallelism and superscalar, processing, pipelining and cache
tuuts for improved computational performance of the processor by faser
‘rogram execution
Various types of memory and their uses
Devices and memory addresses allocations
Performance metrics to measure the performance of a processor
10. Processor selection for embedded sytem
1, Memory selection for embedded system
” 2.4 “BO5T ARCHITECTURE
‘The following subsections summarize the 8051 architecture in brief. A ceader may
refer toa standard text for details
2.1.1 8051 Microcontroller Architecture
Figure 2.1 shows the architecture ofthe classic 8051 microcontroller. Classic means
the original version, based upon which new enhancemetts and vesions are provided
‘The classic version consss of following hardware:
1. A 12 Mie clock, Processor instruction cyte time is! us.
2. An B-bit ALU. The internal bus width i 8
3. CISC Complex Insirvction Set Computer) architecture. (CISC provides many
modes for addressing operands in arithmetic, laical and other instructions,
Several complex instructions take more than one cycle time. Complex
instuetions implement in hardware not by separate hardwired logic circuits
for each instruction but by a microprogram contol circuit}
4. ‘Special bit manipulation instructions.
5. A program counter, in which the inal default reset value defined by the
processor is 00000,
6. A stack pointer, in which the inital defaut value defined by the processors
0x07.
2
2,
13.
(ase)
Fig. 218051 Architecture
{A simple architecture, with n0 floating-point processor, no cache, no memory management unit mo
‘atomie operations uit, no pipeline and no instruction level parallelism, (Sections 2.3 and 2S). There
jis no DMA controle (Section 4.8) in the classic and mast other versions.
'A Harvard memory achitectre(Setion 242). The program memery and data memory have separate
‘adress spaces from 0x0000 ad separate control signals).
(On-chip RAM of [28 bytes. The B052 version provides for RAM of 256 bytes; 32 bytes of RAM are
sso used as four bank (ets of registers. Each estr-set (bank) thus has eight registers. The external
datafstack memory canbe add upto 64 KB in most versions In cetain 8051 enhancements this iit
has been enhanced to 16 MB.
‘There ae special function registers (SFR). These are PSW (processor stats word), A (accumulator),
B tepiser, SP (stack pointer) and resisters for serial 10s, times, pots and interrupt hander.
8351 version has on-chip ROM; 8751 version EPROM; 8951 version has on-chip EEPROM or flash
‘memory of 4 KB. Several versions provide fr higher capacity ROM. Additional program memory can
be added extemally upto 64 KB. In extended 8051 and unified address space versions (8051 EX and
[MK versions) this limit hasbeen extended to 16 MB.
‘Two extemal interrupt pis, INTO and INTI
Four pots PO, P].P2 3p P3 of 8 its each in single chip mode. Section 2.1.3) Thee are two timers
(Section 2.15) anda serial interface (SD. Itcan be programmed fr three fll duplex UARTT modes for
‘serial TO. [JO with each bit ofa word successive transmitted onthe data ine fr atime interval} The
‘Sl can also be programmed fo half duplex synchronous 10 (Section 2.1.6).tc Embodsed Systems
114 Classic version has no pulse widlh modulate ad prs on support v9 DAC. (Seetion 1.3.7) thas
no modem, 0 watchdog timer, 0 ADC. Ceraia vrion spon witchog timer and ADC. Siemens
SAB 80535-Nsuppors ADC with programmable