Fifth Semester B.Tech.

Degree Examination,November 2013

(2008 Scheme)
08.505 : MICROPROCESSORS AND INTERFACING (R)

Time: 3 Hours

Max.Marks : 100

PART-A
Answer all questions. Each question carries 4 marks.
1. Draw the timings diagram and explain how data byte is transferred from memory to MPU.

The data byte is transferred from memory to MPU is done during a Memory Read Cycle. The memory
read cycle consists of three T-states. During the first T-state, the address of the data byte that has to be
transferred from the memory to the CPU is sent from the processor through the Address lines (AD0
AD7 and A8 A15) to the Memory. ALE (Address Latch Enable) is high during the first T-state as
address is being transmitted. The higher order 8 bits of the address stays in the address lines till the third

T-state. In the beginning of the second T-state, the address reaches the memory and searches for the
specific memory location and retrieves data from that location. During that time, the data lines and
address lines contains no information. The data from memory is provided to the data bus and it travels to
MPU during the second and third T-state. By the end of the third T-state, the data will be inside the MPU.
While the data is being read in state T2 and T3, the RD signal should be active.
2. Explain how the port address of a memory mapped I/O can be recognized.
There are two ways of interfacing the I/O devices in 8085 based system. They are Memory mapped I/O
devices and I/O mapped I/O devices. In memory mapped I/O devices the ports are allotted a 16 bit
address like that of a memory location. The processor treats the I/O ports as memory locations for reading
and writing, which means the I/O devices which are mapped by memory mapping are accessed by
executing memory read cycle and memory write cycle.
3. Explain IN and OUT instructions for 8085 microprocessor.
IN and OUT instructions are used for the data from I/O devices.
IN Addr8

(A)

(Addr8)

The content of the port is moved to the A register. The 8 bit port address is given in the instruction. No
flags are affected while executing the instruction. It is a two byte instruction, one byte for the opcode and
one byte for the port address. This instruction comes under direct addressing mode. It consists of three
machine cycles Opcode fetch, Memory read, and I/O read.
OUT Addr8

(Addr8)

(A)

The content of the A register is moved to the port. The 8 bit port address is given in the instruction. No
flags are affected while executing the instruction. It is a two byte instruction, one byte for the opcode and
one byte for the port address. This instruction comes under direct addressing mode. It consists of three
machine cycles Opcode fetch, Memory read, and I/O write.
4. Explain the basic circuit of a DAC and define the terms resolution and setting time.
5. Explain the memory banks in 8086 microprocessor with neat schematics.
The 8086 memory address space can be viewed as a sequence of one million bytes in which any byte may
contain an 8-bit data element and any two consecutive bytes may contain a 16-bit data element. The
address space is physically connected to a 16-bit data bus by dividing the address space into two 8-bit
banks of up to 512K bytes each.
One bank is connected to the lower half of the 16-bit data bus (D0 D7) and contains even address bytes.
i.e., when A0 bit is low, the bank is selected. The other bank is connected to the upper half of the data bus
(D8 - D15) and contains odd address bytes. i.e., when A0 is high and BHE (Bus High Enable) is low, the
odd bank is selected. A specific byte within each bank is selected by address lines A1-A19.

Data can be accessed from the memory in four different ways. They are:
8 - bit data from Lower (Even) address Bank.
o To access memory bytes from Even address, information is transferred over the lower
half of the data bus (D0 - D7). The A0 is output LOW and BHE is output HIGH enabling
only the even address bank.
8 - bit data from Higher (Odd) address Bank.
o To access memory byte from an odd address, information is transferred over the higher
half of the data bus (D8 - D15). The BHE output low enables the upper memory bank. A0
is output high to disable the lower memory bank.
16 - bit data starting from Even Address.
o 16-bit data from an even address is accessed in a single bus cycle. Address lines A1 - A19
select the appropriate byte within each bank. A0 low and BHE low enable both banks
simultaneously.
16 - bit data starting from Odd Address.
o A 16-bits word located at an odd address (two consecutive bytes with the least significant
byte at an odd byte address) is accessed using two bus cycles. During the first bus cycle
the lower byte is accessed. During the second bus cycle, the upper byte with the even
address is accessed. During the first bus cycle, A1 - A19 address bus specifies the address
and A0 as 1 and BHE is low. Therefore the even memory bank is disabled and odd
memory bank is enabled. During the second bus cycle, the address is incremented.
Therefore A0 is zero and BHE is made high. The even memory bank is enabled and the
odd memory bank is disabled.
6. Explain the different segment register in 8086 microprocessor.

7. Explain the use of control signal and s0 in maximum mode of operation in 8086 microprocessor.
The status codes (S0,S1,S2) of the CPU is used by the bus controller to activate maximum mode
memory control signals.
These signals are required by the Intel 8288 bus controller to generate all memory and I/O access
control signals. The below table shows the encoding of these signals.

8. How is the INTR pin enabled in the strobed input mode of operation of 8255 ?
INTR(Interrupt request) is enabled when the STB(Strobe) input returns to a
logic 1, and is cleared when the data are input from the port by the
microprocessor.
9. How many wait states are required to interface the 8279 to 8086 microprocessor.
Two wait states
10. What is a memory to memory DMA transfer?
A memory to memory DMA transfer is used to perform the transfer of a block of data from one
set of memory address to another one
A memory-to-memory DMA transfer is a two cycle operation, and requires a read-from and a
write-to memory cycle to complete each DMA transfer. Each of these two types of cycles,
requires four states for its completion. A total 8 states maybe required for a single memory-tomemory DMA transfer.
(10

4=40 Marks
PART B
Answer any one question from each Module. Each question carries 20 marks.

Module-1
11. Draw the timing diagram and explain the execution of the instructions.
i) MVI A, 32H

ii) IN 01H.

12. Explain the interfacing of a 8 bit ADC (0801) with 8085 with neat schematics and timing diagram.
The Fig.1 shows the interfacing circuit of ADC 0801 and 8085. The ADC 0801 is a 8-bit
successive-approximation AID converter. It has input voltage range from 0 to 5v and it operates
with a single power supply of +5v. It has two inputs VIN(+) and VIN(-) for differential input. For
Single ended input, input is applied to VIN(+) and VIN(-) is grounded. The ADC requires the
clock signal in the range of 100kHz to 800kHz. We can either connect the external CLK IN pin or
we can built the internal clock by connecting a resistor and a capacitor externally, at pins 19 and
4, respectively.
The clock frequency is given by
F =

1
--------1.1 RC

Module-II
13.Draw the internal block diagram of 8086 and explain. Compare it with 8085 microprocessor.

14. a) Write a program in 8086 assembly language to find the average of the even numbers in a group of
n numbers.
.MODEL SMALL
.DATA
VAL1 DB
?
NL1
DB
0AH,0DH,'ENTER HOW MANY NO U WANT:','$'
NL2
DB
0AH,0DH,'ENTER NO:','$'
NL3
DB
0AH,0DH,'AVEARGE:','$'
.CODE
MAIN PROC
MOV AX,@DATA
MOV DS,AX
LEA DX,NL1
MOV AH,09H
INT 21H

MOV AH,01H
INT 21H
SUB AL,30H
MOV
MOV
MOV
MOV

CL,AL
BL,AL
AL,00
VAL1,AL

LBL1:
LEA DX,NL2
MOV AH,09H
INT 21H
MOV AH,01H
INT 21H
SUB AL,30H
ADD AL,VAL1
MOV VAL1,AL
LOOP LBL1
LBL2:
LEA DX,NL3
MOV AH,09H
INT 21H
MOV AX,00
MOV AL,VAL1
DIV BL
ADD AX,3030H
MOV DX,AX
MOV AH,02H
INT 21H
MOV AH,4CH
INT 21H
MAIN ENDP
END
MAIN
b) Write a note on interrupt in 8086 processor.

An interrupt is the method of processing the microprocessor by peripheral device. An interrupt is

used to cause a temporary halt in the execution of program. Microprocessor responds to the
interrupt with an interrupt service routine, which is short program or subroutine that instructs the
microprocessor on how to handle the interrupt.
An 8086 interrupt can come from any of the 3 sources:
1 By External Signal An 8086 can get interrupt from an external signal applied to the
nonmaskable interrupt (NMI) input pin, or the interrupt (INTR) input pin.
2 By Special Instructions 8086 supports a special instruction, INT to execute special program.
At the end of the interrupt service routine, execution is usually returned to the interrupted program
3 By Condition Produced by Instruction An 8086 is interrupted by some condition produced
in the 8086 by the execution of an instruction. For example divide by zero: Program execution will
automatically be interrupted if you attempt to divide an operand by zero.

Module-III
15. Draw the internal block diagram of 8254 and explain the interfacing of 8254 with 8086.

16. Draw the internal block diagram of 8237 and explain the interfacing of 8237 with 8086.