Integration of Carbon Nanotubes with

Semiconductor Technology; Fabrication of Hybrid

Devices by III-V Molecular Beam Epitaxy
S Stobbe1 , P E Lindelof1,2 , J Nyg
ard1,2
1

Hytronics Aps, Universitetsparken 5, DK-2100 Copenhagen

Niels Bohr Institute and Nano-Science Center, Universitetsparken 5,
DK-2100 Copenhagen
2

E-mail: nygard@nbi.dk
Abstract. We review a number of essential issues regarding the integration
of carbon nanotubes in semiconductor devices for electronics: Material
compatibility, electrical contacts, functionalities, circuit architectures and
reliability. In the second part of the paper, we present our own recent results on
incorporation of single-wall nanotubes in III-V semiconductor heterostructures
grown by molecular beam epitaxy (MBE). We demonstrate that singlewall
carbon nanotubes can be overgrown using MBE and electrical contacts to the
nanotubes are obtained by GaMnAs grown at 250 C. The resulting devices
can exhibit field effect action at room temperature.

PACS numbers: 72.80.Ey, 73.63.Fg, 85.65.+h

Submitted to: Semicond. Sci. Technol.

Present address:
Denmark

COMDTU, Technical University of Denmark, DK-2800 Kgs.

Lyngby,

Integration of Carbon Nanotubes with Semiconductor Technology

I. Introduction
It is well documented that carbon nanotubes (CNTs) have excellent electrical
properties both as metals and semiconductors. They can act as one-dimensional
ballistic conductors at room temperature as well as field-effect transistors (FETs)
with performance comparable to that of silicon FETs. 1,2,3 Basic logic circuits have
been formed by coupling such devices 4,5,6 . Moreover, nanotubes have extraordinary
mechanical strength and high thermal conductivity. Recently, new functionalities of
nanotube devices have been demonstrated experimentally, e.g. gate-controlled IR
electroluminescence from FETs 7,8 and singlewall carbon nanotubes are outstanding
candidates for novel electronic applications.
In addition to the performance of individual nanotube devices, however, one
must consider also a number of critical issues regarding the integration of nanotubes
with existing semiconductor technology.
In the first part of this paper (section II) we raise a number of such questions
and point out recent work addressing these issues. We focus on the possibilities
for incorporation of nanotubes in hybrid structures with existing semiconductor
technology rather than truly molecular electronics which we believe is further out
in the future.
In the second part of the paper (section III) we describe our own experiments
on integration of nanotubes with semiconductors by epitaxial encapsulation using
the MBE technique.
II. Integration of nanotubes with semiconductors - a review
In this section we review a number of essential issues concerning the possibilities
for integrating carbon nanotubes with semiconductor technology. It is commonly
known that the continuous down-scaling of CMOS technology will meet serious
challenges within the coming decade, and carbon nanotubes are considered
attractive candidates for solving a number of these challenges. However, it is clear
that although the down-scaling inevitably will saturate, CMOS technology will not
be discarded within the foreseeable future. The more realistic approaches will be
schemes for integration of nanotubes with contemporary technology for enhanced
performance of specific components 9 .
Such integration is presently unfeasible due to a number of unsolved critical
issues, and in this section we review a number of these. Certain aspects of nanotubes
in the context of the semiconductor roadmap have previously been considered by
other authors 2 .
1. Material compatibility
Generally, nanotubes can be introduced in semiconductor devices in two ways, (1)
either by depositing previously grown nanotube material from a liquid suspension or
by transfering from a solid source 10 or (2) the nanotubes may be grown in location
by Chemical Vapour Deposition (CVD) 11 . While deposition from a liquid may
be combined with surface chemistry to attach pre-treated or selected nanotubes to
specific areas of the chip, the latter technique allows for direct growth of nanotubes
at the desired location determined by lithographically defined catalyst patterns
without futher treatment of the CNTs. For mass production, accurate control of
these methods will be crucial.
While nanotubes can withstand the conditions for growth or deposition of
metals and semiconductor material (see below), thermal CVD growth of nanotubes
at elevated temperatures (typically 700-1000 C) can be detrimental to an
underlying semiconductor structure. Progress has been made in growth at low

Integration of Carbon Nanotubes with Semiconductor Technology

ambient temperatures using resistive local heating 12 and by plasma enhanced CVD
(PE-CVD). CNTs have been grown directly on a range of CMOS compatible metal
underlayers which may subsequently act as electrodes 13,14 . In the case of multiwall
CNTs, it was found that the growth efficiency depended on incorporation of a thin
SiO2 layer between the metal and the catalyst material (Ni) 13 . The growth process
must thus be optimized to tailor the specific material on which the nanotubes are
formed. Singlewall nanotubes have successfully been grown by CVD at 875 C on
top of an NMOS integrated circuit which remained fully functional 14 . Mo layers
underneath the catalyst pads acted as electrodes to the nanotubes after growth.
Also, the nanotube growth is strongly dependent on the chemical composition of
the substrate 15 .
Conversely, it is also possible to introduce pre-made carbon nanotubes during
the growth of a semiconductor structure. In the second part of this paper, we
will show that nanotubes can be incorporated directly in a semiconductor matrix
grown by MBE 16 . This overgrowth is performed with III-V semiconductors, while
similar experiments have not been reported with the technologically interesting
silicon structures. Carbon nanotubes endure temperatures up to at least 700 C
and are therefore not only compatible with III-V growth, but also both MBE and
CVD epitaxial growth of Si and Ge.
Fabrication of semiconductor devices involves numerous processing steps,
including metallization, oxide deposition, lithography and etching. Metal electrodes
can be evaporated onto the nanotubes and dielectric layers can also be deposited,
e.g. for use in high performance FETs 17,18 . The closed sp2 bonded carbon structure
of the nanotube surface makes them inert to most standard chemical reactants and
solvents used in processing. CNTs are not affected by exposure to UV or electron
beam lithography and moreover etchants such as hydrofluoric acid used for SiO2
removal does not harm the electronic properties of CNTs 19 . Conversely, nanotubes
can be oxidized and etched almost selectively by oxygen plasma treatments 20 which
is thus useful for removing CNTs from larger areas in combination with masking
by resist or solid material.
2. Electrical contacts
A conventional carbon nanotube device is typically based on a silicon substrate
with an SiO2 cap layer where nanotubes are grown or deposited and subsequently
contacted by metal electrodes using a lift-off technique. The Si substrate is heavily
doped to act as a uniform back-gate. A range of different electrode materials
have been tested and all regimes from tunnel barriers to transparent contacts
(e.g. using Pd films) have been fabricated 21,22,23,24 . For special applications, the
nanotubes can even be contacted with superconducting or ferromagnetic electrodes.
For local gating, the tubes can be covered by a dielectric (such as SiO2 or high gate dielectrics 3,17,21 ) onto which additional top or finger gates are defined by
lithography 18 . Only few studies have departed from these approaches.
Nanotube quantum dots have been fabricated on top of two-dimensional
electron gasses (2DEG) formed in a GaAs/AlGaAs heterostructure. The 2DEG
acted as a back-gate and it was shown that a split gate quantum point contact
defined on the 2DEG could control the gate action on the nanotube dot 25 .
Moreover, an increase in gate coupling was achieved due to the higher dielectric
constant of AlGaAs ( = 12). The depletable 2DEG back-gate approach can be
used to switch the coupling between multiple CNT quantum dots on and off as would
be required for quantum dot qubits in quantum information processing. Another
interesting device would be the combination of a CNT device with the high electron
mobility transistor (HEMT) based on the 2DEG 25 .
Since nanotubes are one-dimensional conductors, their contact resistance when

Integration of Carbon Nanotubes with Semiconductor Technology

coupling to electronically two- or three-dimensional contacts will however exceed

h/4e2 6k (for a singlewall CNT), which means that there is a fundamental
mismatch with the 50 impedance standard for current semiconductor circuits and
this may potentially become a problem for applications.
Fabrication of nanotube devices on top of piezoelectric substrates have
permitted charge transport in nanotube channels mediated by surface acoustic
waves (SAW). The SAWs were generated by lithographically defined microwave
transducers on LiNbO3 26 or quartz 27 substrates. Prospects for single-electron
pumping in nanotubes by this approach seem realistic.
For the integration of nanotubes with silicon MOS circuits the electrical
contacts between the CNTs and the semiconductor substrate circuit was achieved
through Mo metal pads on top of the integrated circuit 14 , which was completed
before nanotube growth on top.
In the above studies, nanotubes were still contacted by conventional metal thin
film electrodes formed by lithography. Another approach in hybrid electronics would
be to incorporate the nanotubes directly into a host crystal by (epitaxial) overgrowth
during the semiconductor fabrication procedure. Successful incorporation of
nanotubes inside semiconductor materials opens possibilities for direct coupling
to bandgap engineered structures such as quantum wells or optical cavities
for optoelectronics.
We have successfully integrated nanotubes with III-V
semiconductors by MBE 16 . Details on recent progress in this direction will be
given below in section III, where reliability experiments on GaMnAs contacts to
nanotubes are described.
3. Functionalities
The most celebrated nanotube component in the context of electronics applications
is the field-effect transistor based on semiconducting nanotubes 28 . It has been
demonstrated for that individual tube devices, performance exceeding that of
present silicon technology can be achieved; transport can be ballistic and high
current densities can be achieved 22,29 . Carbon nanotubes can furthermore be
combined with most gate oxides, including exotic, thin high- dielectric layers
which can be formed by atomic layer deposition 17 . In state-of-the-art devices
transconductances around 104S/m and subthreshold swings above 100 mV/dec
have been demonstrated. For a schematic comparison between various NT and Si
FETs, see e.g. Graham (2005) 2 .
Depending on the choice of contact material and device geometry the devices
may act as genuine FETs or Schottky barrier transistors, respectively. While
the first approach allow for the highest max currents, the latter holds other
interesting prospects. For instance, gate controlled IR emission from electron-hole
recombination have been obtained in ambipolar nanotube transistor when biased
appropriately 7 . In a numbers of works, several nanotube FETs have been coupled
to form basic logic circuits 4,5,17 .
Clearly, all the above devices relies on the ability to separate semiconducting
nanotubes from metallic ones. No convincing selective growth method has been
reported and this remains as a major challenge in nanotube synthesis. Separation
must thus be performed after growth. Some progress have been made in chemical
separation of the various tube species 30 , but such procedures warrant elaborate
treatment of the materials and precludes on chip growth of nanotubes at the desired
locations. Partially selective attachments of semiconducting tubes to electrode
arrays by dielectrophoresis have been reported 31 .
A critical component in a current semiconductor IC is the vertical interconnect,
the via.
These metallic wires are prone to degradation by heating and
electromigration. The capabilities for carrying high current densities in nanotubes 24

Integration of Carbon Nanotubes with Semiconductor Technology

make these interesting alternatives for the present technology. For this application,
the mixture between semiconducting and metallic shells in multiwall nanotubes or
in bundles of singlewall tubes is not a significant problem. Such parallel connections
of several NTs are needed to reduce the total resistance below lower limit of 6.5k
per tube. For instance, experiments have been made with vias obtained by local
growth of individual multiwall nanotubes in holes formed in dielectrical layers by
electron beam lithography or ion beam milling 2 .
Since the excellent performance of all-nanotube components have been reviewed
in numerous earlier reviews 1,2,3,32 , they will not be recapitulated further here.
4. Circuit architectures
While individual CNT devices shows excellent electronic performance, connecting
several, let alone thousands, such devices into functional integrated circuits is a
major challenge. It is difficult to position individual tubes at desired locations with
high yield. Moreover the distribution of tubes with different electrical properties in
typical samples is a further complication.
It has been proven possible to selectively remove the metallic tubes in devices by
electrical breakdown while the semicondcuting tube FETs are turned off by a gate
voltage 33 and this has been used to create nanotube power-FETs 34 It is however
unclear how this procedure can be realized for more complex circuits consisting of
several interconnected tube devices and highly integrated circuits based solely on
e.g. CNT transistors still represent a distant goal.
It seems more promising to aim at incorporating CNT elements only where
they add improved performance or new functionality to integrated circuits, e.g. for
chemical/biochemical sensors 35,36 , sensor arrays 14 , few-electron memories 37,38 or
spintronics components 39 .
We note that there is progress on assembling nanotube structures using
chemical or biochemical methods 40,41 . Utilizing these techniques in commercial
electronics would however call for novel fabrication schemes, but it may in turn pave
the way for large scale manufacture of self-assembled integrated circuits, where the
CNTs are directed to specific locations. Similarly, such methods may be used to
incorporate metallic CNTs into circuits as passive leads to nanoscale elements such
as functional molecules or nanoparticles 20,42 .
Finally, nanotubes may play other roles than electronic components in ICs; for
instance their stability and high thermal conductivity 43 holds prospects for heat
removal by integration in heat sinking elements.
5. Reliability
As pointed out already in the previous sections, the lack of nanotube uniformity
in as-grown nanotube material is hindering reproducible fabrication in many
applications since the nanotube bandstructure (metals, large or small gap
semiconductors) translates directly into device characteristics.
In certain
components such as parallel channel vias and power FETs this problem is
circumvented, but for individual CNT devices the problem is severe.
Another important aspect is the variability of contacts between bulk (metal)
electrodes and CNTs. The contacts vary between different metals and can in some
cases be improved by proper annealing steps 44,23 . However, the molecular nature
of CNTs inherently imply that the contacts are nearly atomic and thus may be very
sensitive to minute changes or perturbations.
To be of any interest in commercial applications the expected lifetime of the
components must at least be on the order of years. Failures may be provoked
by either abrupt events such as electrostatic discharge or by degradation due

Integration of Carbon Nanotubes with Semiconductor Technology

Figure 1. Schematic illustrations of the three device types fabricated. In all

cases CNTs were overgrown by GaMnAs. In devices of type A, a two-terminal
configuration was defined by UV-lithography and wet-etching. Devices of
type B and C were fabricated similarly, but extended with a top-gate for the
former and a superlattice (SL) back-gate for the latter to facilitate field-effect
transistor operation.

to extended operation of the components, for instance at high temperatures or

in a harmful environment. A number of standardized test schemes exist in
the semiconductor industry e.g. under the JEDEC JESD47D standard 45 , but
benchmarking of nanotube devices against such standards is presently very rarely
seen in the open literature.
Whereas protection against abrupt events depends of the specific device design,
some general considerations regarding long-time operation of nanotube components
may be made. Carbon nanotubes as such have been proven to be very durable in
ambient conditions, at elevated temperatures and in various chemical environments.
One may expect that failures most likely will be due to degradation of the interfaces
between nanotubes and the host semiconductor structures. The properties of the
contacts can change upon fluctuations in temperature or even by electromigration
in the case of atomic scale contacts and moderate currents.
III. Experimental results on epitaxial hybrid CNT/III-V semiconductor
devices
In the previous section we reviewed the multitude of approaches towards hybrid
nanotube/semiconductor devices. The majority of these techniques involve device

Integration of Carbon Nanotubes with Semiconductor Technology

processing steps which are incompatible with present CMOS fabrication technology,
and they do not consider nanotube integration within the semiconductor, but rather
on top of it. This means that nanotube deposition or growth must take place on
the surface of a finalized semiconductor device, which puts a severe limitation to
the possible applications.
We believe that there is a potential for applications of hybrid semiconductor/nanotube devices, where the nanotubes are be fully encapsulated within the
semiconductor by means of epitaxial growth 16,46 , thus providing a novel hybrid
material.
The application of MBE-grown Mn-doped GaAs, GaMnAs, for regrowth on
nanotubes has previously been investigated due to the ferromagnetic properties
of this p-type semiconductor at low temperatures 47 . Here we investigate the
applicability of this material system to room temperature operation of hybrid
nanotube/semiconductor devices. In the following we present a fabrication scheme
for such devices as well as experiments on high temperature operating life (HTOL)
testing, and a proof-of-principle demonstration of field-effect in such a hybrid device.
1. Device fabrication
Three types of hybrid CNT/semiconductor devices were investigated, as shown
in figure 1. For devices of type A, single wall carbon nanotube bundles were
dissolved in 1,2-dichlorethane using ultrasonication and the suspension was spincoated on an undoped GaAs (100) substrate. Then the substrate was transferred
to a III-V molecular beam epitaxy (MBE) reactor where 50 nm Ga97% Mn3% As was
epitaxially grown at 250 C. Since the GaMnAs contacts are magnetic, pronounced
magnetoresistance effects can be observed at low temperatures 47 , but here we focus
exclusively on the properties at or above room temperature, where we utilize the
high doping rates possible with this material. For a discussion of the properties
of GaMnAs, see e.g. 48 . During this crystal growth, the quality of the film was
inspected by reflection high energy electron diffraction (RHEED) which confirmed
the two-dimensional growth conditions of the film. In order to electrically isolate
the contact areas of the Ga97% Mn3% As and create CNT bridges, mesa structures
were defined by standard UV-lithography (UVL). In a final step, Cr/Au bonding
pads were defined using a lift-off technique.
The devices of type B were all fabricated like the type A devices, except that
for type B, the CNT bridge was covered with a 2.1m thick photoresist layer
defined by UVL, which upon hard-baking formed a chemically and mechanically
stable dielectric insulator. Finally another Cr/Au layer was deposited on top of
the insulator, thus providing a top-gate for field-effect transistor operation. The
devices of type C were designed for back-gated operation and made by a two-step
MBE growth as described elsewhere 16 . This structure is fundamentally different
from that of type B, in that the superlattice barrier in type C limits leakage currents
by band-offsets as determined by the semiconductor band-structure.
2. High temperature operating life tests
As discussed above, a key parameter to address for CNT applications in
microelectronics is the the time and temperature stability. Here we present the
first HTOL tests on hybrid CNT-III-V semiconductor devices. The devices were
fabricated as those of type A discussed in the previous section and wire-bonded to
suitable chip carriers.
Since GaMnAs layers can only be grown at low temperatures (250 C), it is
common to perform an annealing of the GaMnAs film before measurements 49 . Here,
13 samples were annealed at 125 C for 110 h prior to the HTOL tests.

Integration of Carbon Nanotubes with Semiconductor Technology

Figure 2. Representative topographic AFM picture showing a 3 nm CNT

bridging a 1.4 m gap in a GaMnAs mesa. The contrast is reduced because the
wet etching of the GaMnAs mesa yields a rough surface below the CNT. This
makes it impossible to distinguish between CNT bundles and single CNTs.

Figure 3. The relative resistance change as a function of initial resistance for

13 devices of type A before and after high temperature operating life (HTOL)
testing. A correlation is observed, which shows that the devices with the lower
contact resistance are also the most stable during HTOL.

Figure 4. Device conductances for 20 samples of type A as a function of

the number of bridging CNTs as observed by AFM. Since the total device
conductance scales with the number of bridging CNTs, this confirms that CNTs
are indeed the current carrying channels.

Integration of Carbon Nanotubes with Semiconductor Technology

The HTOL measurement procedure was as follows: For each individual device
I-V traces were measured and then all 13 devices were connected in a series
configuration and 8 V DC was applied. This gave a current response of 1.4 A. Then
they were loaded in the preheated oven at 125 C. After the device temperature had
saturated, the current stabilized at 3.8 A. This point of time was designated t=0
and the HTOL test began. After 100 hours, the devices were taken out of the oven
and cooled to room temperature. Finally, the individual IV traces were remeasured.
The result for all 13 samples is shown in figure 3, where the relative resistance
change is plotted as a function of initial resistance. From the clear correlation, one
can infer that the higher initial resistance, the lesser stability during HTOL testing.
CNTs are known to be very chemically stable, so we speculate that the fluctuations
in device resistance is primarily due to contact resistance instabilities as opposed to
fluctuations in the CNTs. The contact resistance may depend on the actual atomic
arrangement at the CNT-semiconductor interface, and may be particularly sensitive
for high resistance contacts.
To further support this, we scanned the CNT gap using topographic atomic
force microscopy (AFM). This test was done on 20 samples of type A from the
same batch as the 13 samples discussed above. We used the AFM scan to count the
number of CNTs connecting the mesa islands and correlated this with the device
conductance at room temperature. The results is shown in figure 4. This confirms
that CNTs are indeed the current carrying channels in the devices as opposed to
defects or leakage paths. Also, for resistances less than 1 M, CNTs were always
observed, indicating that only samples with a resistance less than 1 M should be
considered as proper nanotube devices in this study. We note that although the
height of the CNTs as measured by topographic atomic force microscopy was found
to be on the order of a few nm as inferred from figure 2, this does not enable us to
distinguish between CNTs and small bundles of CNTs and we use the term CNT
with this reservation in mind.
Finally, after succesfully finishing the HTOL measurements on the 13 samples,
six of them were exposed to oxygen plasma ashering for 6s, which destroys the
electrical properties of CNTs but renders the host semiconductor unaffected. The
resistance was found to increase by several orders of magnitude (data not shown),
which is yet another strong evidence that the conducting paths are comprised of
CNTs.
3. Field effect operation
We fabricated a number of samples of type B and C, and investigated the field
effect properties of these devices. For devices of type C, significant problems
with self-gating (a field-effect in the barrier itself) obscured the results (data not
shown). It is clear that this is a general problem which must be addressed for CNTsemiconductor hybrid transistor devices, because of the background field effect in
the host semiconductor material. For devices of type B, this problem was much less
pronounced, presumably due to screening by the high density hole gas in the highly
Mn-doped GaMnAs cap layer.
The field effect operation at room temperature of such a device is shown in
figure 5. The relative resistance change is 6% over 20V gate voltage. The poor
transconductance is clearly related to the high thickness and low of the photoresist
insulator film, and also the mesa/gate geometry holds room for improvement 50 .
However, here we focus on the proof-of-concept for field-effect operation of this
novel structure, and this measurement is the first demonstration of a epitaxial
hybrid CNT/III-V semiconductor device showing field effect at room temperature.
The sample yield for the devices of type B was found to be less than 1%, which
obviously is far too low for applications. The yield is limited by the fact that at high

Integration of Carbon Nanotubes with Semiconductor Technology

10

Figure 5. Channel resistance as function of gate voltage (large open squares).

The observed field effect corresponds to a relative resistance change of 6% over
a 20V top-gate voltage range. The leakage current for the same device (small
closed squares), demonstrates the high resistance of the dielectric barrier. The
apparent correlation between leakage current and field effect is coincidential,
which was also confirmed by control samples with metallic CNTs which had
similar leakage current characteristics and source-drain resistances but no fieldeffect (data not shown).

nanotube densities, the probability that several tubes will connect the source and
drain increases, and since a fraction of these will be metallic, the metallic ones will
dominate the device behavior. However, the yield could be significantly increased
e.g. by using a much higher nanotube density in combination with high bias burning
of the metallic tubes, leaving only the semiconducting nanotubes behind 33 .
We note that no detailed modelling of the nanotube-semiconductor hybrid
material exists. In one case the electronic structure of nanotubes embedded in a
general crystalline matrix has been considered 51 . Here it was argued that the CNT
band structure would be strongly perturbed and that for semiconducting nanotubes,
a metallic state would result from the coupling to the host. In a different study,
nanotubes lying on a planar InAs surface were considered 52 . Also here interactions
between the NT and the substrate were found to perturb the electronic properties
of the tubes significantly.
IV. Conclusions
In conclusion, we have pointed out a number of challenges for hybrid
semiconductor/nanotube structures and reviewed recent results and progress in this
field.
Experimentally, we have studied a particular approach using regrowth of
GaMnAs on nanotubes pre-deposited on GaAs substrates. Two-terminal hybrid
devices were fabricated and used for studying the HTOL performance. Our results
indicate that long-term stability may not be a problem for certain applications,
but we note that the molecular dimensions of nanotubes makes stable contacts a
delicate issue.
We use a photoresist dielectric barrier to electrically isolate a top-gate from the
nanotube and to provide a proof-of-principle for a hybrid transistor. We find that
the field-effect operation is possible, but the device performance is poor compared to
other geometries. Improvements by orders of magnitude will be possible by simple
optimization of the gate dielectric.
Also back-gated devices were investigated, but further work is needed to
demonstrate this principle. We note that this heterostructure back-gate design has

REFERENCES

11

been shown to function at cryogenic temperatures, where transport is dominated

by Coulomb blockade of the CNT segment between the contacts, turning the device
into a single-electron transistor 16 .
The next step following this proof-of-principle study is to export the techniques
from the GaAs/GaMnAs system to Si, which is both much more technologically
interesting and better understood than GaMnAs. Since only a minority of
contemporary microelectronics is based on heterostructures, the possible integration
of nanotubes with silicon-on-insulator (SOI) substrates may be a technologically
interesting approach.
Acknowledgments
We gratefully thank M. Adell and J. Kanski for MBE growth and J.R. Hauptman,
C.B. Srensen, A. Jensen, C.J. Mahon and J. Hanberg for valuable discussions.
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