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10.
library ieee;
use ieee.std_logic_1164.all;
entity multiplier_2_bit is
port(a: in bit_vector(1 downto 0);b: in bit_vector(1 downto 0);
d: out bit_vector(3 downto 0));
end multiplier_2_bit;
architecture multiplier_2_bit_dfm of multiplier_2_bit is
signal c: bit;
begin
d(0)<=(a(0) and b(0));
d(1)<=((a(1) and b(0)) xor (a(0) and b(1)));
c<=((a(1) and b(0)) and (a(0) and b(1)));
d(2)<=((a(1) and b(1)) xor c);
d(3)<=((a(1) and b(1)) and c);
end multiplier_2_bit_dfm;
11.
library ieee;
use ieee.std_logic_1164.all;
entity comparator_2_bit is
port(a,b: in bit_vector(1 downto 0); y: out bit_vector(2 downto 0));
end comparator_2_bit;
architecture comparator_2_bit_dfm of comparator_2_bit is
begin
y(0)<= (((a(1) and (not b(1))) or (a(1) and a(0) and (not b(0)))) or ((not b(1)) and a(0)
and (not b(0))));
y(1)<= ((((not a(1)) and b(1)) or ((not a(1)) and (not a(0)) and b(0))) or (b(1) and (not
a(0)) and a(0)));
y(2)<= ((a(1) xnor b(1)) and (a(0) xnor b(0)));
end comparator_2_bit_dfm;
12.
library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port(a,b: in bit; sum,carry: out bit);
end half_adder;
architecture half_adder_struct of half_adder is
component xor1 is
port(p,q: in bit; r: out bit);
end component;
component and1 is
port(u,v: in bit; w: out bit);
end component;
begin
x1:xor1 port map(a,b,sum);
x2:and1 port map(a,b,carry);
end half_adder_struct;
entity xor1 is
port(p,q: in bit; r: out bit);
end xor1;
architecture xor_1_dfm of xor1 is
begin
r<=p xor q;
end xor_1;
entity and1 is
port(u,v: in bit; w: out bit);
end and1;
architecture and_1_dfm of and1 is
begin
w<=u and v;
end and_1;
13.
VHDL Code For 4-bit Parallel Adder by Structural
Modelling
library ieee;
use ieee.std_logic_1164.all;
entity full_adder_4_bit is
port(a,b: in bit_vector(3 downto 0); carry_in: in bit;
sum: out bit_vector(3 downto 0); carry_out: out bit);
end;
architecture structural_4_bit_full_adder of full_adder_4_bit is
component full_adder
port(x,y,zin: in bit; s,c: out bit);
end component;
signal carry: bit_vector(4 downto 0);
begin
carry(0)<=carry_in;
GK:for i in 3 downto 0 generate
FA:full_adder port map(a(i),b(i),carry(i),sum(i),carry(i+1));
end generate GK;
carry_out<=carry(4);
end;
entity full_adder is
port(p,q,r:in bit; u,v:out bit);
end;
architecture data_flow_full_adder of full_adder is
begin
u<=((p xor q) xor r);
v<=((p and q) or (q and r) or (r and p));
end;
14.
VHDL Code For 4-Bit Parallel Subtractor by Structural
Modelling
library ieee;
use ieee.std_logic_1164.all;
entity full_subtractor_4_bit is
port(a,b: in bit_vector(3 downto 0); borrow_in: in bit;
difference: out bit_vector(3 downto 0); borrow_out: out bit);
end full_subtractor_4_bit;
architecture full_subtractor_4_bit_struct of full_subtractor_4_bit is
component full_subtractor is
port(x,y,zin: in bit; diff,zout: out bit);
end component;
signal borrow: bit_vector(4 downto 0);
begin
borrow(0)<=borrow_in;
GK: for i in 3 downto 0 generate
FS: full_subtractor port map(a(i),b(i),borrow(i),difference(i),borrow(i+1));
end generate GK;
borrow_out<=borrow(4);
end full_subtractor_4_bit_struct;
entity full_subtractor is
port(r,s,t: in bit; u,v: out bit);
end full_subtractor;
architecture full_subtractor_dfm of full_subtractor is
begin
u<=((r xor s) xor t);
v<=(((not r) and t) or ((s and t) or ((not r) and s)));
end full_subtractor_dfm;
15.
library ieee;
use ieee.std_logic_1164.all;
entity mux_4_1 is
port(s: in bit_vector(1 downto 0);d: in bit_vector(3 downto 0); y: out bit);
end;
architecture mux_4_1_dfm of mux_4_1 is
begin
y<=d(0) when s="00" else
d(1) when s="01" else
d(2) when s="10" else
d(3);
end;
16.
library ieee;
use ieee.std_logic_1164.all;
entity decoder_2_4 is
port(a: in bit_vector(0 to 1); d: out bit_vector(0 to 3));
end decoder_2_4;
architecture decoder_2_4_behavioural of decoder_2_4 is
begin
process(a)
begin
if a="00" then
d<="0001";
elsif a="01" then
d<="0010";
elsif a="10" then
d<="0100";
else
d<="1000";
end if;
end process;
end decoder_2_4_behavioural;