Documente Academic
Documente Profesional
Documente Cultură
FACULTY OF ENGINEERING
KE 26604
COMPUTER ARCHITECTURE AND
MICROPROCESSING (2014/15)
Computer Architecture &
Microprocessor
Tutorial 1
PREPARED BY:
Ramanan A/L Thangasalvam (BK13160570)
PREPARED FOR:
Lecturer: Assoc. Prof. Engr. Dr Ismail Saad
Lab Coordinator: Mr Chan Bun Seng
3)
Fetch instruction:
In the first step, the processor fetches the instruction from the memory. The
instruction is transferred from memory to instruction register.
In the following figure, the processor is ready to fetch instruction. The instruction
pointer contains the address 0100 contains the instruction MOV AX, 0.
The memory places the instruction on the data bus. The processor then copies
the instruction from the data bus to the instruction register.
Execute instruction:
In the last phase, the processor execute the instruction, it stores 0 in register AX.
In above figure, the processor execute the instruction MOV AX, 0. Finally it
adjusts the instruction pointer to point to next instruction to be executed stored
at address 0102.
In this step, the instruction is decoded by the processor. The processor gets any
operand if required by the instruction. For example, the instruction MOV AX, 0.
Stores the value 0 in Ax register. The processor will fetch the constant value 0
from the next location in memory before executing the instruction.
In the above figure, the processor transfers the instruction from instruction
register to the decode unit. The instruction tells the computer to store 0 into AX
register. The decode unit now has all the details of how to do this.
4)
Instruction Cycle State diagram without interrupts:
The instruction cycle has three code segments that do not perform I/O. WRITE
calls the OS to perform an I/O Write. A code sequence then prepares for the I/O
transfer (check device status, copy data to buffer, etc.). The OS issues I/O
command and OS then has to wait and poll device status until I/O completes. An
example of post I/O processing is set status flag. The users program is
suspended until I/O complete
Instruction Cycle State diagram with interrupts:
The figure above shows processing with interrupts. The WRITE call again
transfers control to the OS. After write preparation, control returns to user
program. The I/O proceeds concurrently with user program. When I/O completes,
device issues an interrupt request. OS interrupts user program and executes post
I/O code.
The instruction cycle with interrupts is more effective compared to that without interrupts.
The reason interrupts are used are for the following reasons. The interrupt cycle is added to
the instruction cycle. Processor checks for interrupt which is then indicated by an interrupt
signal if present. If there is no interrupt, the next instruction is fetched. If interrupt is pending
the execution of current the program will be suspended. The interrupt cycle process occurs as
such, the context is saved, PC is set to start address of interrupt handler routine, process
interrupt occurs and restores context and continue interrupted program.
Interrupts remain pending and are checked after first interrupt has
been processed
7) Gordon Moore, the co-founder on Intel Corporation in 1975 stated a law knows
as the Moores Law which states that the number of transistor per square inch on
an integrated chip is to double every 18 months since its invention. This law has
become the heart of the development of the computer and processor and is
practiced in all semiconductor industries. In today's chips, a stretch of silicon
9)
(a) Maximum directly addressable memory capacity in bytes = 32 bit/8 bit
= 4 bytes
(b) (i) a 32-bit local address bus allows more space for data storage 2^32 4GB
space and a 16-bit local data bus allows a maximum of 4 byte of data to be
written to/read off from the memory at a time.
(ii) a 16-bit local address bus allows very less for data storage 2^16 64kB
space and a 16-bit local data bus allows a maximum of 4 byte of data to be
written to/read off from the memory at a time.
(c) The Program Counter (PC) requires 24 bits and the Instruction Register (IR)
required 32 bits.
10) The optimal code for the four machines for the given equation X=(A+B*C)/
(D-E*F) and instructions is as follows:
zero-address
one-address
two-address
three-address
PUSH A
LOAD E
MOV R0, E
MUL R0,E,F
PUSH B
MUL F
MUL R0,F
SUB R0,D,R0
PUSH C
STORE T
MOV R1,D
MUL R1,D,R0
Segmented mode
The mapping works within a segment
and
memory
numbers
where
any
offset
multitasking
rarely
enhanced
operations
with
additional
unless
memory
hardware/software
Used in the Linux
operates
in
the
compatible
segmented mode
Used in the X86 models of intel
Relocation
modules
of
in
this
separately-compiled
space
must
be
size
of
segment
is
variable;
(ii) The 386 microprocessor uses the segmented memory addressing mode
and has six
segment registers, code and stack both 64kb in size and (4x64kb) or
256kb for data.
Only these six segments can be addressed at any given time. Thus, the
total memory
that can be addressed at any given time is:
64kb + 64kb + 256kb = 384kb.
(iii) (a) for, 23FB:FAB3H
12) (i) Data Register general purpose register used as temporary data store
during execution
- examples: AL and AH registers = 8-bits
AX register = 16-bits
EAX register = 32-bits
(ii) Index and pointer register general purpose register used to hold the
offset of the
address of the data in memory
- examples: BP Base pointer (16-bits)
DI Destination Index (16-bits)
SP Stack pointer (16-bits)
(iii) Segment register each holds the base memory address of 64k memory
segment
- example: DS Data segment (16-bit)
CS Code segment (16-bit)
SS Stack segment (16-bit)
(iv) Flags register show the status of result stored in accumulator after
execution of an
instruction. First nine bits used in real mode, where first six
bits are
the status flags that states the change as result of
executing a certain
instruction and the following three bits are the control flags
that are
responsible for the control operation of the 386
microprocessor. Each
flag is 1-bit in size.
- example: CF carry flag
PF parity flag
IF interrupt enable flag