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Device Architectures
Overview
In 1985, Lattice Semiconductor introduced a new type of
programmable logic device (PLD) that transformed the
PLD market: the Generic Array Logic (GAL) device. The
E2CMOS technology of the GAL devices gave them
significant advantages over their bipolar PAL counterparts; not only could GAL devices be programmed quickly
and efficiently, but they could also be erased and reprogrammed. Today, Lattice is the leading supplier,
worldwide, of low-density PLDs. Industry leading performance, low power E2CMOS technology, 100% testability
and 100% programming yields make the GAL family the
preferred choice among system designers.
The GAL family includes fourteen distinct product architectures, with a variety of performance levels specified
across commercial, industrial, and military (MIL-STD883) operating ranges, to meet the demands of any
system logic design.
Lattice GAL products have the performance, architectural features, low power, and high quality to meet the
needs of the most demanding system designs.
introgal_02
vices are capable of emulating virtually all PAL architectures with full function/fuse map/parametric compatibility.
I/CLK
GAL20V8 Only
I
IMUX
CLK
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OLMC
E CMOS Programmable
AND Array
I
IMUX
I/OE
GAL20V8 Only
GAL20V8 Only
CLK
Vcc
Q
Q
XOR
XOR
OE
Vcc
XOR
XOR
XOR
ASYNC.
RESET
SYNC.
PRESET
I/CLK
I
I
I
I
I
I
I
OLMC
I/O/Q
I/O/Q
I/O/Q
1
2
I/O/Q
3
I/O/Q
4
I/O/Q
5
I/O/Q
6
I/O/Q
7
I/O/Q
8
I/O/Q
9
I/O/Q
10
GAL26CV12
GAL18V10 and
GAL22V10
PROGRAMMABLE
AND-ARRAY
GAL18V10
GAL22V10
GAL26CV12
I/O/Q
11
12
GAL22V10 family devices have a product term for Asynchronous Reset (AR) and a product term for Synchronous
Preset (SP). These two product terms are common to all
registered OLMCs.
A R
D
Q
CLK
4 TO 1
MUX
Q
SP
2 TO 1
MUX
AR
AR
CLK
CLK
SP
Q
SP
Active Low
Active High
Active Low
Active High
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(80X40)
OE
PL
AR
PD
D
AP
0
1
X O R (n )
PL
AR
PD
Q
AP
X O R (n )
OE
XOR (n)
When the macrocell is set to the Exclusive-OR Registered configuration, the four product terms are segmented
into two OR-sums of two product terms each, which are
then combined by an Exclusive-OR gate and fed into a Dtype register that is clocked by the low-to-high transition
of the I/CLK pin.
When the macrocell is set to Registered configuration,
three of the four product terms are used as sum-ofproduct terms for the D input of the register. The inverting
output buffer is enabled by the fourth product term. The
output is enabled while this product term is true. The XOR
bit controls the polarity of the output.
When the macrocell is set to the Exclusive-OR combinatorial configuration, the four product terms are segmented
into two OR-sums of two product terms each, which are
then combined by an Exclusive-OR gate and fed to an
output buffer.
4
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
I
4
Each OLMC has four possible logic function configurations: XOR Registered, Registered, XOR Combinatorial,
and Combinatorial. Four product terms are fed into each
macrocell.
PROGRAMMABLE
AND-ARRAY
(40 X 40)
I
4
I/OE
Registered Configuration
OE
XOR
Q
Q
CLK
CLK
Combinatorial Configuration
OE
XOR
I/CLK
I/CLK
I
I
I
CLK
IMUX
8
CLK
I/O/Q
OLMC
1
I
8
I/O/Q
OLMC
3
I/O/Q
OLMC
4
I/O/Q
OLMC
5
I/O/Q
OLMC
6
I
8
I
8
OE
OLMC
2
I/O/Q
OLMC
3
I/O/Q
OLMC
4
I/O/Q
OLMC
5
I/O/Q
OLMC
6
I/O/Q
OLMC
7
I/O/Q
OLMC
8
I/O/Q
I/O/Q
OLMC
8
I/O/Q
OLMC
7
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 40)
PROGRAMMABLE
AND-ARRAY
(64 X 32)
OLMC
1
I/O/Q
OLMC
2
I/OE
OE
10
IMUX
I
I/OE
The GAL16V8Z/ZD (20-pin) and GAL20V8Z/ZD (24pin), at 100uA standby current, provide the highest speed
and lowest power combination PLDs available in the
market. These devices are ideal for battery powered
systems.
The GAL16V8Z and 20V8Z use Input Transition Detection (ITD) to put the device in standby mode and are
capable of emulating the full functionality of the standard
GAL16V8Z/ZD Block Diagram
I/CLK
CLK
OLMC
1
I/O/Q
OLMC
2
I/O/Q
IMUX
CLK
I
8
I/O/Q
OLMC
4
I/O/Q
OLMC
5
I/O/Q
8 OLMC
2
I/O/Q
8 OLMC
3
I/O/Q
8 OLMC
4
I/O/Q
8 OLMC
5
I/O/Q
8 OLMC
6
I/O/Q
8 OLMC
7
I/O/Q
OLMC
8
I/O/Q
I/DPP
OLMC
3
OLMC
6
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 40)
PROGRAMMABLE
AND-ARRAY
(64 X 32)
I/DPP
I/O/Q
I
8
8 OLMC
1
OLMC
7
I/O/Q
OLMC
8
I/O/Q
I
I
8
I
OE
I/OE
OE
I
IMUX
I/OE
11
For the GAL6001, both the ILMC and the IOLMC are
block configurable; however, the ILMC can be configured
independently of the IOLMC. For the GAL6002, both the
ILMC and the IOLMC are individually configurable, and
the ILMC can be configured independently of the IOLMC.
ICLK
INPUT
CLOCK
14
11
23
ILMC
IOLMC
RESET
2
INPUTS
2-11
AND
OUTPUT
ENABLE
14
23
OLMC
E
OR
BLMC
{ OUTPUTS
14 - 23
OCLK
OUTPUT
CLOCK
12
13
RESET
I/CLK
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
12
PROGRAMMABLE
AND-ARRAY
(132X44)
I/O/Q
I/O/Q
Vcc
SCLK
I/CLK
OLMC
14
16
16
14
12
I/O/Q
10
OLMC
10
I
8
4
I
28
26
25
I
I
23
PRESET
Programming
Logic
I/O/Q
SDO
SDI
MODE
SCLK
SDO
9
21
I/O/Q
I/O/Q
11
I/O/Q
I/O/Q
SCLK
I/CLK
I
I
I
I
I
MODE
I
I
I
I
I
GND
I/O/Q
19
18
16
SDI
14
12
GND
I/O/Q
MODE
I
I/O/Q
28
22
14
15
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
SDI
14
November 1996