Appendix

Summary of the PIC18

Instruction Set

A-22

Appendix B

Summary of the PIC18 Instruction Set

B1. General Format for Instruction

15

10
opcode

0
f

d = 0 for result destination to be WREG register.

d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address

Figure 1.8

Byte-oriented file register operations (redraw with permission of Microchip)

15

12 11

opcode
15

f (source file register)

12 11

1111

f (destination file register)

f = 12-bit file register address

Figure 1.9

Byte to byte move operations (2 words) (redraw with permission of Microchip)

15

12

opcode

11

9
b

0
f

b = 3-bit position of bit in the file register (f).

a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address

Figure 1.10

Bit-oriented file register operations (redraw with permission of Microchip)

Appendix B

A-23

Summary of the PIC18 Instruction Set

15

opcode

0
k

k = 8-bit immediate value

Figure 1.11

Literal operations (redraw with permission of Microchip)

15

opcode

0
n<7:0> (literal)

15

8
1111

GOTO label

n<19:8> (literal)

n = 20-bit immediate value

15

8
opcode

15

8
1111

0
n<7:0> (literal)

CALL funct_name

n<19:8> (literal)

S = fast bit
15

11

10

opcode
15

8
opcode

Figure 1.12

n<10:0> (literal)

BRA func_name
0

n<7:0> (literal)

Control operations (redraw with permission of Microchip)

BC func_name

A-24

Appendix B

Summary of the PIC18 Instruction Set

B2. Summary of Instructions

Mnemonic,
Operand

Description

Cycles

Status
Affected

16-bit instruction
word

01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
11da
10da
10da
011a
10da

ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff

ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff

bbba
bbba
bbba
bbba
bbba

ffff
ffff
ffff
ffff
ffff

ffff
ffff
ffff
ffff
ffff

Byte-Oriented File Register Operands

ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF

f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd

Add WREG and f

Add WREG and carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
Decrement f
Decrement f, skip if 0
Decrement f, skip if not 0
Increment f
Increment f, skip if 0
Increment f, skip if not 0
Inclusive OR WREG with f
Move f
Move fs to fd

1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2

C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None

MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORWF

f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a

Move WREG to f
Multiply WREG with f
Negate f
Rotate left f through carry
Rotate left f (no carry)
Rotate right f through carry
Rotate right f (no carry)
Set f
Subtract from WREG with borrow
Subtract WREG from f
Subtract WREG from f with borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f

1
1
1
1
1
1
1
1
1
1
1
1
1 (2 or 3)
1

None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
C, DC, Z, OV, N
C, DC, Z, OV, N
None
None
Z, N

0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
0101
0101
0011
0110
0001

1
1
1 (2 or 3)
1 (2 or 3)
1

None
None
None
None
None

1001
1000
1011
1010
0111

Bit-Oriented File Register Operands

BCF
BSF
BTFSC
BTFSS
BTG

Table B1

f, b, a
f, b, a
f, b, a
f, b, a
f, d, a

Bit clear f
Bit set f
Bit test f, skip if clear
Bit test f, skip if set
Bit toggle

PIC18 Instruction set summary (redraw with permission of Microchip)

Appendix B

Mnemonic,
Operand

A-25

Summary of the PIC18 Instruction Set

Description

Cycles

Status
Affected

16-bit instruction
word

n
n
n
n
n
n
n
n
n
n, s

Branch if carry
Branch if negative
Branch if not carry
Branch if not negative
Branch if not overflow
Branch if not zero
Branch if overflow
Branch unconditionally
Branch if zero
Call subroutine

1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2

None
None
None
None
None
None
None
None
None
NOne

Clear watchdog timer

Decimal adjust WREG
Goto

1
1
2

TO, PD
C
None

No operation
No operation
Pop top of return address
Push top of return address
Relative call
Software device RESET
Return from interrupt enable
Return with literal in WREG
Return from subroutine
Go into standby mode

1
1
1
1
2
1
2
2
2
1

None
None
None
None
None
All
GIE/GIEH,PEIE
None
None
TO, PD

1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0000
0000
0000

0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
1100
0000
0000

nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
kkkk
0001
0000

nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
kkkk
001s
0011

Add literal and WREG

AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word to
FSRx 1st word
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG

1
1
1
2

C, DC, Z, OV, N
Z, N
Z, N
None

1
1
1
2
1
1

None
None
None
None
C, DC, Z, OV, N
Z, N

0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000

1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010

kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk

kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk

None
None
None
None
None
None
None
None

0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0000
0000

1000
1001
1010
1011
1100
1101
1110
1111

Control Operations
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP

n
s
k
s

Literal Operations
ADDLW
ANDLW
IORLW
LFSR

k
k
k
f, k

MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW

k
k
k
k
k
k

Data memory to and from Program memory Operations

TBLRD*
TBLRD*+
TBLRD*
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*
TBLWT+*

Table B1

Table read
Table read with post-increment
Table read with post-decrement
Table read with pre-increment
Table write
Table write with post-increment
Table write with post-decrement
Table write with pre-increment

(continued)

2 (5)