Vlsi Manual 2014

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IMPLEMENTATION OF COMBINATIONAL LOGIC CIRCUITS- HALF

ADDER, FULL ADDER AND 8 BIT ADDERS.
Ex No:
Date :
Aim:
To write a Verilog code and implement half adder, full adder and 8bit adder in Xilinx
Spartan 3E FPGA kit.
Tools Required:
Xilinx ISE 8.1, ModelSim SE 6.0
Procedure:
a) Open file menu from sub menu. Click open
b) Enter the project name and select HDL.
c) Select the device family.
d) Create a new source and enter HDL file name and also the module name.
e) Enter the input and the output variables.
f) Enter the coding in the program window and also save the program
g) Run the model sim simulator and enter the inputs.
h) Obtain the corresponding output waveforms.
711012106105
Design
Half AdderTruth Table
A
0
0
1
1
B
0
1
0
1
Circuit Diagram
Output
S
C
0
0
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
C=AB
Full AdderTruth Table

A
B Cin S
Cout
0
0
0
0
1
1
1
1
S=A
0
0
0
1
0
1
1
1
Circuit Diagram
A
B
AB
S=A B
Ci
n
AB
BCin
ACi
n
Cou
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Half Adder:
Program:
module halfadderm(a, b, sum, carry);
input a;
input b;
output sum;
output carry;
assign carry=a&b;
assign sum=a^b;
endmodule
TEST BENCH
module halfaddert_v;
reg a;
reg b;
wire sum;
wire carry;
halfadderm uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
initial begin
#10 a=1'b0;b=1'b0;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
#10$stop;
end
endmodule
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Full Adder
Program:
module fulladdm(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
wire d,e,f;
xor(sum,a,b,c);
and(d,a,b);
and(e,b,c);
and(f,a,c);
or(carry,d,e,f);
endmodule
TEST BENCH
module fulladdt_v;
reg a;
reg b;
reg c;
wire sum;
wire carry;
fulladdm uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
.carry(carry)
);
initial begin
#10 a=1'b0;b=1'b0;c=1'b0;
#10 a=1'b0;b=1'b0;c=1'b1;
#10 a=1'b0;b=1'b1;c=1'b0;
#10 a=1'b0;b=1'b1;c=1'b1;
#10 a=1'b1;b=1'b0;c=1'b0;
#10 a=1'b1;b=1'b0;c=1'b1;
#10 a=1'b1;b=1'b1;c=1'b0;
#10 a=1'b1;b=1'b1;c=1'b1;
#10$stop;
end
endmodule
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8 BIT ADDER
module ripplemod(a, b, cin, sum, cout);
input [07:0] a;
input [07:0] b;
input cin;
output [7:0]sum;
output cout;
wire[6:0] c;
fulladd a1(a[0],b[0],cin,sum[0],c[0]);
fulladd a2(a[1],b[1],c[0],sum[1],c[1]);
fulladd a8(a[7],b[7],c[6],sum[7],cout);
endmodule
module fulladd(a, b, cin, sum, cout);
input a;
input b;
input cin;
output sum;
output cout;
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assign sum=(a^b^cin);
assign cout=((a&b)|(b&cin)|(a&cin));
endmodule
TEST BENCH
module rippleadder_b;
reg [7:0] a;
reg [7:0] b;
reg cin;
wire [7:0] sum;
wire cout;
ripplemod uut (.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout) );
initial begin
#10 a=8b00000001;b=8b00000001;cin=1b0;
#10 a=8b00000001;b=8b00000001;cin=1b1;
#10 a=8b00000010;b=8b00000011;cin=1b0;
#10 a=8b10000001;b=8b10000001;cin=1b0;
#10 a=8b00011001;b=8b00110001;cin=1b0;
#10 a=8b00000011;b=8b00000011;cin=1b1;
#10 a=8b11111111;b=8b00000001;cin=1b0;
#10 a=8b11111111;b=8b00000000;cin=1b1;
#10 a=8b11111111;b=8b11111111;cin=1b0;
#10 $stop; end
endmodule
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Simulated Waveform (Half Adder)
Simulated Waveform (Half Adder)
Simulated Waveform(8 bit Adder)
711012106105
VIVA-VOCE Question:
1. What is a Logic Gate?
2. Write the names of Universal Gates.
3. Define half adder and full adder.
4. Define half subtractor and full subtractor.
5. What do you mean by carry propagation delay?
RESULT:
Thus the verilog code for the implementation of combinational logic circuits- half
adder, full adder and 8 bit adder has been executed successfully and the output is verified.
711012106105
IMPLEMENTATION OF 4*1 MULTIPLEXER AND 1*4 DEMUX -TEST BENCH
CREATION AND FUNCTIONAL VERIFICATION
Ex No:
Date :
Aim:
To write a Verilog code and to implement 4*1 Multiplexer and 1*4 Demultiplexer
in Xilinx Spartan 3E FPGA kit.
Tools Required:
Procedure:
711012106105
4-to-1 line MUX (or) 4x1MUX
S1 '
I1
I2
S0 '
0
1 4x 1
2 MUX
3
I0
I0
S1
S0
Logic Diagram.
S1
I3
I2
S0
I1
I3
S0
Truth Table
S1
Y
I0
I1
I2
I3
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Program (4:1 MULTIPLEXER)
module muxm(a, s, o);
input [3:0] a;
input [1:0] s;
output o;
reg o;
always @(a or s)
begin
case (s)
2'b00:o=a[0];
2'b01:o=a[1];
2'b10:o=a[2];
2'b11:o=a[3];
default:o=0;
endcase
end
endmodule
TEST BENCH
module muxt_v;
reg [3:0] a;
reg [1:0] s;
wire o;
muxm uut (
.a(a),
.s(s),
.o(o)
);
initial begin
#10 a=4'b1010;
#10 s=2'b00;
#10 s=2'b01;
#10 s=2'b10;
#10 s=2'b11;
#10 $stop;
end
endmodule
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Logic Diagram(1:4 Demux)
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Program (1:4 Demultiplexer)
module demuxm(s,a,d);
input [0:1] s;
input a;
output [0:3] d;
reg [0:3] d;
always @(a or s)
begin
if(a==1)
begin
case (s)
2'b00:d=4'b1000;
2'b01:d=4'b0100;
2'b10:d=4'b0010;
2'b11:d=4'b0001;
default:d=0;
endcase
end else if(a==0)
d=0;
end
endmodule
TEST BENCH
module demuxt_v;
reg [0:1] s;
reg a;
wire [0:3] d;
demuxm uut (
.s(s),
.a(a),
.d(d)
);
initial begin
#10 s=2'b00;a=1'b0;
#10 s=2'b00;a=1'b1;
#10 s=2'b01;a=1'b0;
#10 s=2'b01;a=1'b1;
#10 s=2'b10;a=1'b0;
#10 s=2'b10;a=1'b1;
#10 s=2'b11;a=1'b0;
#10 s=2'b11;a=1'b1;
#10 $stop;
end
endmodule
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Simulated Waveform(4:1 MUX)
Simulated Waveform(1:4 Demux)
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RESULT:
Thus the verilog code for the implementation of 4*1 multiplexer and 1*4
demultiplexer- test bench creation and functional verification has been executed
successfully and the output is verified.
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DESIGN AND SIMULATION OF MULTIPLIER AND ADDRESS DECODER

Ex No:
Date:
Aim : To write a Verilog code and to implement 4 bit multiplier and address
decoder .
Tools Required:
Procedure.
PROGRAM (4 BIT MULTIPLIER)
module multipliermod(a, b, out);
input [4:0] a;
input [4:0] b;
output [9:0] out;
assign out=(a*b);
endmodule
TEST BENCH
module multipliert_b;
reg [4:0] a;
reg [4:0] b;
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wire [9:0] out;
multipliermod uut (.a(a),.b(b),.out(out) );
initial begin
#10 a=4b1000;b=4b0010;
#10 a=4b0010;b=4b0010;
#10 a=4b0100;b=4b0100;
#10 a=4b1000;b=4b0001;
#10$stop;
end
endmodule
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TRUTH TABLE:
E
1
0
0
0
0
INPUT
A
0
0
0
1
1
B
0
0
1
0
1
D0
1
0
1
1
1
OUTPUT
D1
D2
1
1
1
1
0
1
1
0
1
1
D3
1
1
1
1
0
Simulated Waveform(Multiplier)
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2x4 DECODER
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TRUTH TABLE
DECODER
module decoderm(e, a, b, d);
input e;
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input a;
input b;
output [7:0] d;
assign d[0]=(~e)&(~a)&(~b);
assign d[1]=(~e)&(~a)&(b);
assign d[2]=(~e)&(a)&(~b);
assign d[3]=(~e)&(a)&(b);
assign d[4]=(e)&(~a)&(~b);
assign d[5]=(e)&(~a)&(b);
assign d[6]=(e)&(a)&(~b);
assign d[7]=(e)&(a)&(b);
endmodule
TEST BENCH
module decodert_v;
reg e;
reg a1;
reg a0;
wire [3:0] d;
decoderm uut (
.e(EN),
.a0(A0),
.a1(A0),
.d(D)
);
initial begin
#10 e=1'b0;a=1'b0;b=1'b0;
#10 e=1'b0;a=1'b0;b=1'b1;
#10 e=1'b0;a=1'b1;b=1'b0;
#10 e=1'b0;a=1'b1;b=1'b1;
#10$stop;
end
endmodule
Simulated Waveform(2x4 Decoder)
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VIVA-VOCE Question:
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1.What is Multiplexer?
2.What is DeMultiplexer?
3.Give application of multiplexer?
4.What is the difference between Decoder and Demultiplexer?
5.What do you mean by encoder?
6. What is Decoder?
7.What do you mean by comparator?
8. Write a short note on priority encoder?
9. Distinguish between an encoder and decoder?
RESULT:
Thus the verilog code for the implementation of design and simulation of
multiplier and address decoder has been executed successfully and the output is verified.
IMPLEMENTATION OF D FLIP FLOP , JK FLIP FLOP AND T FLIP FLOPTEST BENCH CREATION AND FUNCTIONAL VERIFICATION
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EXPT NO.
DATE :
Aim:
To write a Verilog code and verify simulation of TFF JKFF and DFF.
Tools Required.
Xilinix ISE 9.1, ModelSim SE 6.0
Procedure.
Program:T FF
T FLIPFLOP
module tffmod(t, clk, q);
input t;
input clk;
output q;
reg q;
initial q<=1b0;
always @(posedge clk)
q<=q^t;
endmodule
TEST BENCH
module tflipflopt_b;
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reg t;
reg clk;
wire q;
tffmod uut (.t(t), .clk(clk),.q(q));
initial begin
t = 0;
clk = 0;
#100;
end
always #3 clk=~clk;
always #5 t=~t;
initial
#100 $stop;
endmodule
T Flip Flop Diagram
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Truth Table
D Flip Flop Logic Diagram

Truth Table
D
0
1
D
Q
Q(t+1)
0
1
CP
1
Q'
JK Flip Flop Logic Diagram..

Truth Table
Q
CP
Q'
J
0
0
1
1
K
0
1
0
1
Q(t+1)
Q(t)
0
1
Toggle
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PROGRAM: D FF
D FLIPFLOP
module dflipflopmod(q, d, clk);
output q;
input d;
input clk;
reg q;
always @(posedge clk)
q=d;
endmodule
TEST BENCH
module dflipflopt_b;
reg d;
reg clk;
wire q;
dflipflopmod uut (.q(q),.d(d), .clk(clk) );
initial begin
// Initialize Inputs
d = 0;
clk = 0;
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end
always #3 clk=~clk;
always #5 d=~d;
initial
#100 $stop;
endmodule;
JKFF
module jkms(q,q_bar,clk,j,k);
output q,q_bar;
input clk,j,k;
reg tq,q,q_bar;
always @(clk)
begin
if (!clk)
begin
if (j==1'b0 && k==1'b1)
tq <= 1'b0;
else if (j==1'b1 && k==1'b0)
tq <= 1'b1;
else if (j==1'b1 && k==1'b1)
tq <= ~tq;
end
if (clk)
begin
q <= tq;
q_bar <= ~tq;
end
end
endmodule
TESTBENCH
module jkms_test;
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reg clk,j,k;
wire q,q_bar;
wire clk2,j2,k2;
jkms inst(q,q_bar,clk,j,k);
assign clk2=clk;
assign j2=j;
assign k2=k;
initial
clk = 1'b0;
always #10
clk = ~clk;
initial
begin
j = 1'b0; k = 1'b0;
#60 j = 1'b0; k = 1'b1;
#40 j = 1'b1; k = 1'b0;
#20 j = 1'b1; k = 1'b1;
#40 j = 1'b1; k = 1'b0;
#5 j = 1'b0; #20 j = 1'b1;
#10 ;
end
endmodule
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Simulated Waveform(D flip flop)
Simulated Waveform (T flip flop)
Simulated Waveform(JK Flip flop)
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VIVA-VOCE Question:
1.
2.
3.
4.
5.
6.
What do you mean by latches and flip-flops?

What is the drawback of SR Flip-Flop? How is this minimized?
Define Flip flop.
What are the different types of flip-flop?
What is the operation of D flip-flop?
What is the operation of T flip-flop?
RESULT:
Thus the verilog code for the implementation of D FF, JK FF and T FF-test bench
creation and functional verification has been executed successfully and the output is
verified.
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IMPLEMENTATION OF 2 BIT COUNTER

EXPT NO.
DATE :
Aim:
To write a Verilog code and verify simulation of counters.
Tools Required:
Procedure:
Program(2 bit Counter)
module Count2Bit(Clock, Clear, out);

input Clock, Clear;
output [1:0] out;
reg [1:0]out;
always@(posedge Clock, negedge Clear)
if((~Clear) || (out>=4))
out=2'b00;
else
out=out+1;
endmodule
RESULT:
Thus the verilog code for the implementation of 2 bit counter has been executed
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Simulated Waveform(2 bit Counter)
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IMPLEMENTATION OF PRBS GENERATORS AND ACCUMULATOR-TEST

BENCH CREATION AND FUNCTIONAL VERIFICATION
EXPT NO.
DATE :
Aim:
To write a code and to implement PRBS Generators and Accumulators.
Tools Required:
Procedure:
PROGRAM (PRBS Generators )
module prbs(a,clk,clr);
output [3:0] a;
input clk,clr;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if(clr)
begin
tmp = 4'b1111;
end
else
begin
tmp = { tmp[0]^tmp[1],tmp[3],tmp[2],tmp[1]};
end
end
assign a=tmp;
endmodule
TEST BENCH (PRBS)
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module main;
reg clk, reset;
wire rand;
prbs pr (rand, clk, reset);
initial
begin
forever
begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end
initial begin
reset = 1;
#12
reset = 0;
#90
reset = 1;
#12
reset = 0;
end
endmodule
PROGRAM (Accumulator )
module accumod (in, acc, clk, reset);
input [7:0] in;
input clk, reset;
output [7:0] acc;
reg [7:0] acc;
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always@(clk) begin
if(reset)
acc <= 8b00000000;
else
acc <= acc + in;
end
endmodule
TEST BENCH (Accumulator)
module accumt_b;
reg [7:0] in;
reg clk;
reg reset;
wire [7:0] acc;
accumod uut ( .in(in), .acc(acc),.clk(clk),.reset(reset) );
initial begin
#5 reset<=1b1;
#5 reset<=1b0;
clk =1b0;
in = 8b00000001;
#50 in = 8b00000010;
#50 in = 8b00000011;
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end
always #10 clk = ~clk;
initial#180 $stop;
endmodule
RESULT:
Thus the verilog code for the implementation of prbs generators and accumulatortest bench creation and functional verification has been executed successfully and the
output is verified.
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Simulated Waveform for PRBS generator:
Simulated Waveform for Accumulator
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STUDY OF SYNTHESIS, P&R AND POST P&R SIMULATION OF FULL
ADDER, 8 BIT ADDER, T FLIP FLOP AND 4 BIT COUNTER
Ex No:
Date :
Aim:
To synthesis, P & R and Post P&R simulation of Full Adder, 8 Bit Adder, T Flip Flop
and 4 Bit Counter
Apparatus required:
PC with Windows XP.
XILINX, ModelSim software.
FPGA kit.
RS 232 cable.
Procedure:
Write and draw the Digital logic system.
Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above Verilog code (using ModelSim or
Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.
Theory: Synthesis
Now that you have created the source files, verified the designs behavior with simulation,
and added constraints, you are ready to synthesize and implement the design.
Implementing the Design:
1. Select the counter source file in the Sources in Project window.
2. In the Processes for Source window, click the + sign next to Implement Design. The
Translate, Map, and Place & Route processes are displayed. Expand those processes as
well by clicking on the + sign. You can see that there are many sub-processes and
options that can be run during design implementation.
3. Double-click the top level Implement Design process.ISE determines the current state
of your design and runs the processes needed to pull your design through implementation.
In this case, ISE runs the Translate, Map and PAR processes. Your design is now pulled
through to a placed-and-routed state. This feature is called the pull through model.
4. After the processes have finished running, notice the status markers in the Processes
for Source window. You should see green checkmarks next to several of the processes,
indicating that they ran successfully. If there are any yellow exclamation points, check
the warnings in the Console tab or the Warnings tab within the Transcript window. If a
red X appears next to a process, you must locate and fix the error before you can
continue.
Verification of Synthesis:
Your synthesized design can be viewed as a schematic in the Register Transfer Level
(RTL) Viewer. The schematic view shows gates and elements independent of the targeted
Xilinx device.
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1. In the Processes for Source window, double-click View RTL Schematic found in the
Synthesize - XST process group. The top level schematic representation of your
synthesized design opens in the workspace.
2. Right-click on the symbol and select Push Into the Selected Instance to view the
schematic in detail. The Design tab appears in the Sources in Project window, enabling
you to view the design hierarchy. In the schematic, you can see the design components
you created in the HDL source, and you can push into symbols to view increasing
levels of detail.
3. Close the schematic window.
Theory: P&R and Post P&R Simulation
After implementation is complete, you can verify your design before downloading it to a
device. Viewing Placement: In this section, you will use the Floor planner to verify your
pin outs and placement. Floor planner is also very useful for creating area groups for
designs.
1. Select the counter source file in the Sources in Project window.
2. Click the + sign to expand the Place & Route group of processes.
3. Double-click the View/Edit Placed Design (Floorplanner) process. The Floorplanner
view opens.
4. Select View _ Zoom _ ToBox and then use the mouse to draw a box around the
counter instance, shown in green on the right side of the chip.
5. This Fig 1 shows where the entire design was placed. Click on any of the components
listed in the Design Hierarchy window to see where each component is placed.
6. Zoom in to the right side of the chip even more, and place your mouse over the
K13pad. You can see that your pinout constraint was applied - the DIRECTION pin is
placed at K13.
7. Close the Floorplanner without saving.
Viewing Resource Utilization in Reports: Many ISE processes produce summary
reports which enable you to check information about your design after each process is
run. Detailed reports are available from the Processes for Source window. You can also
view summary information and access most often-utilized reports in the Design
Summary.
1. Click on the Design Summary tab at the bottom of the window. If you closed the
summary during this tutorial, you can reopen it by double-clicking the View Design
Summary process.
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Figure 3: Timing Analyzer - Timing Summary
Figure 4: FPGA Editor - Detailed View
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2. In the Device Utilization Summary section, observe the number of Slice Flip Flops that
were used during implementation. You should see 4 flip flops, since you implemented a
4-bit counter.
3. To see other reports, scroll to the bottom of the Design Summary. You can click on a
report from here to view it in the ISE Text Editor.
Timing Closure: In this section, you will run timing analysis on your design to verify
that your timing constraints were met. Timing closure is the process of working on your
design to ensure that it meets your necessary timing requirements. ISE provides several
tools to assist with timing closure.
1. In the Processes for Source window, under the Place & Route group of processes,
expand the Generate Post-Place & Route Static Timing group by clicking the +sign.
2. Double-click the Analyze Post-Place & Route Static Timing process. The Timing
Analyzer opens.
3. To analyze the design, select Analyze Against Timing Constraints. The Analyze with
Timing Constraints dialog box opens.
4. Click OK. When analysis is complete, the timing report opens.
5. Select Timing summary from the Timing Report Description tree in the left window.
This displays the summary section of the timing report, where you can see that no timing
errors were reported.
6. Close the Timing Analyzer without saving.
Viewing the Placed and Routed Design
In this section, you will use the FPGA Editor to view the design. You can view your
design on the FPGA device, as well as edit the placement and routing with the FPGA
Editor.
1. Double-click the View/Edit Routed Design (FPGA Editor) process found in the
Place & Route group of processes. Your implemented design opens in the FPGA Editor.
2. Look in the List window to examine your design components.
3. Click on the COUNT_OUT K12 IOB in the List window to select the row. This is one
of the outputs in your design.
4. With the COUNT_OUT K12 row selected, select View _ Zoom Selection. In the
editor window, you can see the COUNT_OUT<0> IOB highlighted in red.
5. Push into (double-click) the red-highlighted COUNT_OUT K12 IOB. You should see
Fig 4.
6. Enlarge the window and zoom in so you can see more detail. This view shows the
inside of an FPGA at the lowest viewable level. The blue line shows the route that is used
through the IOB. The red lines show the routes that are available.
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Figure 5: Simulator Processes for Test Bench
Figure 6: Timing Simulation in ISE Simulator

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7. Verify that the signal goes to the pad as an output.

8. Close the FPGA Editor.
Timing Simulation (ISE Simulator): You can verify that your design meets your timing
requirements by running a timing simulation. You can use the same test bench waveform
that was used earlier in the design flow for behavioral simulation. When running timing
simulation, the ISE tools create a structural HDL file which includes timing information
available after Place and Route is run. The simulator will run on a model that is created
based on the design to be downloaded to the FPGA. If you are using ISE Base or
Foundation, you can simulate your design with the ISE Simulator. To simulate your
design with ModelSim, skip to the Timing Simulation (ModelSim) section. To run the
integrated simulation processes:
1. Select the test bench waveform in the Sources in Project window. You can see the ISE
Simulator processes in the Processes for Source window.
2. Double-click the Simulate Post-Place & Route Model process. This process
generates a timing-annotated netlist from the implemented design and simulates it. The
resulting simulation is displayed in the Waveform Viewer. These results look different
than those you saw in the behavioral simulation earlier in this tutorial. These results show
timing delays.
3. To see your simulation results, zoom in on the transitions and view the area between
300 ns and 900 ns to verify that the counter is counting up and down as directed by the
stimulus on the DIRECTION port.
4. Zoom in again to see the timing delay between a rising clock edge and an output
transition.
5. Click the Measure Marker button and then click near the 300 ns mark. Drag the
second marker to the point where the output becomes stable to see the time delay
between the clock edge and the transition.
6. Close the waveform view window.You have completed timing simulation of your
design using the ISE Simulator. Skip past the ModelSim section below, and proceed to
the Creating Configuration Data section.
Timing Simulation (ModelSim): If you have a ModelSim simulator installed, you can
simulate your design using theintegrated ModelSim flow. You can run processes from
within ISE which launches the installed ModelSim simulator.
1. To run the integrated simulation processes, select the test bench in the Sources in
Project window. You can see the ModelSim Simulator processes in the Processes
for Source window.
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Figure 7: Simulator Processes for Test Bench
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Figure 8: Timing Simulation in ModelSim

2. Double-click the Simulate Post-Place & Route VHDL/Verilog Model process.
3. Zoom in on the area between 300 ns and 900 ns to verify that the counter is counting
up and down as directed by the stimulus on the DIRECTION port.
4. Zoom in on the rising clock edges to see that the output transitions occur slightly later
due to the timing delay.
5. Close the ModelSim window.
RESULT:
Thus the study of synthesis,P&R and post P&R simulation of full adder,8 bit
adder,T flip flop and 4 bit counter had been executed successfully and the output is
verified.
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SIMULATION &LAYOUT OF CMOS INVERTER, PARASITIC EXTRACTION

USING TANNER
Expt.No:
Date:
AIM:
To design a CMOS inverter circuit using Tanner tool.
SOFTWARE REQUIRED:
L-Edit & T-SPICE - Tanner Tool.
PROCEDURE
For simulation
1) Draw the schematic of CMOS Inverter using S-edit.
2) Perform Transient Analysis of the CMOS Inverter.
3) Obtain the output waveform from W-edit.
4) Obtain the spice code using T-edit.
For drawing Lay-out
1. Draw the CMOS Inverter layout by obeying the Lamda Rules using Ledit.
i. Poly - 2
ii. Active contact - 2
iii. Active Contact Metal - 1
iv. Active Contact Active region - 2
v. Active Region Pselect - 3
vi. Pselect nWell - 3
2. Check DRC to verify whether any region violate the lamda rule.
3. Setup the extraction and extract the spice code using T-spice. Tanner PRO-V software
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CMOS INVERTER DESIGN
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OUTPUT
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RESULT:
Thus the simulation & layout of CMOS inverter,parasitic extraction using tanner
has been executed successfully and the output is verified.
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SCHEMATIC ENTRY AND SPICE SIMULATION OF MOS DIFFERENTIAL

AMPLIFIER.
Expt.No:
Date:
AIM:
To design a MOS Differential Amplifier circuit using Tanner tool and to
determine its gain, bandwidth, output impedance and CMRR.
SOFTWARE REQUIRED:
L-Edit & T-SPICE - Tanner Tool.
Theory:
A differential amplifier is a type of electronic amplifier that multiplies
the difference between two inputs by some constant factor (the differential gain).
Many electronic devices use differential amplifiers internally. The output of an
ideal differential amplifier is given by:
Where Vin+ and Vin- are the input voltages and Ac is the differential gain.
In practice, however, the gain is not quite equal for the two inputs. This means
that if Vin+ and Vin- are equal, the output will not be zero, as it would be in the
ideal case. A more realistic expression for the output of a differential amplifier
thus includes a second term.
Ac is called the common-mode gain of the amplifier. As differential

amplifiers are often used when it is desired to null out noise or bias-voltages that
appear at both inputs, a low common-mode gain is usually considered good.
The common-mode rejection ratio, usually defined as the ratio between
differential-mode gain and common-mode gain, indicates the ability of the
amplifier to accurately cancel voltages that are common to both inputs.
Common-mode rejection ratio (CMRR):
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PROCEDURE
1. Draw the CMOS Inverter layout by obeying the Lamda Rules using Ledit.
i. Poly - 2
ii. Active contact - 2
iii. Active Contact Metal - 1
iv. Active Contact Active region - 2
v. Active Region Pselect - 3
vi. Pselect nWell - 3
2. Check DRC to verify whether any region violate the lamda rule.
3. Setup the extraction and extract the spice code using T-spice. Tanner PRO-V software
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MOS AMPLIFIER DESIGN
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SIMULATION RESULTS FOR DIFFERENTIAL AMPLIFIER:
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RESULT:
Thus the schematic entry and spice simulation of MOS differential amplifier has
been executed successfully and the output is verified.
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711012106105
DESIGN OF A 10 BIT NUMBER CONTROLLED OSCILLATOR

EXPT NO.
DATE :
Aim:
To design a 10 bit number controlled oscillator using standard cell approach .
Tools Required:
Procedure.
e) Create a new source and enter HDL file name and also the module name.
f) Enter the input and the output variables.
g) Enter the coding in the program window and also save the program
h) Run the model sim simulator and enter the inputs.
i) Obtain the corresponding output waveforms.
PROGRAM
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY nco IS
-- Declarations
port ( clk : in std_logic;
reset : in std_logic;
din : in signed(11 downto 0);
dout : out signed(7 downto 0) );
END nco ;
-- hds interface_end
ARCHITECTURE behavior OF nco IS
type vectype is array (0 to 256) of signed(7 downto 0);
-- ROM cosrom
constant cosrom : vectype := (
0 => "01111111",
1 => "01111111",
2 => "01111111",
3 => "01111111",
4 => "01111111",
5 => "01111111",
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6 => "01111111",
7 => "01111111",
8 => "01111111",
9 => "01111111",
10 => "01111111",
11 => "01111111",
12 => "01111111",
13 => "01111111",
14 => "01111111",
15 => "01111111",
16 => "01111111",
17 => "01111111",
18 => "01111111",
19 => "01111111",
20 => "01111111",
21 => "01111111",
22 => "01111111",
23 => "01111111",
24 => "01111111",
25 => "01111110",
26 => "01111110",
27 => "01111110",
28 => "01111110",
29 => "01111110",
30 => "01111110",
31 => "01111110",
32 => "01111110",
33 => "01111101",
34 => "01111101",
35 => "01111101",
36 => "01111101",
37 => "01111101",
38 => "01111101",
39 => "01111100",
40 => "01111100",
41 => "01111100",
42 => "01111100",
43 => "01111100",
44 => "01111011",
45 => "01111011",
46 => "01111011",
47 => "01111011",
48 => "01111010",
49 => "01111010",
50 => "01111010",
51 => "01111010",
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52 => "01111010",
53 => "01111001",
54 => "01111001",
55 => "01111001",
56 => "01111001",
57 => "01111000",
58 => "01111000",
59 => "01111000",
60 => "01110111",
61 => "01110111",
62 => "01110111",
63 => "01110111",
64 => "01110110",
65 => "01110110",
66 => "01110110",
67 => "01110101",
68 => "01110101",
69 => "01110101",
70 => "01110100",
71 => "01110100",
72 => "01110100",
73 => "01110011",
74 => "01110011",
75 => "01110011",
76 => "01110010",
77 => "01110010",
78 => "01110010",
79 => "01110001",
80 => "01110001",
81 => "01110001",
82 => "01110000",
83 => "01110000",
84 => "01101111",
85 => "01101111",
86 => "01101111",
87 => "01101110",
88 => "01101110",
89 => "01101101",
90 => "01101101",
91 => "01101101",
92 => "01101100",
93 => "01101100",
94 => "01101011",
95 => "01101011",
96 => "01101010",
97 => "01101010",
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98 => "01101010",
99 => "01101001",
100 => "01101001",
101 => "01101000",
102 => "01101000",
103 => "01100111",
104 => "01100111",
105 => "01100110",
106 => "01100110",
107 => "01100101",
108 => "01100101",
109 => "01100100",
110 => "01100100",
111 => "01100011",
112 => "01100011",
113 => "01100010",
114 => "01100010",
115 => "01100001",
116 => "01100001",
117 => "01100000",
118 => "01100000",
119 => "01011111",
120 => "01011111",
121 => "01011110",
122 => "01011110",
123 => "01011101",
124 => "01011101",
125 => "01011100",
126 => "01011100",
127 => "01011011",
128 => "01011011",
129 => "01011010",
130 => "01011001",
131 => "01011001",
132 => "01011000",
133 => "01011000",
134 => "01010111",
135 => "01010111",
136 => "01010110",
137 => "01010101",
138 => "01010101",
139 => "01010100",
140 => "01010100",
141 => "01010011",
142 => "01010010",
143 => "01010010",
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144 => "01010001",
145 => "01010001",
146 => "01010000",
147 => "01001111",
148 => "01001111",
149 => "01001110",
150 => "01001110",
151 => "01001101",
152 => "01001100",
153 => "01001100",
154 => "01001011",
155 => "01001010",
156 => "01001010",
157 => "01001001",
158 => "01001000",
159 => "01001000",
160 => "01000111",
161 => "01000111",
162 => "01000110",
163 => "01000101",
164 => "01000101",
165 => "01000100",
166 => "01000011",
167 => "01000011",
168 => "01000010",
169 => "01000001",
170 => "01000001",
171 => "01000000",
172 => "00111111",
173 => "00111110",
174 => "00111110",
175 => "00111101",
176 => "00111100",
177 => "00111100",
178 => "00111011",
179 => "00111010",
180 => "00111010",
181 => "00111001",
182 => "00111000",
183 => "00111000",
184 => "00110111",
185 => "00110110",
186 => "00110101",
187 => "00110101",
188 => "00110100",
189 => "00110011",
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190 => "00110011",
191 => "00110010",
192 => "00110001",
193 => "00110000",
194 => "00110000",
195 => "00101111",
196 => "00101110",
197 => "00101101",
198 => "00101101",
199 => "00101100",
200 => "00101011",
201 => "00101010",
202 => "00101010",
203 => "00101001",
204 => "00101000",
205 => "00100111",
206 => "00100111",
207 => "00100110",
208 => "00100101",
209 => "00100100",
210 => "00100100",
211 => "00100011",
212 => "00100010",
213 => "00100001",
214 => "00100001",
215 => "00100000",
216 => "00011111",
217 => "00011110",
218 => "00011110",
219 => "00011101",
220 => "00011100",
221 => "00011011",
222 => "00011011",
223 => "00011010",
224 => "00011001",
225 => "00011000",
226 => "00011000",
227 => "00010111",
228 => "00010110",
229 => "00010101",
230 => "00010100",
231 => "00010100",
232 => "00010011",
233 => "00010010",
234 => "00010001",
235 => "00010001",
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236 => "00010000",
237 => "00001111",
238 => "00001110",
239 => "00001101",
240 => "00001101",
241 => "00001100",
242 => "00001011",
243 => "00001010",
244 => "00001010",
245 => "00001001",
246 => "00001000",
247 => "00000111",
248 => "00000110",
249 => "00000110",
250 => "00000101",
251 => "00000100",
252 => "00000011",
253 => "00000010",
254 => "00000010",
255 => "00000001",
256 => "00000000");
signal dtemp : unsigned(17 downto 0);
signal din_buf : signed(17 downto 0);
signal dtemp1 : integer;
constant offset : unsigned(17 downto 0) := "000100000000000000";
begin
process(CLK, RESET)
begin
if (RESET='1') then
dout <= (others => '0');
din_buf <= (others => '0');
dtemp <= (others => '0');
dtemp1 <= 0;
elsif rising_edge(CLK) then
din_buf <= din(11)&din(11)&din(11)&din(11)&din(11)&din(11)&di n;
dtemp <= dtemp + unsigned(din_buf) + offset;
dtemp1 <= to_integer(dtemp(17 downto );
if (dtemp1 >= 0) and (dtemp1 < 257) then
dout <= cosrom(dtemp1);
elsif (dtemp1 >= 257) and (dtemp1 < 513) then
dout <= -cosrom(512-dtemp1);
elsif (dtemp1 >= 513) and (dtemp1 < 769) then
dout <= -cosrom(dtemp1-512);
else
dout <= cosrom(1024-dtemp1);
end if;
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end if;
end process;
RESULT:
Thus the design of a 10 bit number controlled oscillator has been executed
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AUTOMATIC LAYOUT GENERATION
Expt. No:
Date:
AIM:
To generate the Layout from the schematic using the Tanner tool and verify
the layout using simulation.
APPARATUS REQUIRED:
S-Edit, L-Edit using Tanner Tool.
Conversion procedure for schematic to Auto layout
Step1: Draw the schematic using S Edit and verify the output in W Edit.
Step2: Extract the schematic and store it in another location
Conversion procedure for schematic to Auto layout
Step1: Draw the schematic using S Edit and verify the output in W Edit.
Step2: Extract the schematic and store it in another location
Step3: Open the L Edit, open the design in Ring VCO
Step4: Create the new cell.
Step5. Open the schematic file (.sdl) using the SDL Navigator
Step6: Do the necessary connections as per the design.
Step7: Name the ports and check the design for the DRC Rules
Step8: Locate the Destination file in the setup Extract window and extract
the layout.
Step9: Include the Library and the print voltage statements in the net list
which is obtained.
Step10: Verify the layout design using W Edit
SCHEMATIC DIAGRAM:
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LAYOUT:
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SIMULATED WAVEFORM:
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RESULT:
Thus the automatic layout generation has been executed successfully and the
output is verified.
67

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711012106105

IMPLEMENTATION OF COMBINATIONAL LOGIC CIRCUITS- HALF

Full AdderTruth Table

Simulated Waveform (Half Adder)

Simulated Waveform(8 bit Adder)

Logic Diagram(1:4 Demux)

Simulated Waveform(4:1 MUX)

Simulated Waveform(1:4 Demux)

DESIGN AND SIMULATION OF MULTIPLIER AND ADDRESS DECODER

Simulated Waveform(2x4 Decoder)

T Flip Flop Diagram

D Flip Flop Logic Diagram

JK Flip Flop Logic Diagram..

Simulated Waveform (T flip flop)

Simulated Waveform(JK Flip flop)

What do you mean by latches and flip-flops?

IMPLEMENTATION OF 2 BIT COUNTER

module Count2Bit(Clock, Clear, out);

Simulated Waveform(2 bit Counter)

IMPLEMENTATION OF PRBS GENERATORS AND ACCUMULATOR-TEST

Simulated Waveform for PRBS generator:

Simulated Waveform for Accumulator

Figure 3: Timing Analyzer - Timing Summary

Figure 4: FPGA Editor - Detailed View

Figure 5: Simulator Processes for Test Bench

Figure 6: Timing Simulation in ISE Simulator

7. Verify that the signal goes to the pad as an output.

Figure 7: Simulator Processes for Test Bench

Figure 8: Timing Simulation in ModelSim

SIMULATION &LAYOUT OF CMOS INVERTER, PARASITIC EXTRACTION

CMOS INVERTER DESIGN

SCHEMATIC ENTRY AND SPICE SIMULATION OF MOS DIFFERENTIAL

Ac is called the common-mode gain of the amplifier. As differential

MOS AMPLIFIER DESIGN

SIMULATION RESULTS FOR DIFFERENTIAL AMPLIFIER:

DESIGN OF A 10 BIT NUMBER CONTROLLED OSCILLATOR

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