Documente Academic
Documente Profesional
Documente Cultură
TDDC33
Lab Instructions
Table of Contents
1. Introduction ......................................................................................................................................... 3
2. Initial preparations .............................................................................................................................. 4
3. Synthesis ............................................................................................................................................. 5
3.1. Input ............................................................................................................................................. 5
3.2. Output .......................................................................................................................................... 5
3.3. Synthesis procedure ..................................................................................................................... 5
4. Design for test using DFTAdvisor .................................................................................................. 7
4.1. Input ............................................................................................................................................. 7
4.2. Output .......................................................................................................................................... 7
4.3. Starting DFTAdvisor ................................................................................................................... 7
4.4. Circuit Setup ................................................................................................................................ 7
4.5. Test Synthesis .............................................................................................................................. 7
4.5.1 Full Scan Insertion ..................................................................................................................... 8
4.5.2 Partial Scan Insertion ................................................................................................................. 8
5. Fault Coverage Analysis and Test Pattern Generation using FastScan ............................................ 10
5.1. Input ........................................................................................................................................... 10
5.2. Output ........................................................................................................................................ 10
5.3. Writing test patterns ................................................................................................................... 10
5.4. Starting FastScan ....................................................................................................................... 11
5.5. Circuit setup ............................................................................................................................... 11
5.6. Fault simulation ......................................................................................................................... 12
5.7. Test pattern generation ............................................................................................................... 12
5.8. Results and analysis ................................................................................................................... 13
6. Test point insertion in VHDL ........................................................................................................... 14
6.1. Input ........................................................................................................................................... 14
6.2. Output ........................................................................................................................................ 14
6.3. Inserting test points .................................................................................................................... 14
7. Board test using Boundary Scan (IEEE 1149.1) ............................................................................... 15
7.1. Input ........................................................................................................................................... 15
7.2. Output ........................................................................................................................................ 15
TDDC33 Design for Test of Digital Systems
1. Introduction
This document describes the environmental setup and the tools needed to complete the lab
assignments in the course TDDC33 Design for Test of Digital Systems. The tools that are used in this
course are listed in Table 1. For the synthesis, automatic test pattern generation (ATPG), and design
for test (DFT), the core cells from AMS 0.35m [1] standard cell library will be used together with
the test library c35_CORELIB.atpg. A design named s27 will be used as an example throughout these
instructions. The s27 design is described in VHDL (s27.vhdl) and stored in a directory named
s27_test. The name of the design and the directory will later be changed as you solve the lab
assignments.
The rest of this document is organized as follows. Chapter 1 contains information about how to setup
the system in order to start the tools. The following chapters, Chapter 2 to Chapter 7, contain
instructions for the synthesis, DFT, test pattern generation, test point insertion, and board testing,
respectively.
Task
Synthesis
Design for test
Test pattern generation
Boundary Scan
Boundary Scan
Tool
Leonardo Spectrum
DFTAdvisor
FastScan
Trainer1149
TSTAP-Studio
Tool vendor
(Mentor Graphics)
(Mentor Graphics)
(Mentor Graphics)
(Testonica)
(SAAB Aerotech)
2. Initial preparations
The following commands are all executed in a terminal window.
Add the modules /mentor/tessent and mentor/fpgadv if they are missing.
To check which modules are already loaded issue the following command:
module list
If the modules /mentor/tessent and mentor/fpgadv are missing from the list, use the following
command to add the modules.
mkdir s27_test
Download and extract the required files. (Described in the labs)
gunzip labX.tar.gz
$MODEL_TECH/vlib work
Compile the vhdl files
$MODEL_TECH/vcom s27.vhdl
3. Synthesis
This chapter describes the synthesis procedure using Leonardo Spectrum from Mentor Graphics. It is
assumed that the initial preparations, described in the Chapter 2, have been made.
3.1. Input
A compiled VHDL-file
3.2. Output
A synthesized Verilog netlist
leonardo &
Click OK
In the Quick Setup tab
Select library file:
technology->ASIC->AMS->c35_CORELIB
Select input file
s27.v
In the Advanced tab
Run Flow
4.1. Input
A design netlist (Verilog netlist)
Library file
4.2. Output
A new design netlist
ATPG setup files (dofile and procedure file)
run
After running these commands, in the command window you will get a brief report stating the number
of sequential elements that were identified in your design and how many of them have been converted
into scan cells. Next, we insert the test logic in the design by issuing the following command:
Once you have prepared the configuration file you only need to insert the test logic that is specified
there. To do this, use the following command:
5.1. Input
A design netlist (Verilog netlist)
Library file
External test patterns (optional)
Command files: dofile and testproc file (optional)
5.2. Output
Test patterns
Fault coverage
10
clock_sequential ;
force
"PI" "01010" 0;
pulse "/H" 1;
force
"PI" "10110" 2;
11
If you are about to work with a design that contains scan chains, and you want the ATPG tool to use
these test feature while generating the patterns, then you need to provide the dofile to the tool by
issuing the following command:
dofile filename.dofile
Once you are done with the circuit setup, you can continue further with either running fault
simulation, in which case you should switch to the FAULT system mode, or running the ATPG
process, in which case you should switch to the ATPG system mode. Switching the system mode is
done by using the following command:
report faults
To supply your own test pattern set, you should use the following command:
run
To get a detailed report about the fault coverage, use the following command
report statistics
create patterns
In the reported statistics you will be able to see what is the fault coverage for the generated test
patterns.
TDDC33 Design for Test of Digital Systems
12
13
6.1. Input
A design described in VHDL
6.2. Output
A new design with test points.
Add the new input and output ports in the ENTITY block
Modify the design (introduction of new gates may be required) such that the new ports are
used to control and observe the hard-to-test parts of the design.
Please refer to Appendix A for an example of VHDL code with inserted test points.
14
7.1. Input
A board design, which consists of one bsdl-file for each chip and another file that contains a list of
connections between the chips.
7.2. Output
A test program.
java version
15
Select appropriate item in the Mode menu to change the working mode. Another way is to use the
toolbar buttons illustrated in Figure 4.
In Debug Mode it is possible to perform boundary scan operations on the current design. In the Board
Edit mode the user can create and/or modify the design. In this tutorial we focus on boundary scan
operations in Debug Mode.
Training->Inject Fault
The Injection Fault window, illustrated in Figure 5, will appear.
16
7.6. Writing and verifying a test program using the Test Constructor
The following procedure describes how to write a test program that detects if there is a stuck-at 0 fault
present at the net2 for the design presented in Figure 3. (to identify the net, just place the cursor over
the wire and the label of the net will appear)
Select the Debug Mode
Mode->Debug
The Test Constructor panel will appear as illustrated in Figure 6.
17
The buttons TLR, IR, and DR are used for test logic reset, perform scan on instruction register, and
perform scan on data register, respectively.
Specify the instruction and test vector.
Training->Check Fault
net 2
18
7.7. Writing and verifying a test program using the TAP Controller
The following procedure describes how to write a test program that detects if there is a stuck-at 0 fault
present at the net2 in Figure 20.
Open the TAP Controller state machine.
Specify the input signals TDI and TMS by pressing the buttons TDI(0) and TMS(0). The test clock is
toggled by pressing TCK(0).
Load the EXTEST instruction and apply the test vector.
The stuck-at 0 fault is detected by applying the test procedure presented in Table 2.
TDI(Value)
TMS(Value)
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
2
2
15
3
2
35
3
1
15
2
1
Comment
Run-Test/Idle
Select IR-Scan
Shift-IR
Shift in EXTEST for both chips
Select DR-Scan
Shift-DR
Shift in test vector (all 1s)
Select DR-Scan
Capture DR (responses captured)
Shift-DR (shift out results)
Update-DR
Run-Test/Idle
19
20
component nandg
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;
component norg
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;
component invg
generic (tpd_hl : time;
tpd_lh : time);
port (in1 : std_logic;
out1 : out std_logic);
end component;
component buffg
generic (tpd_hl : time;
tpd_lh : time);
port (in1 : std_logic;
out1 : out std_logic);
end component;
-- ******* Portes generiques sur le nombre d'entr
component andg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time);
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;
component nandg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time );
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;
component org_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time) ;
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;
21
component norg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time) ;
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;
component xorg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time) ;
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;
component xnorg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time) ;
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;
component DFFC
generic (tpd_hl : time;
tpd_lh : time);
port (DFFC,H,C : std_logic;
Q : out std_logic);
end component;
component DFF
generic (tpd_hl : time;
tpd_lh : time);
port (D,H : std_logic;
Q : out std_logic);
end component;
component TFFC
generic (tpd_hl : time;
tpd_lh : time);
port (T,H,C : std_logic;
Q : out std_logic);
end component;
signal INTERP : std_ulogic_vector(0 to 11):=(others=>'0') ;
signal OUTPI : std_ulogic_vector(OUTP'range):=(others=>'0') ;
22
BEGIN
DFF0 : DFF generic map (1 ns,1 ns)
port map (
D => INTERP(1),
H => H,
Q => INTERP(0));
DFF1 : DFF generic map (1 ns,1 ns)
port map (
D => INTERP(3),
H => H,
Q => INTERP(2));
DFF2 : DFF generic map (1 ns,1 ns)
port map (
D => INTERP(5),
H => H,
Q => INTERP(4));
INV0 : INVG generic map (1 ns,1 ns)
port map (
in1 => INP(0),
out1 => INTERP(6));
INV1 : INVG generic map (1 ns,1 ns)
port map (
in1 => INTERP(3),
out1 => OUTPI(0));
AND0 : ANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(6),
inp(1) => INTERP(2),
out1 => INTERP(7));
OR0 : ORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(9),
inp(1) => INTERP(7),
out1 => INTERP(8));
OR1 : ORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(3),
inp(1) => INTERP(7),
out1 => INTERP(10));
NAND0 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(10),
inp(1) => INTERP(8),
out1 => INTERP(11));
23
24
References
[1] http://asic.austriamicrosystems.com/databooks/c35/databook_c35_33/, April 2006.
25