Workbook MSP430F5xx - One - Day - Workshop - v1-2 PDF

MSP430 Microcontroller Workshop
Student Guide
Revision 1.2
July 2010
Technical Training
Organization
Important Notice
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Revision History
March 2010 Revision 1.0
July 2010 Revision 1.1 Roadmap and portfolio slide update
July 2010 Revision 1.2 Name change
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ii
MSP430 Microcontroller Workshop Microcontroller Workshop
Introduction
Introduction
This module will cover the MSP430 architecture, instruction set, and development tools. In the
lab exercise Code Composer Studion will be installed and we will verify that the hardware and
software has been configured properly.
Agenda
Introduction to the MSP430F5xx

5xx Active & Low Power Mode
Operation
A Mixed-Signal Application Example
Using Hardware Timers to Conserve
Power
A Fully-optimized ADC12 Routine
MSP430 Tools, Resources and
Conclusion
Portfolio
2
MSP430 Microcontroller Workshop - Introduction
1-1
Module Topics
Module Topics
Introduction ............................................................................................................................................... 1-1
Module Topics......................................................................................................................................... 1-2
Introduction ............................................................................................................................................ 1-3
TI Processor Portfolio......................................................................................................................... 1-3
5xx Summary...................................................................................................................................... 1-4
MSP430 Generations.......................................................................................................................... 1-5
MSP430 Roadmap.............................................................................................................................. 1-6
Orthogonal CPU ................................................................................................................................. 1-7
Unified Clock System......................................................................................................................... 1-7
5xx Operating Modes ......................................................................................................................... 1-8
Operating Range................................................................................................................................. 1-8
Memory Map ...................................................................................................................................... 1-9
SYS Module ....................................................................................................................................... 1-9
GPIO..................................................................................................................................................1-10
Port Map Module...............................................................................................................................1-10
Universal Serial Communications Interface ......................................................................................1-11
LCD_B and AES128 .........................................................................................................................1-11
USB ...................................................................................................................................................1-12
CC430................................................................................................................................................1-12
Embedded Emulation ........................................................................................................................1-13
Block Diagram...................................................................................................................................1-14
Experimenters Board........................................................................................................................1-14
Code Composer Studio 4.1 ................................................................................................................1-15
Community Support ..........................................................................................................................1-15
Lab 1: Setting up the Software and Hardware.......................................................................................1-17
Objective ...........................................................................................................................................1-17
Hardware / Software Requirements...................................................................................................1-17
Procedure...........................................................................................................................................1-18
1-2
Introduction
Introduction
TI Processor Portfolio
TI Embedded Processing Portfolio

TI Embedded Processors
Microcontroll ers (MCUs)
16-bit ultralow power
MCUs
32-bit
real-time
MCUs
MSP430
C2000
Delfino
Piccolo
Up to
25 MHz
40MHz to
300 MHz
ARM -Based Processors

32-bit ARM
Cortex-M3
MCUs
Stellaris
ARM Cortex-M3
ARM
Cortex-A8
MPUs
Sitara
ARM Cortex-A8
& ARM 9
Digital Signal Processors (DSPs)

DSP
DSP+ARM
C6000
DaVinci
300MHz to
>1GH z
Ultra
Low pow er
DSP
C6000
C5000
video pr oc essors
OMAP
U p to
100 MHz
Flas h
8 KB to 256 KB
USB, ENET
MAC +PHY CAN,
AD C, PWM, SPI
Multi-core
DSP
24.000
MMACS
C ache,
RAM, R OM
300MHz to >1Gh z
+Accelerato r
Ca che
RAM, ROM
Ca che
R AM, ROM
Up to 300 MHz
+Accelerator
Up to 32 0KB RA M
U p to 128 KB ROM
USB, C AN,
PCIe, EMAC
USB, ENET,
PC Ie, SATA , SPI
SRIO, EMAC
DMA, PC Ie
USB, AD C
McB SP, SPI, I 2C
Flas h
1 KB to 256 K B
Fla sh, RAM

16 KB to 51 2 K B
Analog I/O, A DC
LCD, USB, RF
PWM, ADC ,
CAN, SPI, I 2C
Measurement,
Sensing, General
Purpose
Motor Control,
Digi tal Power,
Li ghti ng, Ren. Enrgy
Connectivity, S ecurity,
Moti on Control, HM I,
I ndustrial Automati on
I ndustrial com puti ng,

POS & portable
data term inal s
Floati ng/Fi xed Poi nt

Video, Audio, Voice,
Securi ty, Conferencing
Telecom test & meas,

media gateways,
base stati ons
Medical , Biometrics
$0.25 to $9 .00
$ 1.5 0 to $20 .00
$ 1.00 to $8.00
$5 .0 0 to $20.00
$5.00 to $20 0.00
$40 to $ 200.00
$3.00 to $1 0.00
Audi o, V oi ce
Software & Dev. Tools

5xx Gen Summary
3
1-3
Introduction
5xx Summary
5xx Generation Summary
Ultra-Low Power
Increased Performance
230 A/MHz
1.9 A standby mode
Wake up from standby in < 5 s
Up to 25 MHz
8 MHz across entire operating range
(1.8 - 3.6 V)
1.8V ISP flash erase & write
Fail-safe, flexible clocking system
Innovative Features
Integrated LDO, BOR, WDT+, RTC

Multi-channel DMA supports data
movement in standby mode
More connectivity: USB, RF
AES encryption, RTC on backup
battery
User-defined Bootstrap Loader
Industry-leading code density
MSP430 Generations
1-4
Introduction
MSP430 Generations
MSP430 Generations
1xx
2xx
4xx
5xx
Basic Clock System
Basic Clock System +
FLL, F LL +
Unified Clock System

UCS
Core voltage same as

supply voltage
Core voltage same as supply

voltage
Core voltage same as

supply voltage
Programmable
Core Voltage
with integrated PMM
16-bit CPU
16-bit CPU, CPUX
16-bit CPU, CPU X
16-bit CPUXV2
GPIO
GPIO w/ pull-up and

pull-down
GPIO
GPIO w/pull-up
and pull-down,
drive strength
N/A
N/A
N/A
CRC 16
Software RT C
Software R TC
Software RT C with Basic

Timer, Basic Timer + RTC
T rue 32-bit RTC w/Alarms
USART
USCI, USI
USAR T, USCI
USCI, USB, RF
DMA up to 3-ch
DMA up to 3-ch
DMA up to 3-ch
DMA up to 8-ch
MPY16
MPY16
MPY16, MPY32
MPY32
ADC10,12
ADC10,12
ADC12
ADC12_A
4- wire JT AG
4-wir e JT AG, some devices with

Spy-Bi-Wire
4-wire JTAG
4-wire JT AG and
Spy-Bi-Wire
MSP430 Generations
5
1-5
Introduction
MSP430 Generations
Category
2xx
4xx
5xx
CPU Clock (max)
16MH z
8MHz
25MH z
Active Current
(@ 3.0V, typical)
515u A @ 1MH z
4.2mA @ 8MH z
6 00uA @ 1MHz
4 .8m A @ 8MHz
290u A @ 1 MHz
1.84mA @ 8 MHz 23 0 u A/MHz
9.1mA @ 16 MHz
N /A
8.90mA @ 2 5MHz
120KB / 8KB (Flash / RAM)
Wake-up Time From LPM3
1us
6us
5us
Standby LPM3 Current
0.9 1.1uA
1.1 2.5uA
1.9uA (RTC, WDT , SVS

enabled)
LPM4 Current
0.1uA
0.1uA
1.2uA (LPM4) / 0.1uA (LPM4.5)
Flash ISP Minimu m DV CC
2.2V
2.7V
1.8V
Port I/O Interrupt Capability
P1/P2
P1/P2
P1/P2
Prog. Port Pin Drive Strength
N/A
N/A
All port pins
Prog. Pull-ups / Pull- downs
All port pins
N/A
All port pins
12-bit A/D Internal Reference

Curr ent
500 uA
500 uA
100 uA*
12-bit A/D Active Conversion

Curr ent
800 uA
800 uA
150 uA*
Available MCLK Sources
DCO
LFXT1
XT 2 (if available)
VLO
F LL
LF XT 1
XT2 (if available)
N/A
LF XT 1
Some devices also P3/P4
Available FLL Reference

Clocks
F LL
LFXT 1 / XT 1
XT2 (if available)
VLO
R EF O
UCS
LFXT1, REFO,
& XT2 (if pr esent)
Roadmap
* 2xx, 4xx AD C12 ; 5xx - R EF & AD C12 _A

6
MSP430 Roadmap
MSP430 Roadmap
Device
Produ ct ion
Developm en t
F51x2
Lighti ng
16 M Hz
120 kB F lash
8 kB RAM
500 nA Stand by
1.8 3. 6V
F = Flash
C = ROM
FR = FRAM
8M Hz
60 kB Fl ash
10 kB RAM
1. 8 3.6 V
RF
F6/563x
BGM, Catal og
F 53xx
F543x
F541x
The Ne w Ge ne ration
5xx-6xx
Gen Purpose
L 092
0.9V Nati ve
F 21x2
F21x1
1xx-Catalog
USB
USB
F22xx
75 + de vices
F550x
F23x0
F23x0
F20xx
F552x
FRAM
F261x
F241x
F23x-F24x
2xx-Catalog
CC430
FR57xx
100+ dev ic es
F15x-F16x
F/CG461x
F13x- F14x
Fx43x
F12xx
F44x
F/C11xx
Fx42x
F 47x4
Fx42x0
F/C41x F E42x2
F41x2
F 471xx
Fx47x
25M Hz
256 kB Fl ash
16 kB RAM
1. 8 3.6V
FRAM , US B, RF
6xx: L CD Control ler
230 uA/M Hz
10 0+ devices
4xx: L CD
Up to 16 M Hz
120 kB Fl ash
8 kB RAM
L CD Control ler, 160
seg men ts
1. 8 3.6V
CPU
1-6
Introduction
Orthogonal CPU
5xx MSP430Xv2 Orthogonal CPU

C-compiler
friendly
Memory address range increased to
1MB
CPU
registers increased to 20-bits

Address-word instructions
Direct 20-bit CPU register access

Atomic (memory-to-memory) instructions
Instruction compatible
with previous
CPU
Cycle
count optimization
Extension word allows
all instructions
Direct access to 1MB address space
Bit, byte, word and address-word data
Repeat instruction function
UCS
8
Unified Clock System
Unified Clock System (UCS)
Six independent clock sources
Low Freq
LFXT1
VLO
32768 Hz crystal
10 kHz
REFO
32 kHz
High Freq
XT1
XT2
4 32 MHz crystal
4 32 MHz crystal
DCO
FLL multiple of reference
clock
FLL references are divisible
LFXT1 / XT1
REFO
XT2
ACLK / SMCLK / MCLK tree is

fully orthogonal
Clocks on demand
MODOSC provided to modules
Flash controller & ADC12_A

Operating Modes
1-7
Introduction
5xx Operating Modes
5xx Operating Modes
SVS protection for just 200 nA

Active Mode 230 uA/MHz
CPU active
Fast Peripher als Enabled
32 kHz Per ipherals Enabled - RTC
LPM0 70 uA
CPU disabled
Fast Peripher als Enabled
32 kHz Per ipherals Enabled RTC
LPM3 1.9 uA
CPU disabled
Fast Peripher als Disabled
32 kHz Per ipherals Enabled

RTC, Watchdog & SVS protection
LPM4 1.2 uA
All clocks disabled
Wake on interrupt
LPM4.5 (LPM5) 100 nA
Regulator & all clocks disabled

No RAM retention
BOR on nRST/NMI or Port I/O
Operating Range
10
Operating Range
5xx Voltage vs. Frequency Operating Range
25MHz peak performance

More performance
across VCC range
Flash ISP @ min. VCC

8MHz @ min. VC C
Up to 25MHz @ 2.4V-3.6V
Programmable VCORE
maximizes power
efficiency
Lowering VCC or VCORE
reduces system current
Mem Map
11
1-8
Introduction
Memory Map
5xx Memory Map
Page-free 20-bit addressing
User-definable Boot Strap

Loader
RAM starts at 0x1C00
Always a contiguous
block
Beginning of MAIN flash

moves according to RAM
Vector table starts at 0xFF80
SYS
12
SYS Module
5xx Peripherals The SYS Module
Reset Interrupt Vector Generator
Generates a constant that maps to the

cause of last reset
Simplifies reset handling
Brownout (BOR) (highest priority)

RST/NMI (POR)
DoBOR (BOR)
Port_wak eup (BOR)
Security violation (BOR)
Manages non-maskable interrupts
Reset events
NMIs split into SYSNMI & UNMI
SYSNMIs have higher priority
Separate interrupt vectors
SVSL (POR)
SVSH (POR)
SVML_OVP (POR)
SVMH_OVP (POR)
DoPOR (POR)
WDT time out (PUC)
Factory application data is

considered part of the SYS module
Factory calibration data and

peripheral discovery table
WDT k ey v iolation (PUC)

KEYV flash k ey violation (PUC)
PLL unlock (PUC)
PERF peripheral/config area fetch (PUC)
GPIO
13
1-9
Introduction
GPIO
5xx Peripherals GPIO

Initial state of GPIO pins is a digital input
Port registers allow for different configurations
PxDIR direction (input vs output)
PxREN enables internal pull-up/pull-down resistors

(input)
PxDS enables additional drive strength (output)
Select ports have interrupt capabilities
PxIE Interrupt enable
PxIES Interrupt edge select
PxIFG Interrupt flag registers
GPIO functionality is multiplexed with analog

and digital peripheral functions
PxSEL Peripheral function select
Port Map Module
14
Port Map Module
5xx Peripherals Port Map Module
Port mapping allows for additional digital signals to be

mapped to one or several output pins.
PM_xxx denotes a por t-mappable signal

Datasheet sp ecifies which por ts can be mapped
By default, single configuration per PUC reset
Port Mapp ing Reconfigure bit (PMRECNFG) allows for

runtim e re-configur ations
Port mapping configuration is password protected
Available on select MSP430 families. (Check the datasheet)
USCI
15
1 - 10
Introduction
Universal Serial Communications Interface

Universal Serial Communications Interface
USCI - New standard MSP430 serial interface

Auto clock start from any low power mode
Two independent communication blocks
Asynchronous communication modes
UART standard and multiprocessor protocols
UART with automatic Baud rate detection
(LIN support)
Two modulators support n/16 bit timing
IrDA bit shaping encoder and decoder
Synchronous communication modes
SPI (Master & Slave modes, 3 & 4 wire)
I2C (Master & Slave modes)
UxRXBUF
Recei ver Shif t
Reg ister
UCLKI
ACLK
SMCLK
SM CLK
URXD
SOM I
Baud -Rate
Gener ator
ST E
SIMO
Tran smit Sh ift

Reg ister
UTXD
UxTXBUF
Clock Phase and Polarity
UCLK
LCD and AES
16
LCD_B and AES128
5xx Peripherals LCD_B & AES128
LCD distinguishes 6xx from 5xx

Static, 2-, 3- or 4-mux displays
Supports up to 196 LCD segments
Blinking of individual segments
Regulated charge pump
Software-driver contrast control
Integrated drivers to decouple LCD
load from the bias generation
Encryption and decryption according to

AES FIPS PUB 197 with 128-bit key
Key expansion for en- and decryption
Off-line key generation for decryption
AES ready interrupt flag
USB
17
1 - 11
Introduction
USB
5xx + USB
Single-chip USB solution

Just add USB connector & TI-supplied USB API software
for the most common device classes (CDC/HID/MSC)
USB + analog + ultra-low-power
+3.3V
V USB
+5V VBUS
PUR
DD+
USB
Module
TPD2E00 1DRL
CPU
Power Supply
& Superv is ion
RAM
DMA
Timers RTC
Clock s
ESD
DVCC
12-bit
ADC
32x32
MPY
Flash
CRC
16
Comparator
Serial
Comms
4MHz
ESD Protection
Diode Arr ay
CC430
18
CC430
5xx + Low-Power RF The CC430

CC430
Supports:
300-348MHz,
387- 464MHz
and 779-928MHz
Low-power
RF SoC
Low Power
RF IC
MSP430
MCU
Radio Frequency
Application &
Protocol
processor
Low Power
< 1 GHz RF
Transceiver
High sensitivity
Low current consumption
Excellent blocking performance
Flexible data rate & modulation format
Backwards compatible
MSP430
5xx MCU
Ultra-low power
High analog performance
High level of integration
Ease of development
Sensor interface
Emulation
19
1 - 12
Introduction
Embedded Emulation
5xx Embedded Emulation
Used for in-system programming and emulation

JTAG access can be locked using SW no fuse
JTAG pins serve as 4 x pin GPIO port (Port J)
Support for both 4-wire and 2-wire Spy-Bi-Wire
Compatible with existing MSP430 tools
Emulation
20
5xx Embedded Emulation
Simplifies in-system debugging and reduces

development time
Up to 8 hardware breakpoints with complex triggering

capabilities
40-bit wide CPU cycle counters in hardware
JTAG Mailbox system provides direct interface to the
CPU during
Debugging (Run-time data UART RTDX)

Programming / Test
State Storage: non-intrusive trace buffer for

data and address bus (e.g., instruction fetch)
Block Diagram
21
1 - 13
Introduction
Block Diagram
MSP430F5438A Block Diagram
MSP-EXP430F5438
22
Experimenters Board
MSP-EXP430F5438
Easy power select
USB communication
Microphone
Filtered PWM audio output
USB, JTAG, Battery
Active, selectable gain

Head phone com patibility
2-axis accelerometer
Dot-matrix LCD (138x110)
Integrated backlight
1 x 5-direction switch
2 x push-button switches
RF Interface
CCxxxx EVMs
EZRF I/F (6 & 18- pin)
Please ensure 2 x AA
batteries are in place on
the back of the board
Load your F5438A into the

socket in the appropriate
orientation
CCS
23
1 - 14
Introduction
Code Composer Studio 4.1
Code Composer Studio v4.1:

A single development
platform for all TI processors
Enhancements:
Speed
Code
size improvements
Auto-updating
License
manager
Support for all TI MCUs
Only $495 for MCU Edition
FREE 16KB-limited edition
Community Support
24
Community Support
Extensive Community Support

E2E Community
Videos,
Blogs, Forums
Extensive community
support and idea exchange
Global customer support
http://e2e.ti.com
Processor Wiki
Growing
collection of
technical wiki articles
Tips & tricks, common
pitfalls, and design
ideas
http://wiki.msp430.com
Lab_1
25
1 - 15
Introduction
*** this page intentionally left blank ***
1 - 16
Lab 1: Setting up the Software and Hardware

Objective
The objective of this lab exercise is to install Code Composer Studio and verify that the hardware
and software has been configured properly. Also, we will cover some of the basic features of the
development tools using a simple program running on the MSP430F5438A. These development
tools will be used with all of the following lab exercises in this workshop.
Hardware / Software Requirements
PC running Windows XP or greater
MSP-FET430UIF with JTAG ribbon cable and USB cable
MSP-EXP430F5438 board with MSP430F5438 device
Labs and solutions files
Lab_1: Blink the LED

FET
Blink the LED

with C code
running on the
MSP430F5438A
Agenda
26
1 - 17
Procedure
If youve already completed the installation steps that were emailed to you before the
workshop, skip to step 9.
Download and Install Code Composer Studio 4.1

1. Click on this link to begin the Code Composer Studio download process. Download the
latest DVD image of Code Composer Studio. You will need to agree to the export
conditions and you will be emailed a link to the installation zip file. Click on the link and
save the zip file to your desktop. Unzip the file into a folder on your desktop named
Setup CCS. You can delete the zip file and the Setup CCS folder when the installation
has completed.
2. Disconnect any evaluation board or FET that you have connected to your PCs USB
port(s).
3. Open the Setup CCS folder on your desktop and double-click on the file named
setup_CCS_n.n.n.n.exe.
4. Follow the instructions in the Code Composer Studio installation program. Select
the Platinum Edition for installation when the Product Configuration dialog
window appears. Click Next.
1 - 18
5. In the Choose ISA dialog, make sure that only the MSP430 checkbox is selected.
Click Next.
In the Select Components dialog, uncheck the Target Content and Emulators
checkboxes then check the MSP430 USB FET checkbox and click Next. Click
Next in the Start Copying Files dialog. The installation should take less than 10
minutes to complete.
1 - 19
Driver Installation
6. Download the workshop installation files from this link on the MSP430 One Day Workshop Wiki site. Unzip the file to your desktop (the folder name is MSP430).
7. In the unzipped MSP430 folder on your desktop, open the USB drivers folder. Doubleclick on setup.exe. Follow the wizard steps until it completes. Then, using Windows Explorer, navigate to C:\Program Files\Texas Instruments Inc\TUSB3410 Single Driver
Installer\DISK1 and double-click on setup. Follow the wizard steps until the driver installation completes.
Lab File Installation

8. Back in the unzipped MSP430 folder on your desktop, open the Labs folder and doubleclick on 5xx_ODW.exe. Leave the unzip directory as C:\5xx_ODW and click Unzip.
When the process completes, click Close. The labs have now been installed in
C:\5xx_ODW.
Hardware Setup
9. Connect the USB cable to the MSP-FET430UIF port marked USB and that the other end
of the cable to your computers USB port. Your computer should recognize the new USB
device.
10. Next, connect the ribbon cable to the MSP-FET430UIF port marked Target and the
other end to the JTAG emulation debug port on the MSP-EXP430F5438 Experimenters
Board.
JTAG Emulation Port
1 - 20
11. The MSP-EXP430F5438 Experimenters Board has several jumpers that control power to
the board:
SW1 JP2 JP3 JP1
JP4 pins 5-6
Be sure that the jumpers are set as follows:
JP1 430 PWR provides power to the MSP430F5438A (ON)

Used to measure current consumption of the MSP430F5438A
JP2 SYS PWR provides power to the entire MSP-EXP430F5438 board (ON)
Used to measure current consumption of the entire board
JP3 RF PWR provides power to the RF connector headers (ON)
JP4 USB RST enable for USB chip (ON)
SW1 FET/USB/BATT power supply switch (FET position)

FET: Power board from FET interface
USB: Power board from USB interface
BATT: Power board from batteries
1 - 21
Start Code Composer Studio

12. On your PC desktop you should have a shortcut that looks like this:
Double-click the shortcut to start Code Composer Studio 4.1. As CCS
loads, the following splash screen will be displayed:
After a few moments, the Workspace Launcher window will appear. In the Workspace
window, enter C:\ 5xx_ODW\workspace and click the OK button on the lower right.
This will create a workspace folder in that location. All of the workshops lab project
folders will be added to this location as we work on them.
1 - 22
13. If you are prompted to review and install updates, click No. When the license dialog
appears, select Evaluate Code Composer for 30 days and click OK.
When the Welcome screen appears, close it by clicking on the CCS emblem in the upper
right corner.
1 - 23
Create a New Project

14. On the menu bar, click File New CCS Project. When the New CCS Project
dialogue appears, name the project Lab_1 and click Next. Note that this location will be
under the workspace folder.
In the Select a type of project window, change the project type to MSP430 and click
Next.
In the Additional Project Settings window, make no changes and click Next.
In the Project Settings window, change the Device Variant to MSP430F5XXX and
select MSP430F5438A and click Finish.
1 - 24
Understanding the IDE Display

15. CCS 4.1 is a highly customizable tool, but your first view of it should look like below:
If the Cheat Sheets pane is open on the right, close it by clicking the X on the tab.
The left-hand pane is the Project pane. All of the components; libraries, source files,
settings, etc. that comprise a project are displayed here. The middle pane is the
Workspace pane. When you are editing, the Eclipse editor will be seen here, along with
tabs to the files being edited. The Outline pane, on the right, displays C/C++ file
elements, like structures, etc.
Click on the + next to Lab_1 to expand the project.
1 - 25
Create and Add a Source File

16. Right-click in the Project pane and select New Source File. When the New Source
File window appears, name the Source File Blink_LED.c and click Finish. In the
Project pane you will see that Blink_LED.c is now added to the project and that the file
is open for editing in the Workspace pane. (If it is not open for editing, double-click on
Blink_LED in the Project pane.)
In the Blink_LED.c editor window that appears, type the following code, or you can
cut/paste it from the Blink_LED.txt file included in the Lab_1 folder.
To cut/paste, select File Open File from the menu bar. Navigate to:
C:\5xx_ODW\Lab_1, select Blink_LED.txt, and then click Open. Cut/Paste to the
Blink_LED.c editor window.
#include
"msp430x54x.h"
void main(void)
{
WDTCTL = WDTPW + WDTHOLD;
// Hold WDT for clock/port config
P1OUT = 0x00;
P1DIR |= BIT0;
// Enable LCD output
WDTCTL = WDT_ADLY_1000;
SFRIE1 |= WDTIE;
// WDT source by ACLK, 1s interval

// Enable WDT interrupt
__enable_interrupt();
// Enable global interrupts
}
// Watchdog Timer interrupt service routine
#pragma vector = WDT_VECTOR
__interrupt void WDT_ISR(void)
{
SFRIFG1 &= ~WDTIFG;
P1OUT ^= 0x01;
// Toggle P1.0 using exclusive-OR
}
On the menu bar, click the Save button
1 - 26
Download and Run the Program

17. Click the Debug button
(not the Debug perspective button). Clicking this button
will compile the source file in your project and download the executable to the flash
memory of the MSP430F5438A.
A Progress Information window will open and inform you of the status of the assembly
and download.
Note: If the FET firmware does not match the CCS version, CCS will automatically
prompt you to update it if you are prompted, select Update.
18. You should now have a screen that looks something like this:
The buttons on the top-left that look like this:
control the running of the code. Click on the Run button

to run the code. You
should notice that the red LED1 near the lower edge of the board is blinking about once
per second.
1 - 27
Halt Debugging and Close the Project

19. Click the Terminate All button
to halt the program, terminate the debugger
session and return to the editor view.
20. Right-click on Lab_1 in the project pane and select Close Project.
Youre done.
1 - 28
Active and Low Power Operation

Introduction
This module will explore the ultra-low power capabilities of the MSP430 architecture. The
Power Management Module (PMM) and Unified Clock System (UCS) will be discussed along
with techniques that are used to minimize power consumption. In the lab exercise we will
experiment with the various active and low power modes.
MSP430 Workshop - Active and Low Power Mode Operation
2-1
Module Topics
Module Topics
Active and Low Power Operation............................................................................................................ 2-1
Module Topics......................................................................................................................................... 2-2
Active and Low Power Operation ........................................................................................................... 2-3
Ultra-Low Power Best Practices......................................................................................................... 2-3
Unified Clocking System (UCS) ........................................................................................................ 2-5
Power Management Module (PMM).................................................................................................. 2-7
Interrupts and the Stack ...................................................................................................................... 2-9
Intrinsics ............................................................................................................................................. 2-9
Fail-Safe Behavior.............................................................................................................................2-10
Available Oscillators .........................................................................................................................2-10
Overview of Lab2 Exercise ...............................................................................................................2-11
Lab 2: Active and Low Power Mode Operation ....................................................................................2-12
Objective ...........................................................................................................................................2-12
Procedure...........................................................................................................................................2-14
2-2

Ultra-Low Power Best Practices
Ultra Low Power (ULP) Operation Best Practices
Power-efficient MSP430 apps:
Minimize instantaneous current draw

Maximize time spent in low power modes
The MSP430 is inherently low-power, but your

design has a big impact on power efficiency
Proper low-power design techniques make the

difference
ULP Best Practices

28
2-3
ULP Operation Best Practices
Power draw increases with
Vcc
CPU clock speed (MCLK)
Temperature
Slowing MCLK reduces instantaneous power, but

usually increases active duty cycle
Power savings can be nullified

The ULP sweet spot that maximizes performance for the
minimum current consumption per MIPS: 8 MHz MCLK
Full operating range (down to 1.8V)
5xx has integrated LDO with variable output voltage

Optimize core voltage for chosen MCLK speed
ULP Best Practices

29
ULP Operation Best Practices
Digital input pins subject to shoot-through current
Input voltages between VIL and VIH cause shoot-through if

input is allowed to float (left unconnected)
Port I/Os should
Driven as outputs
Be driven at Vcc/ground by an external device
Have a pull-up/down resistor
ULP Clock Control (UCS)

30
2-4
Unified Clocking System (UCS)

ULP Clock Control:
Unified Clocking System (UCS) Defaults
FLLREFCLK = XT1CLK
ACLK = XT1CLK
MCLK = DCOCLKDIV
SMCLK = DCOCLKDIV
DCOCKLDIV = DCOCLK / 2
DCO_freq ~= 2 MHz, so
MCLK_freq ~= 1 MHz
SMCLK_freq ~= 1MHz
ULP Clock Control (FLL)

31
ULP Clock Control:

The 5xx Frequency Locked Loop (FLL)
FLLREFCLK sources:
32 kHz internal REFO

LFXT1 / XT1
crystal oscillator
XT2 crystal oscillator
DCO frequency equation

fDCO = (fFLLREFCLK / n) * (N + 1) * D
n = FLLREFDIV
N = FLLN
D = FLLD
ULP Clock Control (DCO)

32
2-5
ULP Clock Control:

The 5xx Digitally Controlled Oscillator (DCO)
DCO ranges from 200 kHz 60 MHz
RSEL bits select the range
DCO bits set one of 32 taps in each range
MOD bits mix two frequencies

fDCO and fDCO+1 to produce DCOCLK
PMM
33
2-6
Power Management Module (PMM)
Power Management Module (PMM)
Integrated Low Dropout (LDO) regulator: VCC ? VCORE

VCORE is programmable to four levels
Brown Out Reset (BOR) is always ON
PMM is password protected
Unlock:
Lock:
PMMCTL_H = 0xA5
PMMCTL_H = 0x00
Integrated Supervision and Monitoring
Monitoring provides interrupts on low voltage condition
Supervision generates Power On Reset (POR) on low voltage

condition
Vcc domain is referred to as the high-side (SVSH, SVMH)
Core voltage domain is referred to as the low-side (SVSL, SVML)
Accurate voltage supervision
200nA - Normal Performance Mode (20 us response time)
2 uA - Fast Performance Mode
(2 us response time)
V core
Supervision and Monitoring
34
Steps to Change VCORE
Increa sing the Core Voltage

1.
Change the low-side monitor threshold
2.
Change the core voltage level
3.
Wait until the core voltage level is reached
4.
Change supervisor threshold to match the monitor level
De creas ing t he Core Voltage

5.
6.
Decrease supervisor and monitor lev els

Decrease the core v oltage level
35
2-7
Voltage Supervision & Monitoring

High -sid e Full Perfo rmance
Mod e
SVS / SVM d isabled
SVS / SVM disa bled

Ze ro-powe r BOR protec tion is
ALWAYS ON
5 us wake up fr om LPM2,3,4
+0 uA active & LPM 2,3 ,4 current
consumption
High-s ide Full Perform ance Mode

Low-side SVS / SVM disabled
+4uA a ctive curre nt cons um ption
+0uA LPM2,3,4 curre nt
consumption
Automatic high-s ide pr ote ction
whe n CPU is active
Maximum Rob ustness

Fas t Per for mance Mode
5 us wakeup from LPM2,3 ,4
+8 uA ac tiv e & LPMx curr ent
c onsumption
5 us wakeup from LPMx
Power on Default Mode

N orm al Per for mance Mode
+800 nA active curr ent
c onsumption
0 nA LPM2 ,3,4 curr ent
c onsumption
High -side Fast Performance

Mod e
High-side Fas t Pe rformance Mode

Low-side SVS / SVM disable d
5 us wak eup from LPM2,3,4
+4 uA active & LPM2,3,4 c ur rent
cons um ption
Autom atic high-side pr otection
when CPU is a ctive
150 us wakeup from LPMx

Cur rent
Entering LPMs
36
Entering Low Power Modes
Interrupts and St ack

37
2-8
Interrupts and the Stack
Interrupts and the Stack

Entering Interrupts
Any currently executing instruction is completed.
The PC, which points to the next instruction, is pushed onto the stack.
The SR is pushed onto the stack.
The interrupt with the highest priority is selected
The interrupt request flag resets automatically on single-source flags.
Multiple source flags remain set for servicing by software.
The SR is cleared. This terminates any low-power mode. Because the
GIE bit is cleared, further interrupts are disabled.
The content of the interrupt vector is loaded into the PC; the program
continues with the interrupt service routine at that address.
Int rinsics
38
Intrinsics
Using Intrinsic Functions to
Program the Status Register (SR)
Intrinsic Functions:
__bi c_ SR_reg iste r(LPM3 _bits);
__bi c_ SR_reg iste r_on_ exit(LPM3 _bits);
__bi s_ SR_reg iste r(LPM3 _bits + GIE);
__bi s_ SR_reg iste r_on_ exit(unsign ed short a);
__ge t_ SR_re giste r(void) ;
__ge t_ SR_re giste r_on _exit(void) ;
__en able _interr upts( ) ;
__di sa ble_i nterrup ts( );
Other useful intrinsics:

__no _op eration ();
__de lay_cycle s(100 0000 );
__bcd _add _short( short, sho rt );
__bcd _add _lon g( long, long ) ;
__eve n_in_ rang e( );
Refer to intrinsics.h or compiler documentation

Fail-Safe
39
2-9
Fail-Safe Behavior
Fail-Safe Behavior & Clock Requests
LFXT1 reverts to REFO

HFXT1 & XT2 revert to DCO
On startup, LFXT1 will fail
because quartz crystals are not
instant-on
Clearing the fault flags allows
expected default operation
Modules place clock requests

to the system clocks
LPM3 entry can be prevented if
a module requires SMCLK to
operate properly
User must be aware of the
clocks required in the system.
Available Oscillators
40
Available Oscillators
ULP Review of Available Oscillators

Clock
Frequency
Precision
Current Draw
DCO
100kHz
60MHz
Low
60uA
HFXT1/
XT2
4 - 32MHz
High
260uA @
12MHz
MODOSC
5MHz
n/a
n/a
Crystal
Required
High-Frequency
Low-Frequency
RTC
LFXT1
VLO
REFO
32kHz
~10kHz
32kHz
High
Low
Medium/High
300nA
60nA
3uA
Lab_2
41
2 - 10
Overview of Lab2 Exercise
Lab2: Active & ULP Mode Operation

Learn and understand how two key modules (PMM &
UCS) achieve ultra low power operation by measuring the
power consumption of various Active and LPM3 scenarios
Using an ammeter and measure the current through
the PWR1 jumper
FET
Agenda
42
2 - 11
Lab 2: Active and Low Power Mode Operation

Objective
The objective of this lab exercise is to gain an understanding on how two key modules of the
MSP430F5438A are used to achieve ultra-low power operation. The Power Management
Module (PMM) and Unified Clock System (UCS) will be configured and modified as we measure
the typical average current consumption of the device in the following active and LPM3
scenarios:
Active running at 8 MHz initialize the FLL
Active running at 25 MHz change the COREV levels for greater than 8 MHz
operation
LPM3 REFO- enter LPM3 with default ACLK settings
LPM3 LFXT1 handle oscillator faults to set LFXT1 ACLK
LPM3 VLO evaluate ultra-low power tradeoffs for oscillators at VLO ACLK
The LPM3 applications blink the LED on and off every 3 seconds. After you have verified that
the application download and function, you can comment out the line P1OUT ^= ~BIT0; . This
will allow you to measure the current without the spikes due to the LED.
2 - 12
In the Active Running scenarios (first two in the box above) a function is called to provide a
current consumption test. This test includes a mix of various MSP430 instructions (type I, II,
JMP, emulations, etc.) and uses various MSP430 addressing modes. The function is called from
C with the following code:
// Call active mode current consumption test
ACTIVE_MODE_TEST();
ACTIVE_MODE_TEST ( ) is written in assembly and consists of the following:
ACTIVE_MODE_TEST
IDD_AM_L1
.global
.text
MOV
MOV
MOV
ADD
SWPB
MOV
; run 8
XOR
DEC
JNZ
JMP
.end
ACTIVE_MODE_TEST
#0x2000, R4
#0x4, 0(R4)
&0x2000, &0x2002
@R4, 2(R4)
@R4+
@R4, R5
times
@R4+, &0x2020
R5
IDD_AM_L1
ACTIVE_MODE_TEST
- Code mixes with types of instructions: type I,II, JMP, emu

- Code mixes with address modes
- Type of Instructions
# of instructions:
6+8*3 = 30
ALU inst:
2+2*8 = 18
-60%
Data Read inst:
4+1*8 = 12
-40%
Data Write inst:
-40%
Control/Jump :
8
-26%
2 - 13
Procedure
Import CCS Project
1. Import the CCS project for this lab exercise by clicking:
Project Import Existing CCS/CCE Eclipse Project
Then in the Import dialog window click Browse and navigate to: C:\5xx_ODW\ Lab_2.
Select Lab_2 in the Projects box, check the Copy projects into workspace checkbox
and click Finish.
In the Project pane of CCS, click the plus sign (+) to the left of Lab_2 and notice the
files are listed for the various low power measurement scenarios. Note that the
ACTIVE_8_MHZ.c file is included in the build.
2 - 14
Active Running at 8 MHz

In this scenario we will measure current consumption of the device in the active mode
running at 8 MHz.
2. Be sure that Lab_2 is set as the [Active ACTIVE_8_MHZ] build configuration. If
not, then right-click in the Project pane, select Active Build Configuration and left-click
ACTIVE_8_MHZ.
3. Open ACTIVE_8_MHZ.c for editing and notice the following:
halBoardInit( ) initializes the GPIO for minimum current consumptions and

ultra-low power operation
Init_FLL_Settle( ) selects the RSEL, DCO taps, delay for FLL to settle, and
MCLK, SMCLK, ACLK sources
For future reference:
Check out #include hal_ucs.h
Check the MSP430 application notes for hal_UCS and hal_PMM library
descriptions
4. Click the Debug

button to assemble/compile and download the executable into the
device flash memory.
5. Click the Run
button to run the program, then click the Terminate All
button
to halt the program, terminate the debugger session, and return to the C/C++ perspective.
6. Disconnect the 14-pin JTAG cable from the Experimenters board.
7. Be sure that the batteries are in place on the underneath of the Experimenters board and
move the SW1 FET/USB/BATT power supply switch to BATT.
SW1 JP2 JP3 JP1
8. Turn on your multimeter and set it to a range that can measure <10mA. (Be sure that the
leads are connected to the proper jacks to read current).
9. Remove and save the JP1 MSP430 PWR jumper and connect the multimeter leads to
the header with the red lead closest to the edge of the board.
2 - 15
10. Measure the current consumption:__________ (It should be between 1.9 mA 2.1 mA).
11. Some further information:
Since the CPU performs a 32-bit fetch, code alignment can impact current consumption
significantly
2 - 16
Active Running at 25 MHz

In this scenario we will change the core voltage levels for operation greater than 8 MHz and
measure current consumption of the device in the active mode running at 25 MHz.
12. Disconnect and turn off your multimeter. Reconnect the JP1 MSP430 PWR jumper,
and the 14-pin JTAG cable. Move the SW1 FET/USB/BATT power supply switch to
FET.
13. Right-click in the CCS Project pane and select Active Build Configuration. Left-click
ACTIVE_25_MHZ. Lab_2 should now be set as the [Active ACTIVE_25_MHZ]
build configuration.
14. Open ACTIVE_25_MHZ.c for editing and notice the following:
SetVCore(PMMCOREV_3) is used to set one level at a time - <hal_pmm.c>

//***********************************************************//
// Set VCore
//**********************************************************//
unsigned int SetVCore (unsigned char level)
{
unsigned int actlevel;
unsigned int status = 0;
level &= PMMCOREV_3;
actlevel = (PMMCTL0 & PMMCOREV_3);
// step by step increase or decrease
while (((level != actlevel) && (status == 0)) || (level < actlevel))
{
if (level > actlevel)
status = SetVCoreUp(++actlevel);
else
status = SetVCoreDown(--actlevel);
}
return status;
}
SVSx & SVMx management turns off SVSL and SVSM, leaves SVSH in full
performance mode, and delivers fast wake-up (5 s) time with SVS protection on
DVcc
15. Click the Debug

All
button, click the Run
button and then click the Terminate
button.
16. Disconnect the 14-pin JTAG cable from the Experimenters board and move the SW1
FET/USB/BATT power supply switch to BATT.
17. Turn on your multimeter and set it to a range that can measure <10mA. (Be sure that the
leads are connected to the proper jacks to read current).
19. Measure the current consumption:__________ (It should be between 7.1 mA 8.3 mA).
2 - 17
LPM3 REFO Mode

In this scenario we will enter the LPM3 mode with the default ACLK settings and measure
current consumption of the device when the internal 32 kHz REFO clock sources ACLK.
FET.
21. In the CCS Project pane, set LPM3_REFO as the active build configuration.
22. Open LPM3_REFO.c for editing and notice the following:
Entering LPM3 using intrinsic functions

__bis_SR_register(LPM3_bits + GIE);
__no_operation();
// Enter LPM3, enable interrupts

// For debugger
Watchdog triggers an interrupt approximately every 3 seconds

/* Initialize WDT to interval timer mode, triggering every 3 seconds */
WDTCTL = WDTPW+WDTSSEL__VLO+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0;
SFRIE1 |= WDTIE;
// Enable WDT interrupt
Return from ISR using intrinsic function

// Watchdog Timer interrupt service routine
#pragma vector = WDT_VECTOR
__interrupt void WDT_ISR(void)
{
__bic_SR_register_on_exit(LPM3_bits);
}
23. Click the Debug

All
button.
26. Turn on your multimeter and set it to the lowest DC milliamp measurement range. (Be
sure that the leads are connected to the proper jacks to read current).
27. LED1 on the Experimenters board will blink ON and OFF if the program is running
correctly.
28. Measure the current consumption while LED1 is OFF:__________ (It should be
between 4.3 A 4.9 A).
2 - 18
LPM3 LFXT1 Mode

In this scenario we will handle oscillator faults to set LFXT1 ACLK and measure current
consumption of the device when the internal 32 kHz crystal on the LFXT1 oscillator sources
ACLK.
FET.
30. In the CCS Project pane, select LPM3_LFXT1 as the active build configuration.
31. Open LPM3_LFXT1.c for editing and notice the following:
Initializing crystal pins and LFXT_Start( );

/* Initialize LFXT1 */
P7SEL |= BIT1+BIT0;
LFXT_Start(XT1DRIVE_0);
LFXT_Start (XT1DRIVE_0);
// Enable crystal pins
<hal_UCS.c>
void LFXT_Start(unsigned int xtdrive)

{
UCSCTL6_L |= XT1DRIVE1_L+XT1DRIVE0_L; // Highest drive set - XT1 startup
while (SFRIFG1 & OFIFG) {
// check OFIFG fault flag
UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clr OSC flt flags
SFRIFG1 &= ~OFIFG;
// Clear OFIFG fault flag
}
UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) |(xtdrive); // set Drive mode
}
32. Click the Debug

All
button.
correctly.
2 - 19
LPM3 VLO Mode

In this scenario we will evaluate the tradeoffs for oscillator at VLO ACLK and measure
current consumption of the device when VLO sources ACLK.
FET.
39. In the CCS Project pane, select LPM3_VLO as the active build configuration.
40. Open LPM3_VLO.c for editing and notice the following:
ACLK clock source selection

SELECT_ACLK(SELA__VLOCLK);
Other UCS_Library macros
41. Click the Debug

All
// Select VLO_CLOCK to source ACLK
button.
correctly.
Halt Debugging and Close the Project

47. Turn off your multimeter.
48. Right-click on Lab_2 in the CCS Project pane and select Close Project.
Youre done.
2 - 20
Analog Peripherals
Introduction
This module will discover the mixed-signal capability of the MSP430 architecture and learn
about its effect on low power operation. In the lab exercise we will measure an analog signal
using the integrated temperature sensor, perform an analog-to-digital conversion, and send the
results over a USB link to a CCS4 terminal window.
MSP430 Workshop Analog Peripherals
3-1
Module Topics
Module Topics
Analog Peripherals.................................................................................................................................... 3-1
Module Topics......................................................................................................................................... 3-2
Analog Peripherals ................................................................................................................................. 3-3
Comp_B Analog Comparator ............................................................................................................. 3-3
ADC12_A........................................................................................................................................... 3-4
Conversion Memory and Control ....................................................................................................... 3-5
Lab 3 Overview .................................................................................................................................. 3-6
Lab 3: Brute-Force Temperature Sampling............................................................................................ 3-8
Objective ............................................................................................................................................ 3-8
Procedure............................................................................................................................................ 3-9
3-2
Analog Peripherals
Analog Peripherals
Comp_B Analog Comparator
Comp_B Analog Comparator

Inverting and noninverting terminal
input multiplexer
Software-selectable RC filter for the
comparator output
Output provided to Timer_A capture
input
Interrupt capability
Selectable reference voltage
generator and voltage hysteresis
generator
Reference voltage input from shared
reference
Ultra-low-power comparator mode
ADC12_A
44
3-3
Analog Peripherals
ADC12_A
ADC12_A Features
12-bits, SAR, 200 ksps+
Timer_A/B, software
triggers
Up to 12 external input
Conversion Modes:
Single
Sequence
Repeat-single
Repeat-sequence
Internal/external
reference
16 conversion result
storage
Input range: Vss Vref

ADC12_A
45
ADC12_A Enhancements
VREF settling time
Tighter temp coefficient on

internal reference
75us vs. 17ms
50ppm vs. 100ppm
Lower power modes
Selectable speed vs power
ADC12_A core is only enabled

when needed
Higher clock dividers for

faster system clocks
~6x lower current than ADC12
150uA for ADC active
100uA for 2.5V VREF active
Temp and Vcc

46
3-4
Analog Peripherals
ADC12 Temperature & Vcc Sampling
On-chip temperature sensor channel

On-chip Vcc/2 channel
The temperature sample period > 30
us
Temp sensor offset voltage is large
and must be calibrated
2-point calibration data inside

Factory Application Data
Conversion Memory and Control

47
Conversion Memory and Control
ADC12 Conversion Memory & Control
Each memory register is configurable
EOSx Identifies the end of a sequence-of-conversions.
When the conversion result is written into the EOS

ADC12MEMx register, the interrupt will be triggered.
SREFx Selects the reference (internal, external, etc)

INCHx Selects input channel for the ADC12MEMx register
Input channels can be mixed for a sequence-ofconversions

Lab 3 Flowchart
48
3-5
Analog Peripherals
Lab 3 Overview
Lab 3: Brute-force Temperature Sampling
Lab 3 code
49
Lab 3.c Code

while(1){
REFCTL0 |= REFON;
__delay_cycles(85);
ADC12CTL0 |= ADC12ENC+ADC12SC;
// Enable internal reference

// Settling time for reference
// (Re)enable & trigger conversion
// Poll IFG until ADC12MEM1 loaded signifying sequence is complete

while(!(ADC12IFG & BIT1));
ADC12CTL0 &= ~ADC12ENC;
REFCTL0 &= ~REFON;
temp_temp = ADC12MEM0;
temp_vcc = ADC12MEM1;
//
//
//
//
Disable conversions to configure REF

Disable internal reference
Read ADC12 temperature conversion
Read ADC12 Vcc/2 conversion
// Calculate temperature in degrees Celsius & format display string accordingly

...
// Calculate temperature in degrees Fahrenheit & format display string accordingl
...
// Calculate Vcc in volts & format display string accordingly
...
/* Initialize serial communication module to send data over USB */
halUsbInit();
halUsbSendString(&USB_string[0],USB_STRING_LEN+2);
halUsbShutDown();
// Shut down USB to enter sleep mode
__delay_cycles(2200000);
// Delay 2 seconds
}
}
Alphabet Soup
50
3-6
Analog Peripherals
Decoding the Alphabet Soup

void halADCInit(void){
ADC12CTL0 = ADC12SHT0_7 + ADC12ON + ADC12MSC;
ADC12CTL1 = ADC12CONSEQ_1+ADC12SHP;
ADC12MCTL0 = ADC12SREF_1 + ADC12INCH_10;
ADC12MCTL1 = ADC12SREF_1 + ADC12INCH_11 + ADC12EOS;
REFCTL0 |= REFMSTR + REFVSEL_1;
}
(msp430x54xA.h file)
(User Guide)
Lab 3 Power
51
540 uA
Curre nt
Lab 3 Power
Active
A DC
= 150uA
A ctive
ADC
= 150uA
3 90uA
1. 5V Internal Ref erence = 100uA
2 90uA
75us
80us
Active MCLK
@1MHz=290uA
Time
2 seconds until next Sample
CPU
is ALWAYS ON (~290 uA)

Delay between ADC12 samples executed by software
ADC12
handled completely in software
Reference settling, Software trigger, IFG polling

Lab 3
52
3-7
Lab 3: Brute-Force Temperature Sampling

Objective
The objective of the next three lab exercises (Lab 3 though Lab 6) is to gain an understanding on
how the ultra-low power features of the MSP430F5438A compare in a mixed-signal application.
In all three cases we will perform the same application task measure an analog signal using
the integrated temperature sensor, perform an analog-to-digital conversion, and send the results
over a USB link to a CCS4 terminal window. Each case will show significant differences in
power consumption:
Lab 3 implements brute-force temperature sampling with the ADC12_A. This
implementation had no interrupts, all CPU delays and flag polling. Current draw was
about 300 uA.
Lab 4 will use timer interrupts. We will handle the two second delay with a hardware
timer interrupt. This will prove to be the most significant decrease in power
consumption.
Lab 5 will be a fully optimized ADC12 routine. We will use the ADC12 interrupts to
signify end-of-conversion. The timer will automatically handle the reference settling
time as well as trigger the ADC12 sampling. This will maximize the time that the
CPU spends in LPM3.
Lab 3: Using the ADC12
Use ADC12 integrated temperature sensor

Set up ADC12 to perform a single conversion
Loop continuously, converting to Degrees F and C in software
Touch the F5438A with a finger to change the temperature
Open a watch window in the debugger to see the temperature values
FET
Agenda
53
3-8
Procedure
Import CCS Project
1. Import the CCS project for the next three lab exercises by clicking:
Project Import Existing CCS/CCE Eclipse Project
In the Import dialog window click Browse and navigate to the C:\5xx_ODW folder and
select OK. Next, in the Projects window check Lab_3, Lab_4, and Lab_5 (be sure all
three labs are selected). Then check the Copy projects into workspace checkbox and
click Finish.
2. Set Lab_3 as the [Active Lab3] project by right-clicking on Lab_3 in the Project pane
and selecting Set as Active Project. Click the plus sign + to the left of Lab_3 and
notice the files are listed for the project.
Determine COM port for MSP-EXP430 Board

3. Connect the small size connector of the USB-to-miniUSB cable to the
MSP-EXP430F5438 Experimenters board and the other end to the USB port on your
computer.
4. Determine the COM port used for the board by clicking (in Windows) Start Run then
type devmgmt.msc in the box and select OK. (In Windows 7, just type into the Search
programs and files box)
In the Device Manager window that opens, left-click the symbol left of
Ports (COM & LPT) and record the COM port number for
MSP-EXP430F5438 USB Serial Port (COMxx):________. Close the Device
Manager.
3-9
Examine, Download, and Run Code

5. Back in CCS, open Lab_3_soln.c for editing and notice the code used to calculate the
temperature and voltage. The code that follows is used to format the data for displaying.
At the bottom notice the code used to initialize the ADC12:
// 5.4MHz (MODOSC_max) * 30 us (t_sensor)= 162 cyc min samp time
ADC12CTL0 = ADC12SHT0_7 + ADC12ON+ADC12MSC;
ADC12CTL1 = ADC12CONSEQ_1+ADC12SHP;
ADC12MCTL1 = ADC12SREF_1 + ADC12INCH_11 + ADC12EOS;
/* Initialize the shared reference module */
REFCTL0 |= REFMSTR + REFVSEL_0;
// Configure internal 1.5V ref
}
ADC12SHT0_7 selects sample and hold time = 192 ADC12CLK cycles
t_sensor must be > (5.4 MHz (MODOSC_max) * 30 us (t_sensor) = 162 cycles)
ADC12MSC selects multiple sample and conversion so multiple conversions

are performed automatically (only a single trigger per SOC is required)
ADC12SHP is the sample-and-hold signal select which selects SAMPCON

to be sourced from sampling timer (~5 MHz MODOSC)
ADC12SREF_1 selects the internal reference as the reference for

ADC12MEM channels 0 and 1
ADC12INCH_x is the input channel select (x = 10 for the temperature

sensor; x = 11 for Vcc/2)
ADC12EOS identifies channel 11 as the end-of-sequence of conversions
REFMST disables backwards compatibility mode to leverage REF module
REFVSEL selects 1.5V reference
To understand how the above code example works, first the bit field descriptions are
found in the Users Guide:
3 - 10
And the bit fields are defined in msp430f5438a.h :
6. Turn on your multimeter and set it to a range that can measure about 300uA. Click the
button to assemble/compile and download the executable into the device
Debug
flash memory.
7. Click the Run
button to run the program.
Open a CCS4 Terminal Window

8. Make sure the code has been downloaded and running. In CCS select:
Window Show View Other
In the Show View box, left-click the plus sign + next to Terminal. Click on Terminal
and select OK. A terminal window will appear.
button. In the Terminal
9. On the right side of the terminal pane ,click the Settings
Settings window that appears, configure the Connection Type as Serial using the pulldown tab.
10. Make the following changes to the Terminal Settings and then click OK.
Port:
COMxx as recorded in step 4
Baud Rate:
9600
Data Bits:
Stop Bits:
Parity:
none
Flow Control:
none
Timeout (sec):
11. Now you should see scrolling temperature (in C and F) and the voltage in the Terminal
pane. Verify the temperature reading changes in the terminal window by placing your
finger or breathing on the MSP430 device on the board.
3 - 11
Current Measurement
13. Click the Disconnect
button in the Terminal pane and disconnect the USB-tominiUSB cable from your PCs USB port.
14. Observe the current consumption. Because of the timer delay and the meters inability to
read quickly changing currents, your readings will jump around
In this application the CPU is always on.
The delay between ADC12 samples is executed by software

// Delay 2 seconds
ADC12 is handled completely in software (i.e. reference settling, software

trigger, IFG polling)
15. Turn off your multimeter and reconnect the 14-pin JTAG cable and the USB-tominiUSB cable.
16. Click the Terminate All
button.
Youre done.
3 - 12
Hardware Timers
Introduction
This module will discuss the features of the MSP430 hardware timers. Many microprocessors
incorporate timer to generate simple time intervals. The timers on the MSP430 include additional
capabilities for generating PWM waveforms, controlling the ADC hardware, and even implement
UART communication functions. In the lab exercise we will build on the previous exercise and
use the hardware timers to conserve power.
MSP430 Workshop Hardware Timers
4-1
Module Topics
Module Topics
Hardware Timers ...................................................................................................................................... 4-1
Module Topics......................................................................................................................................... 4-2
Hardware Timers .................................................................................................................................... 4-3
Timer Architecture ............................................................................................................................. 4-3
Counting Modes ................................................................................................................................. 4-4
Interrupts ............................................................................................................................................ 4-4
Timer_B vs Timer_A.......................................................................................................................... 4-5
Lab 4 Details....................................................................................................................................... 4-6
Lab 4: Using Hardware Timers to Conserve Power............................................................................... 4-7
Objective ............................................................................................................................................ 4-7
Procedure............................................................................................................................................ 4-8
4-2
HaTrdware Timers
Hardware Timers
Timer Architecture
Timer Architecture
Asynchronous 16-bit
timer/counter
Continuous, up-down,
up count modes
Multiple
capture/compare
registers
PWM outputs
Interrupt vector register

for fast decoding
Can trigger DMA

transfer
On all MSP430s
Timer Modes
55
4-3
HaTrdware Timers
Counting Modes
Timer Counting Modes
Interrupts
56
Interrupts
Timer_B Interrupts
The Timer_B Capture/Comparison Register 0 Interrupt Flag
(TBCCR0) generates a single interrupt vector:
TBCCR0 CCIFG
No handler is required
TIMERB0_VECTOR
TBCCR1-6 and TB interrupt flags are prioritized and combined

using the Timer_B Interrupt Vector Register (TBIV) into another
interrupt vector
TBCCR1 CCIFG
TBCCR2 CCIFG
TBIV
TIMER_B1_VECTOR
TBIFG
Your code must contain a handler to determine which Timer_B
interrupt triggered
The same applies to Timer_A
B vs A
57
4-4
HaTrdware Timers
Timer_B vs Timer_A
Timer_B vs Timer_A
Default function identical to Timer_A
8, 10, 12, or 16-bit timer or counter (16-bit only for Timer_A)
Outputs double-buffered for simultaneous loading
CCRx registers can be grouped for simultaneous updates
Tri-state function from external pin
Lab 4 Flowchart
58
4-5
HaTrdware Timers
Lab 4 Details
Lab 4 Temperature Measurement with Timer

Main loop
Timer CCR0 ISR
Lab 4 Power
59
54 0uA
Curr ent
Lab 4 Power
Active
ADC
= 150uA
Acti ve
ADC
= 150uA
390u A
290u A
75us
80us
Active MCLK
@1MHz=290uA
2.1uA
Time
2 seconds until next Sampl e
CPU is in LPM3 most of the time
Delay between ADC12 samples handled by

hardware
ADC12 handled completely in software
Reference settling, Software trigger and IFG polling

Lab 4
60
4-6
Lab 4: Using Hardware Timers to Conserve Power

Objective
In this lab exercise we will perform the same application task as the previous exercise, but we
will make use of Low Power Mode 3 to reduce power consumption. Timer B will be configured
to count in up-mode and trigger an interrupt which will replace the two second software delay
used in the previous lab exercise. Also, Timer B CCR0 interrupt service routine (ISR) will
software trigger an ADC12 sample/conversion. These modifications will provide the most
significant decrease in power consumption.
Lab 4: Using Hardware Timers to

Conserve Power
Perform same task as previous lab exercise, but use LPM3 to
reduce power consumption
Timer B will be used to replace the 2 second software delay
FET
Agenda
61
4-7
Procedure
Set Active Project and Check COM Port Connection
1. Set Lab_4 as the [Active Lab 4] project by right-clicking on Lab_4 in the Project
pane and selecting Set as Active Project. Click the minus sign (-) next to Lab_3 to
collapse the Lab_3 project. Click the plus sign (+) next to Lab_4 and notice the files are
listed for the project.
2. Make sure that the small size connector of the USB-to-miniUSB cable is connected to the
MSP-EXP430 board and the other end to the USB port on your computer. Also make
sure your emulator cables are properly connected.

3. Close any open editor panes. Open Lab_4_soln.c for editing and notice the code used to
integrate LPM3, the Timer_ISR ( ), and initialize a Timer_B to trigger a periodic wakeup using a timer capture event:
Integrate LPM3 into the code

// Bit-set (LPM3_bits + GIE) in SR register to enter LPM3 mode
__bis_SR_register(LPM3_bits + GIE);
__no_operation();
Timer_ISR( )
Handle the ADC12_A reference enable and software trigger

Clear the LPM3 bits in SR register on stack to exit active from the ISR
// Timer B0 CCR0 interrupt service routine

#pragma vector=TIMER0_B0_VECTOR
__interrupt void TIMER0_B0_ISR(void)
{
REFCTL0 |= REFON;
// Enable internal 1.5V ref
__delay_cycles(85);
// 1.5V REF settling time
ADC12CTL0 |= ADC12ENC+ADC12SC;
// (Re)enable & trig conv
}
Init Timer_B to trigger a periodic wake-up using a timer capture event

void halTimerInit(void)
{
TB0CCR0 = 65535;
TB0CCTL0 = CCIE;
TB0CTL
= TBSSEL_1 + MC_1 + TBCLR;
// CCR0 interrupt enabled

// ACLK, upmode, clr TBR
Debug
flash memory.
5. Click the Run
4-8
Connect the Terminal

6. Click the Terminal tab on the right of your screen, then click the Connect
Right-click in the Terminal pane and select Clear All.
button.
7. You should see scrolling temperature (in C and F) and the voltage in the Terminal
Current Measurement
9. Click the Disconnect
button in the Terminal pane and disconnect the USB-tominiUSB cable from your PCs USB port.
In this application the CPU is in LPM3 most of the time.
The delay between ADC12 samples is handled by hardware
ADC12 is handled completely in software (i.e. reference settling, software

trigger, IFG polling)
4-9
11. Turn off your multimeter and reconnect the 14-pin JTAG cable and the USB-tominiUSB cable.
button.
Youre done.
4 - 10
Optimized ULP ADC12 Routine

Introduction
This module will discuss how to optimize the data acquisition capability of the MSP430 ADC for
ultra-low power operation. In the lab exercise optimize the routine by keeping the CPU inactive
most of the time and only activating it when needed.
MSP430 Workshop - Optimized ULP ADC12 Routine
5-1
Module Topics
Module Topics
Optimized ULP ADC12 Routine.............................................................................................................. 5-1
Module Topics......................................................................................................................................... 5-2
Optimized ULP ADC12 Routine ............................................................................................................. 5-3
Timer Output and Triggering.............................................................................................................. 5-3
Timer_B Interrupts ............................................................................................................................. 5-4
Handler ............................................................................................................................................... 5-4
Interrupt Control................................................................................................................................. 5-5
How to Write the ADC12IFG1 Handler............................................................................................. 5-5
Lab 5 Code ......................................................................................................................................... 5-6
Lab 5 Power........................................................................................................................................ 5-6
Lab 5: Fully Automated ADC12 Routine ................................................................................................ 5-7
Objective ............................................................................................................................................ 5-7
Procedure............................................................................................................................................ 5-8
5-2

Timer Output and Triggering
Timer Output Continuous Mode
Each CCRx register can be used in the different timer modes to

generate interrupt flags
Independent PWM frequencies with different duty cycles can be
automatically generated in continuous mode using CCR0 and CCR1+
A new interrupt (TAIFG or TBIFG) occurs on every rollover of the timer
Continuous Mode
Timer Triggering ADC12

63
Timer-Triggering the ADC12
Power Optimization:
Currently: Tim er delays for 2 seconds, software ADC12 trigger
Optimization: Timer delays for 2 seco nds, then:
[1] En ables reference on TBIF G r ollover

[2] Trigger s ADC12 sample/conversion u sing TBCCR1 output
SHP bit selects whether the sample time is set by:

TBCCR1 outp ut (SHP = 0)
SHT0x * ADC12CLK [ lab uses SHT0x * ADC12CLK cycles (192 x 1/5MHz ~= 40 us)]
Time between TBIFG and TBCCR1 must be > 75 us for 2.0V REF to stabilize
Timer Interrupts
64
5-3
Timer_B Interrupts
Timer_B Interrupts
The Timer_B Capture/Comparison Register 0 Interrupt Flag
(TBCCR0) generates a single interrupt vector:
TBCCR0 CCIFG
TIMERB0_VECTOR
TBCCR1-6 and TB interrupt flags are prioritized and combined

using the Timer_B Interrupt Vector Register (TBIV) into another
interrupt vector
TBCCR1 CCIFG
TBCCR2 CCIFG
TBIV
TIMER_B1_VECTOR
TBIFG
Handler
65
Handler
TB0IV Handler Example

TB0IV
0 0 0 0 0 0 0 0 0 0 0 x x x x 0
15
0
Highest-priority IFGs cleared

when TB0IV is read
#pragma
#pragma vector
vector == TIMER0_B1_VECTOR
TIMER0_B1_VECTOR
__interrupt
__interrupt void
void TIMER0_B1_ISR(void)
TIMER0_B1_ISR(void)
{{
__even_in_range(TB0IV,10))
switch(
switch(__even_in_range(TB0IV,10))
{{
case
//
case 22 ::
// TBCCR1
TBCCR1 CCIFG
CCIFG
P1OUT
P1OUT ^=
^= 0x04;
0x04; break;
break;
case
4
:
//
TBCCR2
CCIFG
case 4 :
// TBCCR2 CCIFG
P1OUT
P1OUT ^=
^= 0x02;
0x02; break;
break;
case
//
case 10
10 ::
// TBIFG
TBIFG
P1OUT
P1OUT ^=
^= 0x01;
0x01; break;
break;
}}
}}
Source
TAIV Contents
No interrupt pending
0
02h
TBCCR1 CCIFG
04h
TBCCR2 CCIFG
06h
Reserved
08h
Reserved
0Ah
TBIFG
0Ch
Reserved
0Eh
Reserved
0xF814
0xF814
0xF818
0xF818
0xF81A
0xF81A
0xF81C
0xF81C
0xF81E
0xF81E
0xF820
0xF820
0xF822
0xF822
0xF824
0xF824
0xF828
0xF828
0xF82A
0xF82A
0xF82E
0xF82E
0xF830
0xF830
0xF834
0xF834
add.w
add.w
reti
reti
jmp
jmp
jmp
jmp
reti
reti
reti
reti
jmp
jmp
xor.b
xor.b
reti
reti
xor.b
xor.b
reti
reti
xor.b
xor.b
reti
reti
&TB0IV,PC
&TB0IV,PC
0xF824
0xF824
0xF82A
0xF82A
0xF830
0xF830
#0x4,&P1OUT
#0x4,&P1OUT
#0x2,&P1OUT
#0x2,&P1OUT
#0x1,&P1OUT
#0x1,&P1OUT
Interrupt Control
66
5-4
Interrupt Control
ADC12 Interrupt Control
Power
optimization:
Currently:
Optimization:
Polling for ADC12MEM1IFG

Enable ADC12MEM1IFG interrupts & wake CPU
only to handle conversion data
ADC12
Interrupt Enable (ADC12IE) bits enable interrupt request

on a write to the respective ADC12MEMx register
ADC12MEM1 has EOS set, so interrupt will be requested after the
sequence of temperature and vcc/2 conversions is complete
Reading the ADC12MEMx register clears the respective interrupt
flag
ADC12IFG1 Handle r
67
How to Write the ADC12IFG1 Handler
How to Write the ADC12IFG1 Handler
sw itc h(_ _eve n_i n_r ange(AD C12 IV, 36) )

{
ca se 0: b rea k;
// N o i nterru pt
ca se 2: b rea k;
// O ver flow
ca se 4: b rea k;
// T ime overf low
ca se 6: b rea k;
// A DC1 2MEM0I FG
ca se 8:
// A DC1 2MEM1I FG
Dis able RE F & ADC12 sam ples;
Rea d AD C12 MEM 0 & ADC 12M EM1;
Exi t ac tiv e t o main( );
bre ak;
ca se 36: bre ak;
}
Lab 5 Code
68
5-5
Lab 5 Code
Lab 5 Code
Main
ADC12MEM1 ISR
Timer Overflow ISR
Lab 5 Power
69
Lab 5 Power
Curr ent
Lab 5 Power
252 uA
Acti ve
ADC
= 150uA
A ctive
ADC
= 150uA
102 uA
2 .1 uA
Time
2 seconds until next Sampl e
CPU is no longer active during:
ADC12 reference settling

ADC12 sampling
ADC12ISR wakes CPU for very short time:
Entry/exit to ISR
Disables the reference
Stores the ADC12MEM0 & ADC12MEM1 values
Wakes active on exit from LPMx
Lab 5
70
5-6
Lab 5: Fully Automated ADC12 Routine

Objective
In this lab exercise we will perform the same application task as the previous exercise, but we
will use a fully automated ADC12 routine which will optimize the data acquisition for ultra-low
power consumption. To minimize power consumption the CPU will not be active during the
ADC12 reference settling and sampling. The ADC12ISR will wake the CPU for a very short
period of time on entry/exit of the ISR and storing the ADC12MEM0 and ADC12MEM1 results.

Perform same task as previous lab exercise, but use Timer B
in continuous mode to trigger TBIFG interrupt and generate
TBCCR1 output
Time between TBIFG and TBCCR1 will automatically handle
internal reference settling time
FET
Agenda
71
5-7
Procedure
Set Active Project and Check COM Port Connection
1. Set Lab_5 as the [Active Lab 5] project by right-clicking on Lab_5 in the Project
pane and selecting Set as Active Project. Click the minus sign (-) next to Lab_4 to
collapse the Lab_3 project. Click the plus sign (+) next to Lab_5 and notice the files are
listed for the project.
2. Make sure that the small size connector of the USB-to-miniUSB cable is connected to the
MSP-EXP430 board and the other end to the USB port on your computer. Also make
sure your emulator cables are properly connected.

3. Close any open editor panes. Open Lab_5_soln.c for editing and notice the code used to:
Put TimerB into continuous mode, set/reset output mode on CCR1, enable TBIFG
interrupts, and trigger CCR1 rising edge > 75 s (t_ref_settle) after TBIFG ISR
turns on the reference
void halTimerInit(void)
{
TB0CCR0
= 65535;
TB0CCR1
= 3;
// 3 x 1/32768kHZ = 91us
TB0CCTL1 = OUTMOD_3;
// CCR1 output mode to TB0CCR1
// ACLK, continuous mode, clear TBR
TB0CTL
= TBSSEL_1 + MC_2 + TBCLR + TBIE;
}
Initialize ADC12_A to trigger an interrupt when conversion is complete

// 5.4MHz (MODOSC_max) * 30 us (t_sensor)= 162 cycles min sampling time
ADC12CTL0 = ADC12SHT0_7+ADC12ON+ADC12MSC;
// Set samp time to 192 cyc
// Enable TB0.OUT1 as ADC trigger (ADC12SHS_x), enable seq-chan
ADC12CTL1 = ADC12SHS_3+ADC12CONSEQ_1+ADC12SHP;// En seq-chan & samp tim
// ADC inchA10 => temp sense
ADC12MCTL1 = ADC12SREF_1 + ADC12INCH_11 + ADC12EOS;// ADC inchA11 => Vcc
ADC12IE |= BIT1;
// Enable ch ADC12MEM1IFG interrupts
/* Initialize the shared reference module */
REFCTL0 |= REFMSTR + REFVSEL_0 + REFON;
// Config int 1.5V ref
ADC12CTL0 |= ADC12ENC;
// Disable conv to config REF
}
5-8
Timer ISR enables the reference and conversions

/ Timer B0 overflow interrupt service routine
#pragma vector=TIMER0_B1_VECTOR
__interrupt void TIMER0_B1_ISR(void)
{
switch(__even_in_range(TB0IV,14))
{
case 0: break;
// No interrupt
case 2: break;
// TB0CCR1 not used
case 4: break;
// TB0CCR2 not used
case 6: break;
// TB0CCR3 not used
case 8: break;
// TB0CCR4 not used
case 10: break;
// TB0CCR5 not used
case 12: break;
// TB0CCR6 not used
case 14:
// TBIFG overflow handler
REFCTL0 |= REFON;
// Enable internal 1.5V reference
ADC12CTL0 |= ADC12ENC;
// Disable conversions to configure REF
break;
}
}
ADC12_ISR disables further ADC12 conversion, disables the reference to conserve

power, reads ADC12MEM0 and ADC12MEM1 into the temp variables, and clears
the LPM3 bits in the SR register saved into the stack to exit active from ISR
#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR (void)
{
switch(__even_in_range(ADC12IV,34))
{
case 0: break;
// Vector 0: No interrupt
case 2: break;
// Vector 2: ADC overflow
case 4: break;
// Vector 4: ADC timing overflow
case 6: break;
// Vector 6: ADC12IFG0
case 8:
// Vector 8: ADC12IFG1
ADC12CTL0 &= ~ADC12ENC;
// Disable conversions to configure REF
REFCTL0 &= ~REFON;
// Disable internal 1.5V reference
temp_temp = ADC12MEM0;
// Read ADC12 temp measmt, clear IFG
temp_vcc = ADC12MEM1;
// Read ADC12 vcc/2 measmt, clr IFG
. . .}}
Debug
flash memory.
5. Click the Run
Connect the Terminal

6. Click the Terminal tab on the right of your screen, then click the Connect
button.
7. You should see scrolling temperature (in C and F) and the voltage in the Terminal
5-9
Current Measurement
button in the Terminal pane and disconnect the USB-to9. Click the Disconnect
miniUSB cable from your PCs USB port.
In this application the CPU is not active during reference settling and sampling. The CPU
wakes for a very short period of time to enter/exit ISR and store results.
11. Turn off and disconnect your multimeter from the MSP-EXP430 board. Reconnect the
JP1 MSP430 PWR jumper. Disconnect the USB-to-miniUSB cable from the board.
button.
Shut Down
13. Disconnect the FET USB cable from your PC and shut down Code Composer Studio.
Youre done.
5 - 10
Tools, Resources and Conclusion

Introduction
This module will wrap up our discussion by covering the tools and resources available to the
MSP430 designer.
MSP430 Workshop - Tools, Resources and Conclusion
6-1
Module Topics
Module Topics
Tools, Resources and Conclusion............................................................................................................. 6-1
Module Topics......................................................................................................................................... 6-2
Tools ....................................................................................................................................................... 6-3
Programming Tools ................................................................................................................................ 6-5
Boards..................................................................................................................................................... 6-6
Software Tools and Resources ................................................................................................................ 6-7
Conclusion .............................................................................................................................................. 6-8
6-2
Tools
Tools
IAR for MSP430
CCS
73
Code Composer Studio v4.1:

A single development
platform for all TI processors
Enhancements:
Speed
Code
size improvements
Auto-updating
License
manager
Support
for all TI MCUs
Only $495 for MCU Edition
FREE 16KB-limited edition
eZ430 Tools
74
6-3
Tools
The eZ430 Family of MSP430 Tools

The eZ430 is a tradition of low-cost,
easy-to-use tools for MSP430
Options include RF, energyharvesting, RFID, even a wireless

sports watch development kit!
FETs
75
6-4
Programming Tools
Programming Tools
Programming Tools
Parallel FET
Supports ALL MSP430 devices

Supports 4-Wire JTAG mode
only
Fixed output voltage of 2.8V
No JTAG fuse blow
Simple hardware circuit,
possible to implement as part
of a product
USB FET
Supports ALL MSP430 devices

Supports 4-Wire and 2-Wire
(Spy-Bi-Wire) JTAG
Adjustable output voltage:
1.8 - 3.6V, 100mA
JTAG fuse blow
Fast operation
Gang Programmer
76
Gang Programmer GANG430
Target Boards
77
6-5
Boards
Boards
Target Boards for Device Programming
100-pin target board exclusive to

the F543x(A) / F541x(A) devices
Development board with 100-pin
TSSOP (PW) ZIF socket (MSPTS430PZ5x100)
All pins brought out to pin
headers for easy access
Programming via JTAG,
Spy-bi-wire or BSL
A FET board exists for most
variants of MSP430
Only $49
MSP-EXP430FG4618
78
MSP-EXP430FG4618 Experimenter Board
Connector for
CC1100/CC1101/
CC2500/CC2420 EMs
Includes support for the

CC2480 ZigBee
Processor
SW examples and
function library available
at www.ti.com/ccmsplib
Software Tools
79
6-6
Software Tools and Resources
Software Tools and Resources

MSP430 Software Tools
Wireless Networking Protocols
Z-Stack (CC2520 + MSP430F5438 ZigBee)
TI-MAC
SimpliciTI (on MSP430 MediaWiki)
DASH7
Wireless M-Bus
6LoPAN
Example Code for the MSP-EXP430F5438

Experimenter Board (www.ti.com/msp430tools)
Drivers for hardware peripherals, LCD, USB conn.
Operating Systems
uC-OSII
IAR PowerPac
Salvo
FreeRTOS
www.ti.com
80
www.ti.com/msp430
Users Guides
Datasheets
Code Libraries
100+ Application Reports
1000+ Code Examples
Product Brochure
Latest Tool Software
3rd Party Listing
Silicon Errata
Summary
81
6-7
Conclusion
Conclusion
5xx Generation Summary
Ultra-Low Power
Increased Performance
230 A/MHz
1.9 A standby mode
Wake up from standby in < 5 s
Up to 25 MHz
8 MHz across entire operating range
(1.8 - 3.6 V)
1.8V ISP flash erase & write
Fail-safe, flexible clocking system
Innovative Features
Integrated LDO, BOR, WDT+, RTC

Multi-channel DMA supports data
movement in standby mode
More connectivity: USB, RF
AES encryption, RTC on backup
battery
User-defined Bootstrap Loader
Industry-leading code density
Dont Forget
82
Dont Forget!
Take your workshop handouts home with you
Fill out the evaluation form on line if possible

(use paper forms otherwise)
This material is available on-line:
http://processors.wiki.ti.com/index.php/MSP430_5xx_One_Day_Workshop
Thank you for attending

Have a safe trip home
83
6-8

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TI Embedded Processing Portfolio

ARM -Based Processors

Digital Signal Processors (DSPs)

Fla sh, RAM

I ndustrial com puti ng,

Floati ng/Fi xed Poi nt

Telecom test & meas,

$ 1.5 0 to $20 .00

$5.00 to $20 0.00

Software & Dev. Tools

MSP430 Microcontroller Workshop - Introduction

5xx Generation Summary

Integrated LDO, BOR, WDT+, RTC

MSP430 Microcontroller Workshop - Introduction

Basic Clock System

Basic Clock System +

Unified Clock System

Core voltage same as

Core voltage same as supply

Core voltage same as

16-bit CPU, CPUX

16-bit CPU, CPU X

GPIO w/ pull-up and

Software RT C with Basic

T rue 32-bit RTC w/Alarms

4-wir e JT AG, some devices with

MSP430 Microcontroller Workshop - Introduction

CPU Clock (max)

120KB / 8KB (Flash / RAM)

120KB / 8KB (Flash / RAM)

256KB / 16KB (Flash / RAM)

Wake-up Time From LPM3

Standby LPM3 Current

1.9uA (RTC, WDT , SVS

1.2uA (LPM4) / 0.1uA (LPM4.5)

Flash ISP Minimu m DV CC

Port I/O Interrupt Capability

Prog. Port Pin Drive Strength

All port pins

Prog. Pull-ups / Pull- downs

All port pins

All port pins

12-bit A/D Internal Reference

12-bit A/D Active Conversion

Available MCLK Sources

Some devices also P3/P4

Available FLL Reference

* 2xx, 4xx AD C12 ; 5xx - R EF & AD C12 _A

MSP430 Microcontroller Workshop - Introduction

5xx MSP430Xv2 Orthogonal CPU

registers increased to 20-bits

Direct 20-bit CPU register access

Extension word allows

Direct access to 1MB address space

Bit, byte, word and address-word data

Repeat instruction function