CSE 313 4.16.

14
Chapter 3 continue

The concept of memory

- is made up of large number of locations.
- each is uniquely identifiable
- each have the ability to store a value
Address space
- is the total number of uniquely identifiable memory locations.
ex. 16 MB memory
- this consist of 16 million uniquely identifiable memory locations
Addressibility
- is the number of bits stored in each memory location.
ex. 16 mb memory
byte = 8 bits.
Ex. 2^2 by 3 Bit memory.
Address space: 2^2 - 4 memory locations
Addressibility: 3 bits
sequential logic circuits
- digital logic structures that can both process and store information.
state
- set of values stored is the state at a particular time
counter (0->3>0)
000
001
010
011
100
*each of these are states.

Chapter 4: The von Neuname Model

4.16.14

Basic components
- to get a task done in a computer
- computer program : a set of instructions
- computer : to carry out the tasks
Memory
- contains instructions and data
- processing unit
- input devices (keyboard, mouse, scanners, discs)
- output device (monitor, printer, LED)
- control unit for interpreting certain instructions
Memory Address Register
- just the location of that memory
Memory Data Register
- contains the data
Processing Unit
- ALU operations
Memory
ex. 2^k xm
address space: 2^k
addressibility M-bits
computer
ex. 256mb
address space 256 million memory locations
Prime Operations
- LOAD : read a value from a memory location (LD, LDR, LDI in LC3)

- STORE : writing a value to into a memory locations (ST, STR, STI in LC3)
Interface to memory
MAR - Memory Address Register
MDR - Memory DATA Register
To load a location (A)
1. write the address of memory location A into MAR of A
2. send a read enable signal to memory
3. read the data from MDR
To STORE a value x to location A
1. write the data x to MDR
2. write address location A into mAR
Processing unit
- consist of:
1. functional units
- ALU - Arithmatic Logic unit (add subtract)
- other complex operations of functional units (ex sq rt, divide,
multiplication)
2. Registers
- operands
- R0 R1 R2 R3 R4 R5 R6 R7 } each of these holds 16 bits of
information.
3. word size
- number of bits normally processed by the ALU in one instruction
LC-3 word size => 16 bits

Control Unit
- orchestrates the execution of the program
- Instruction Register IR
- contain the current instruction to be executed
- Program Counter PC
- contains the address of the next instruction to be executed.
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CSE 313 4.21.14
Central Idea of Von Neoman model
- program + data on strand in sequences of bits (0 and 1s) in computers memory
- the program is executed one instruction at a time.
Instruction
- specifies 2 things
- operation to be performed
- operands - such as data/locations to be used for the operation
- instruction is coded in a sequence of bits
- such as LC3 which are 16 bits long or even 32 bit long
ADD
- ADD ______, ________, _______
- operands - 2 source operands (data to be added)
- destination operand (sum to be stored after the addition operation)
LC3 add instruction
- The LC3 has 16 bits instructions
- each instruction has four bit output
- LC3 has 8 general purpose registers (GPR)

Ex. ADD R1 R2 R3
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 [0 1 0] 0 0 0 [0 1 1]
[15-12 outcode]
R2
R3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADD operation [ 0

0 0 1][

DR ] [

][

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CSE 313 4.23.14

LDR Instructions
- load instruction read data from memory
- LDR has 2 operands =>
- values to be read from memory
- destination register
ex. LC-3
LDR DR, SR1, offset
* R is used to identify the mechanism that will be used to calculate the address of
the memory l ovation to be read (this is known as the addressing mode) [also known as
base + offset]
[][][][]
(first 4 15-12 is the LDR)

[][][][]
(DR)

[][][][]
(SRC1)

Ex.
LDR R1, R6, #14
R6 + 14
* if you see 0110 from 15-12 then it is a LDR function
* 11-9 is 001 for R1
* 8-6 is 110 for R6

[][][][][]
(offset)

* 5-0 is 001110 is for #14

Instruction cycles
- each instruction cycle go through 6 phases.
1. fetch the instruction from memory
- obtain next instruction from memory and loads into instruction
register
2. decode instruction
- look at outcome [15-12] to decode what operation
3. evaluate the address
- compute address of the operand in memory
4. fetch operands from memory
- contains the source operand needed to process the instruction
ex. ADD R1, (R2), (R3)
5. execute operation
- carries out the execution of the operation
ex. ADD - > addition
6. store result
- stores value in destination register
add R1, R2, R3
R1 < R2 + R3

3- Basic kinds of instruction

1. operate instruction => ADD, AND
2. data instruction => LD, ST
3. control instruction => change the sequence of instruction execution.
JMP R1, uncdition => BR, BRexp, BRn , BRp, BRzp
4.

Instruction Set Architecture (ISA)

ISA => all the programmer visible components and operations of the computer

ISA specifics
- memory organization
- address space (how many memory locations)
- address eligibility (how many bits per location
- Register set
-how many ? src?
- instruction set
- opcode
- data types
- addressing mode
LC-3
- memory
- address space => 2^16 locations
- addressbility => 16 bits
- registeres
- 8 GPS (general purpose registers)
- R0, R1, R2, .. R7
- other registers
- not directly addressable but used by instruction PC
- instruction set (15 opcodes)
- operate instr => ADD, AND, NOT
- data movement instruction => LD, LDR, LDI, ST, STR, STI, LEA
- control instructions => JMP, BR,
DATA TYPES
- 16 bits 2s compliment integers
ADDRESSING MODE
- mechanism for specifying where the operand is located.
CONDITION CODES
- LC3 = > 3 single bit registers are set (set to 1) or cleared (set to 0)
OPERATE INSTRUCTION
LC3 = > 3 operate instruction (ADD, AND, NOT)
NOT => (15-12) 1001 (11-9) DST
* urinary operation only requires one operand.

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CSE 313
Ch.5 4/28/14

0001dst sr c1000src2
ADD [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []
0 in line 5 means register mode
0 1 0 1 same
AND [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []

ADD/AND (Immediate mode)

0001dst sr c1100src2
ADD [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []
1 in line 5 means immediate mode
0 1 0 1 same
AND [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []

Using operate Instruction

* ADD, AND, NOT
* subtract
R2 <- R1 <-R3:
NOT R3, R3
ADD R3, R3, #1
ADD R2, R1, R3
* OR r1 -> not }
inverting it means R1 NOT NOT
r2 -> not }
inverting means R2 NOT NOT

final NOT R1, R1

NOT R2, R2
AND R3, R1, R2
NOT R3, R3

data movement instruction

*between registers and input output discuss(later ch 8)
load - read data from memory to register
LD -> PC relative mode
LDR ->
LDI -> indirect mode
Store - write data from register and memory
ST -> PC relative mode 0011
STR - base effect mode 0111
STI -> indirect mode 1011 SR

Base + Offset mode

LDR } -> specify base + offset mode
STR }
0110dstbaseoffset
LDR [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []
|
v
seat
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CSE313 4/30/14
Chapter 5
JMP instruction
- JMP is an unconditional branch always taken
- target address in a register
|
|
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1100000base000000
[] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []
11110000-------TRAP [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] []

//
chapter 7
Questino 5.15
line 1: LEA R1, x20
line 2: LD R2, x20
line 3: LDI R3, x20
line 4: LDR R4
first 4 bits
second 3 bits: register
first 3

//================================================================
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Chapter 7: Assembly Language
5/5/2014

ADD R4, R1, R3

2 classes of languages:
- high level (C, C++, Fortran)
- low level (assembly language)
Assembler is a program that turns symbols into a machine instruction

//================================================================
//================================================================
//================================================================
5/7/14
.orig x3000
ld r2 lower
ld r3, ascii
ld r4, upper
agaIn trap x23
ADD r1 R@ r#
BRn EXIT
ADD R1 R4 R0
BRf EXIT
ADD R0, R0, R3
TRAP x21
BRexp AGAIN
EXIT TRAP x25
LOWER .FILL XFFEF
UPPER >FILL XFFA6
ASCII .FILL x0020
.END

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May 14, 2014
MIDTERM ch1-5

ex. AND R1, R1, R0

0110 111 111 111111
LDR R7 , R7 , x3F
The load effective address modify the code bits?
- everything except the STORE (True)
What is halt?
- it is a trap instruction (true)
using operand type instructions only place the value 45 in R1
//
25.125
A). Binary
25/2 = 12 + 1
12/2 = 6 + 0 ^
6/2 = 3 + 0 |
3/2 = 1 + 1 |
1/2 = 0 + 1 |
* take the remainders from bottom to top
25 = 1 1 0 0 1
.125 * 2 = 0 .25
.25 * 2 = 0. 5
.5 * 2 = 1. 0
`
0.125 = 0.001

25.125 = 11001.001
n = (-1)^s * 1.Fraction * 2^ E-127
2^4 = 2^e-127
4 = e - 127
131 = E = 1000 0001
11001.001 = (-1)^0 * 1.1001001*2^4
TOTAL = 0 [] 10000011 [] 1001 0010 [] 0

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CSE 313
May 21, 2014
asynchronous: things are happening at different speeds
synchronous: things are happening at the same speeds