Power Reduction and Prediction

Techniques for
3-D Reconfigurable Architectures
Krishna Chaitanya Nunna
( )
PhD Student
Kyushu University

Outline

3D FPGAs
Power Issues
Thermal Issues
Target Work
Plan

2012/4/5

Kyushu University

Outline

3D FPGAs
Power Issues
Thermal Issues
Target Work
Plan

2012/4/5

Kyushu University

FPGA
Field-programmable gate arrays (FPGAs)
programmable logic devices (PLDs)
can be configured by the end-user to implement any digital circuit.
SEL
MUX

MUX

Configurable Logic
Blocks

SEL

MEMO
RY

OUT

FF

I/O Blocks

LOGIC BLOCK

Programmable Interconnects

FPGA Architecture

2012/4/5

SWITCH and CONNECTION BLOCKS

Kyushu University

FPGA Conventional
CAD Flow

Application
Description

Synthesis

Technology Mapping

Partitioning

Placement

Routing

Bit Stream
Generation
2012/4/5

Kyushu University

Island Style 3D FPGA

Embedded Block
Logic Block

Connection Block
Switch Box
Wires
I/O pads

TSV

2012/4/5

Kyushu University

Outline

3D FPGAs
Power Issues
Thermal Issues
Target Work
Plan

2012/4/5

Kyushu University

Power Issues
More transistors are needed to implement a given logic circuit in an FPGA
in comparison with a custom ASIC.
leads to a higher power consumption per logic gate in FPGAs and
power-efficiency is undisputed as an area in which ASICs are superior
to FPGAs.
Power has been cited as a limiting factor in the ability of FPGAs to
continue to replace ASICs.

2012/4/5

Kyushu University

Power components breakdown

Total Power Consumption

Static Power

Dynamic Power

Logic
Blocks

Connection
Boxes

Switch
boxes

Logic
Blocks

Switch
boxes

Entire area

Active or Utilized Area

2012/4/5

Connection
Boxes

Kyushu University

Dynamic Power Breakdown

in Xilinx Virtex-II [Shang02]

Static Power Breakdown

in Xilinx Spartan-3 [Tuan03]

[Shang02] L. Shang, A. Kaviani, and K. Bathala. Dynamic Power Consumption in the Virtex-II FPGA Family". In: ACM/SIGDA International
Symposium on Field Programmable Gate Arrays, pp. 157{164, Monterey, CA, 2002.
[Tuan03] T. Tuan and B. Lai. Leakage Power Analysis of a 90nm FPGA". In IEEE Custom Integrated Circuits Conference, pp. 57-60, San Jose, CA,
2003

2012/4/5

Kyushu University

10

From our experiments

300

Power in mW

250

FPGA Array = 20x20

Channel Width = 50

200
Dynamic(Total)

150

Dynamic(Routing)

100

Static(Total)

50

Dynamic(Logic)

0
66.5

70

83.5

90.5

97.25

Circuit Size Increases----------->

Power consumption due to routing resources dominates.

Static power is almost constant with increasing circuit size.
For early stage power estimation, concentration on utilized routing resources
makes a big difference.
2012/4/5

Kyushu University

11

Outline

3D FPGAs
Power Issues
Thermal Issues
Target Work
Plan

2012/4/5

Kyushu University

12

Thermal Issues

Thermal management of FPGA devices is more critical compared to ASIC

solutions,
as it dissipates more power, while their operating temperatures usually exceed
the critical one.
Also, the leakage current increases exponentially with temperature, causing a
positive feedback loop between leakage power and temperature [Farzan05].

The thermal problem is severe in the 3D cases for mainly two reasons:
The vertically stacked multiple layers of active devices causes a rapid
increase of power density;
The thermal conductivity of the dielectric layers between the device layers is
very low compared to silicon and metal.

Temperature increase as a function of the number of chip-layers (n) and

the power density in each layer.

Thermal issues in 3D FPGAs are

relatively unexplored.
[Farzan05] Farzan Fallah and Massoud Pedram, Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits, IEICE
leakage review journal 2005

2012/4/5

Kyushu University

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Outline

3D FPGAs
Power Issues
Thermal Issues
Target Work
Plan

2012/4/5

Kyushu University

14

Application
Description

Our proposed flow

Synthesis

We are targeting for a 3D FPGA EDA

methodology which can be of
power/thermal-aware.

Technology
Mapping

TA
Partitioning

3D
Architecture
Description

TA
Layer Assignment

Pros:
thermal-aware partitioning

Layout
information for
next iteration

TA
2D/3D Placement

Cons:
- unavailability of required information
(for the first step) based on rough
assumptions for the partitioning
2012/4/5

TA
3D Routing

Accurate post-layout simulation

Kyushu University

Bit Stream
Generation

15

How The Performance Metrics are

Considered?
Power
consumption

Temperature

Timing

Partitioning

Early estimation

Early estimation

Cut size-implicit

Layer
Assignment

considered

considered

Cut size and net

length

Placement

More accurate
estimation

More accurate
estimation

Wirelength
estimation

Routing

Most accurate
estimation

Most accurate
estimation

Precise
wirelength

2012/4/5

Kyushu University

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Present Status

3D Partitioning- A Detailed View

Application
Description

Estimating Power &

Thermal Parameters

Partitioning

Synth
esis

Technolo
gy
Mapping

3D
Architecture
Description
TA
Partitioning

Power and
Thermal
conditions are
met?

No

TA
Layer
assignment

TA
2D/3D
Placement

Yes
TA
3D
Routing

Layout
information for
next iteration
2012/4/5

Accurate postlayout simulation

Kyushu University

Bit Stream
Generation

17

Outline

3D FPGAs
Power Issues
Thermal Issues
Target Work
Plan

2012/4/5

Kyushu University

18

Future Plan and Conclusion

Power and thermal-aware partitioning

Power and thermal-aware placement
Power and thermal-aware routing
Dynamic thermal management
Possible architecture exploration
3D integration mitigates many of the restrictions introduced by existing design
methodologies.
Thermal management of 3D reconfigurable architectures is critical as FPGAs
exhibit high power consumption higher temperatures in 3D stack
Significant contribution can be made in this domain which can hopefully
exhibits promising results.

2012/4/5

Kyushu University

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