ABSTRACT:

CHAPTER 1
INTRODUCTION TO VLSI

Very-large-scale integration (VLSI) is the process of creating integrated circuits by

combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s
when complex semiconductor and communication technologies were being developed. The
microprocessor is a VLSI device. The term is no longer as common as it once was, as chips
have increased in complexity into the hundreds of millions of transistors.

Overview
The first semiconductor chips held one transistor each. Subsequent advances added more
and more transistors, and, as a consequence, more individual functions or systems were
integrated over time. The first integrated circuits held only a few devices, perhaps as many as
ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic
gates on a single device. Now known retrospectively as "small-scale integration" (SSI),
improvements in technique led to devices with hundreds of logic gates, known as large-scale
integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has
moved far past this mark and today's microprocessors have many millions of gates and
hundreds of millions of individual transistors.
At one time, there was an effort to name and calibrate various levels of large-scale integration
above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used. But the huge number of
gates and transistors available on common devices has rendered such fine distinctions moot.
Terms suggesting greater than VLSI levels of integration are no longer in widespread use. Even
VLSI is now somewhat quaint, given the common assumption that all microprocessors are
VLSI or better.
As of early 2008, billion-transistor processors are commercially available, an example of which
is Intel's Montecito Itanium chip. This is expected to become more commonplace as
semiconductor fabrication moves from the current generation of 65 nm processes to the next 45
nm generations (while experiencing new challenges such as increased variation across process
corners). Another notable example is NVIDIAs 280 series GPU.
This microprocessor is unique in the fact that its 1.4 Billion transistor count, capable of a
teraflop of performance, is almost entirely dedicated to logic (Itanium's transistor count is
largely due to the 24MB L3 cache). Current designs, as opposed to the earliest devices, use
extensive design automation and automated logic synthesis to lay out the transistors, enabling
higher levels of complexity in the resulting logic functionality. Certain high-performance logic
blocks like the SRAM cell, however, are still designed by hand to ensure the highest efficiency
(sometimes by bending or breaking established design rules to obtain the last bit of performance
by trading stability).
What is VLSI?

VLSI stands for "Very Large Scale Integration". This is the field which
involves packing more and more logic devices into smaller and smaller areas.

Simply we say Integrated circuit is many transistors on one chip.

Design/manufacturing of extremely small, complex circuitry using modified

semiconductor material

Integrated circuit (IC) may contain millions of transistors, each a few mm in size

Applications wide ranging: most electronic logic devices

1.1.

History of Scale Integration

late 1940s Transistor invented at Bell Labs

late 1950s First IC (JK-FF by Jack Kilby at TI)

early 1960s Small Scale Integration (SSI)

10s of transistors on a chip

late 1960s Medium Scale Integration (MSI)

100s of transistors on a chip

early 1970s Large Scale Integration (LSI)

1000s of transistor on a chip

early 1980s VLSI 10,000s of transistors on a

chip (later 100,000s & now 1,000,000s)

Ultra LSI is sometimes used for 1,000,000s

SSI - Small-Scale Integration (0-102)

MSI - Medium-Scale Integration (102-103)

LSI - Large-Scale Integration (103-105)

VLSI - Very Large-Scale Integration (105-107)

ULSI - Ultra Large-Scale Integration (>=107)

1.2.

Advantages of ICs over discrete components

While we will concentrate on integrated circuits , the properties of integrated circuits-what we

can and cannot efficiently put in an integrated circuit-largely determine the architecture of the
entire system. Integrated circuits improve system characteristics in several critical ways. ICs
have three key advantages over digital circuits built from discrete components:


Size. Integrated circuits are much smaller-both transistors and wires are shrunk to
micrometer sizes, compared to the millimeter or centimeter scales of discrete components.
Small size leads to advantages in speed and power consumption, since smaller components have
smaller parasitic resistances, capacitances, and inductances.

Speed. Signals can be switched between logic 0 and logic 1 much quicker within a chip
than they can between chips. Communication within a chip can occur hundreds of times faster
than communication between chips on a printed circuit board. The high speed of circuits onchip is due to their small size-smaller components and wires have smaller parasitic capacitances
to slow down the signal.

Power consumption. Logic operations within a chip also take much less power. Once
again, lower power consumption is largely due to the small size of circuits on the chip-smaller
parasitic capacitances and resistances require less power to drive them.
VLSI and systems
These advantages of integrated circuits translate into advantages at the system level:

Smaller physical size. Smallness is often an advantage in itself-consider portable

televisions or handheld cellular telephones.

Lower power consumption. Replacing a handful of standard parts with a single chip
reduces total power consumption. Reducing power consumption has a ripple effect on the rest of
the system: a smaller, cheaper power supply can be used; since less power consumption means
less heat, a fan may no longer be necessary; a simpler cabinet with less shielding for
electromagnetic shielding may be feasible, too.

Reduced cost. Reducing the number of components, the power supply requirements,
cabinet costs, and so on, will inevitably reduce system cost. The ripple effect of integration is
such that the cost of a system built from custom ICs can be less, even though the individual ICs
cost more than the standard parts they replace.
Understanding why integrated circuit technology has such profound influence on the design of
digital systems requires understanding both the technology of IC manufacturing and the
economics of ICs and digital systems.
Applications

Electronic system in cars.

Digital electronics control VCRs

Transaction processing system, ATM

Personal computers and Workstations

Medical electronic systems.

Etc.

1.3.

Applications of VLSI

Electronic systems now perform a wide variety of tasks in daily life. Electronic systems in some
cases have replaced mechanisms that operated mechanically, hydraulically, or by other means;
electronics are usually smaller, more flexible, and easier to service. In other cases electronic
systems have created totally new applications. Electronic systems perform a variety of tasks,
some of them visible, some more hidden:

Personal entertainment systems such as portable MP3 players and DVD players perform
sophisticated algorithms with remarkably little energy.

Electronic systems in cars operate stereo systems and displays; they also control fuel
injection systems, adjust suspensions to varying terrain, and perform the control functions
required for anti-lock braking (ABS) systems.

Digital electronics compress and decompress video, even at high-definition data rates,
on-the-fly in consumer electronics.

Low-cost terminals for Web browsing still require sophisticated electronics, despite their
dedicated function.

Personal computers and workstations provide word-processing, financial analysis, and

games. Computers include both central processing units (CPUs) and special-purpose hardware
for disk access, faster screen display, etc.

Medical electronic systems measure bodily functions and perform complex processing
algorithms to warn about unusual conditions. The availability of these complex systems, far
from overwhelming consumers, only creates demand for even more complex systems.
The growing sophistication of applications continually pushes the design and manufacturing of
integrated circuits and electronic systems to new levels of complexity. And perhaps the most
amazing characteristic of this collection of systems is its variety-as systems become more
complex, we build not a few general-purpose computers but an ever wider range of specialpurpose systems. Our ability to do so is a testament to our growing mastery of both integrated
circuit manufacturing and design, but the increasing demands of customers continue to test the
limits of design and manufacturing

CHAPTER 2
2.

VHDL Basics

2.1.

Introduction

VHDL is an acronym for Very High Speed Integrated Circuits Hardware description Language.
The language can be used to model a digital system at many levels of abstraction ranging from
the algorithmic level to the gate level. The complexity of the digital system being modeled
could vary from that of a simple gate to a complete digital electronic system. The VHDL

language can be regarded as an integrated amalgamation of sequential, concurrent, net list and
waveform generation languages and timing specifications.

2.2.

History of VHDL

VHDL stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description
Language. It was developed in the 1980s as spin-off of a high-speed integrated circuit research
project funded by the US department of defense. During the VHSIC program, researchers were
confronted with the daunting task of describing circuits of enormous scale (for their time) and
of managing very large circuit design problems that involved multiple teams of engineers. With
only gate-level tools available, it soon became clear that more structured design methods and
tools would be needed.
To meet this challenge, teams of engineers from three companies - IBM, Texas Instruments and
Intermetrics were contracted by the department of defense to complete the specification and
implementation of a new language based design description method. The first publicly available
version of VHDL, version 7.2 was released in 1985. In 1986, the IEEE was presented with a
proposal to standardize the language, which it did in 1987 and academic representatives. The
resulting standard, IEEE 10761987 is the basis for virtually every simulation and synthesis
product sold today. An enhanced and updated version of the language, IEEE 1076-1993, was
released in 1994, and VHDL tool vendors have been responding by adding these new language
features to their products.

Although IEEE standard 1076 defines the complete VHDL language, there are aspects of the
language that make it difficult to write completely portable design descriptions (description that
can be simulated identically using different vendors tools). The problem stems from the fact
that VHDL supports many abstract data types, but it does not address the simple problem of
characterizing different signal strengths or commonly used simulation conditions such as
unknowns and high impedances. Soon after IEEE 1076-1987 [3] was adopted, simulator
companies began enhancing VHDL with new non-standard types to allow their customers to
accurately simulate complex electronics circuits. This caused problems because design
descriptions entered into one simulator were often incompatible with another with other
environments. VHDL was quickly becoming a non-standard.

To get around the problem of non-standard data types, an IEEE committee adopted another
standard. This standard numbered 1164, defines a standard package (a VHDL feature that
allows commonly used declaration to be collected into an external library) containing definition
for a standard nine-value data type. This standard data type is called standard logic, and the
IELL 1164 package is often referred to as the standard logic package.

The IEEN 1076-1987 and IEEE 1164 standards together form the complete VHDL standard in
widest use today (IEEE 1076-1993 is slowly working its way into the VHDL mainstream, but it
does not add significant number of features for synthesis users).

In the search for a standard design and documentation tool for the Very High Speed Integrated
Circuits (VHSIC) program the United States Department of Defense (DOD) in the summer of
1981 sponsored a workshop on HDLs at Woods Hole, Massachusetts. The conclusion of the
workshop was the need for a standard language, and the features that might be required by such
a standard in 1983.DoD established requirements for a standard VHSIC hardware description
language(VHDL), based on the recommendation of the Woods Hole workshop. A contract for
the development of the VHDL language, its environment, and its software was awarded to IBM,
Texas instruments and Intermetrics. VHDL 2.0 was released only six months after the project
began. The language was significantly improved hereafter and other shortcomings were
corrected leading to the release of VHDL 6.0. In 1985 this significant developments led to the
release of VHDL 6.0. In 1985 these significant development led to the release of VHDL 7.2
language reference manual. This was later on developed as IEEE 1076/A VHDL language
reference manual.

Efforts for defining the new version of VHDL stated in 1990 by a ream of volunteers working
under the IEEE DASC (Design Automation Standards committee). In October of 1992, a new
VHDL93 was completed and was released for review. After minor modifications, this new
version was approved by the VHDL balloting group members and became the new VHDL
language standard. The present VHDL standard is formally referred as VHDL 1076-1993.

2.3.

Levels of abstraction (Styles)

VHDL supports many possible styles of design description. These styles differ primarily in how
closely they relate to the underlying hardware. When we speak of the different styles of VHDL,
then, we are really talking about the differing levels of abstraction possible using the language.
To give an example, it is possible to describe a counter circuit in a number of ways. At the
lowest level of abstraction, you could use VHDL's hierarchy features to connect a sequence of
predefined logic gates and flip-flips to form a counter circuit.

Fig. 4.1 Levels of abstraction

In a behavioral description, the concept of time may be expressed precisely, with actual delays
between related events, or may simply be an ordering of operations that are expressed
sequentially. When you are writing VHDL for input to synthesis tools, you may use behavioral
statements in VHDL to imply that there are registers in your circuit. It is unlikely, however, that
your synthesis tool will be capable of creating precisely the same behavior in actual circuitry as
you have defined in the language.

The highest level of abstraction supported in VHDL is called the behavioral level of abstraction.
When creating a behavioral description of a circuit, you will describe your circuit in terms of its

operation over time. The concept of time is the critical distinction between behavioral
descriptions of circuits and lower-level descriptions.

If you are familiar with event-driven software programming languages then writing behavior
level VHDL will not seem like anything new. Just like a programming language, you will be
writing one or more small programs that operate sequentially and communicate with one
another through their interfaces. The only difference between behavior-level VHDL and a
software programming language such as Visual Basic is the underlying execution platform: in
the case of Visual Basic, it is the Windows operating system; in the case of VHDL, it is a
simulator.

An alternate design method, in which a circuit design problem is segmented into registers and
combinational input logic, is what is often called the dataflow level of abstraction. Dataflow is
an intermediate level of abstraction that allows the drudgery of combinational logic to be hidden
while the more important parts of the circuit, the registers, are more completely specified.

There are some drawbacks to using a purely dataflow method of design in VHDL. First, there
are no built-in registers in VHDL; the language was designed to be general-purpose, and
VHDLs designers on its behavioral aspects placed the emphasis. If you are going to write
VHDL at the dataflow level of abstraction, then you must first create behavioral descriptions of
the register elements that you will be using in your design. These elements must be provided in
the form of components or in the form of subprograms.

But for hardware designers, for whom it can be difficult to relate the sequential descriptions and
operation of behavioral VHDL with the hardware that is being described, using the dataflow
level of abstraction can make quite a lot of sense. Using dataflow, it can be easier to relate a
design description to actual hardware devices.

The dataflow and behavior levels of abstraction are used to describe circuits in terms of their
logical function. There is a third style of VHDL that is used to combine such descriptions
together into a larger, hierarchical circuit description.
Structural VHDL allows you to encapsulate one part of a design description as a re-usable
component. Structural VHDL can be thought of as being analogous to a textual schematic, or as
a textual block diagram for higher-level design.

2.4.

Need for VHDL

The complex and laborious manual procedures for the design of the hardware have paved the
way for the development of languages for high level description of the digital system. This
high-level description can serve as documentation for the part as well as an entry point into the
design process. The high level description can be processed through various boards, or gate
array using the synthesis tools of Hardware Description language us such a language. VHDL
was designed as a solution to provide an integrated design and documentation to communicate
design data between various levels of abstractions.
2.5.

Advantages of VHDL

VHDL allows quick description and synthesis of circuits of 5, 10, 20 thousand gates. It also
provides the following capabilities. The following are the major advantages of VHDL over
other hardware description languages:
Power and flexibility VHDL has powerful language constructs which allows code description
of complex control logic.
Device independent design VHDL creates design that fits into many device architecture and
it also permits multiple styles of design description.

Portability VHDLs portability permits the design description to be used on different

simulators and synthesis tools. Thus VHDL design descriptions can be used in multiple projects.
ASIC migration The efficiency of VHDL allows design to be synthesized on a CPLD or an
FPGA. Sometimes the code can be used with the ASIC.
Quick time to market and low cost VHDL and programmable logic pair together facilitate
speedy design process. VHDL permits designs to be described quickly.
Programmable logic eliminates expenses and facilitates quick design iterations
The language can be used as a communication medium between different Computer Aided
Design (CAD) and Computer Aided Engineering (CAE) tools.

The language supports hierarchy, i.e., a digital system can be modeled as a set of
interconnected components; each component, in turn, can be modeled as a set of interconnected
subcomponents.
The language supports flexible design methodologies: Top-Down, Bottom- Up, or Mixed.
The language is technology independent and hence the same behavior model can be
synthesized into different vendor libraries.
Various digital modeling techniques such as finite-state machine descriptions, algorithmic
descriptions and Boolean equations can be modeled using the language.
It supports both synchronous and asynchronous timing models.
It is an IEEE and ANSI standard, and therefore, models described using these languages are
portable.
There are no limitations that are imposed by the language on the size of the design.


The language has elements that make large-scale design modeling easier, for e.g.
Components, functions, procedures and packages.
Test benches can be written using the same language to test other VHDL models.
Nominal propagation delays, min-max delays, setup and holding timing, timingconstraints,
and spike detection can all be described very naturally in this language.
Behavioral models that conform to a certain synthesis description style are capable of being
synthesized to gate-level description.
The capability of defining new data types provides the power to describe and simulate a new
design technique at a very high level of abstraction without any concern about implementation
details.

Design methodology using VHDL

There are three design methodologies namely: bottom-up, top-down and flat
The bottom-up approach involves the defining and designing the individual components, then
bringing the individual components together to form the overall design.

In a flat design the functional components are defined at the same level as the
interconnection of those functional components.
A top-down design process involves a divide-and-conquer approach to implement the design a
large system. Top-down design is referred to as recursive partitioning of a system into its subcomponents until all sub-components become manageable design parts. Design of a component
is manageable if the component is available as part of a library, it can be implemented by
modifying an already available part, or it can be described for a synthesis program or an
automatic hardware generator.

Elements of VHDL
Constructs of the VHDL language are designed for describing hardware components, packaging
parts and utilities use of libraries and for specifying design libraries and parameters. In its
simplest form, the description of a component in VHDL consists of an interface specification
and an architectural specification. The interface description begins with Entity keyword and
contains the input-output ports of the component. An architectural specification begins with the
Architectural keyword, which describes the functionality of a component.
This functionality depends on input-output signals and other parameters that are specified in the
interface description. Several architectural specifications with different identifiers can exist for
one component with a given interface description. VHDL allows architecture to be configured
for a specific technology environment.
In a hardware design environment it becomes necessary to group components or utilities
used for description of components. Components and such utilities can be grouped by use of
packages. A package declaration contains components and utilities to be come visible by
Entities and Architectures. VHDL allows the use of Libraries and binding of sub-components

of a design to elements of various libraries. Constructs for such applications include a library
statement and configurations.

2.6.

VHDL language features

The various building blocks and constructs in VHDL which have been used are:

Entity
Every VHDL design description consists of at least one entity. In VHDL, an entity declaration
describes the circuit as it appears from the "outside", from the perspective of its input and
output interfaces.
An entity declaration in VHDL provides the complete interface for a circuit. Using the
information provided in an entity declaration (the port names and the data type and direction of
each port), you have all the information you need to connect that portion of a circuit into other,
higher-level circuits.
The entity declaration includes a name, compare, and a port statement defining all the inputs
and outputs of the entity. Each of the ports is given a direction (either in, out or inout).
Formal Definition
It is the hardware abstraction of a digital system. Entity declaration describes the external view
of the entity to the outside world.
Simplified syntax:
Entity entity-name is
Port (port-list);
[generic(generic-list);]
end entity-name;

Description
All designs are expressed in terms of entities. Entity is the most basic building block in
a design. The uppermost level of the design is the top-level entity. If the design is hierarchical,
then the top-level description will have lower-level descriptions contained in it. These lowerlevel descriptions will be lower-level entities contained in the top-level entity description.

Architecture

Every entity in a VHDL design description must be bound with a corresponding architecture.
The architecture describes the actual function of the entity to which it is bound. Using the
schematic as a metaphor, you can think of the architecture as being roughly analogous to a
lower-level schematic pointed to by the higher-level functional block symbol.
The second part of a minimal VHDL source file is the architecture declaration. Every entity
declaration you write must be accompanied by at least one corresponding architecture.
The architecture declaration begins with a unique name, followed by the name of the entity to
which the architecture is bound. Within the architecture declaration is found the actual
functional description of our comparator. There are many ways to describe combinational logic
functions in VHDL.
Formal Definition
A body associated with an entity declaration to describe the internal organization or operation of
a design entity. An architecture body is used to describe the behavior, data flow or structure of a
design entity:
Simplified syntax
Architecture architecture-name of entity-name is
Architecture-declarations
Begin
Concurrent-statements
End [architecture] [architecture-name];

Description
Architecture assigned to an entity describes internal relationship between input and
output ports of the entity. It contains of two parts: declarations and concurrent statements. First
(declarative) part of architecture may contain declarations of types, signals, constants,
subprograms (functions and procedures), components and groups.
Concurrent statements in the architecture body define the relationship between inputs
and outputs. This relationship can be specified using different types of statements: Concurrent
signal assignment, process statement, component instantiation, and concurrent procedure call,
generate statement, concurrent assertion statement, and block statement. It can be writing in
different styles: structural, dataflow, behavioral (functional) or mixed.
The description of a structural body is based on component instantiation and generates
statements. It allows creating hierarchical projects, from simple gates to very complex
components, describing entire subsystems. The Connections among components are realized
through ports.

The Dataflow description is built with concurrent signal assignment statements. Each of
the statements can be activated when any of its input signals changes its value.
The architecture body describes only the expected functionality (behavior) of the circuit,
without any direct indication as to the hard ware implementation. Such description consists
only of one or more processes, each of which contains sequential statements. The Architecture
body may contain statements that define both behavior and structure of the circuit at the same
time. Such architecture description is called mixed.

Component declaration
Formal Definition
A component declaration declares a virtual design entity interface that may be used in
component instantiation statement.
Simplified syntax:
Component component-name
[generic(generic-list)];
port(port-list);
end component [component-name];

Component instantiation
Formal Definition
A component instantiation statement defines a subcomponent of the design entity in which it
appears, associate signals or values with the ports of that subcomponent, and associates values
with generics of that subcomponent.
Simplified syntax
Label: [component] component-name
Generic map (generic-association-list);
Port map (port-association-list);

Configuration declaration
Formal Definition
A configuration is a construct that defines how component instances in a given block are bound
to design entities in order to describe how design entities are put together to form a complete
design.

 Simplified syntax
Configuration configuration-name of entity-name is
Configuration declarations.
For architecture-name
For instance-label: component-name
Use entity library-name. Entity-name (arch-name);
End for;
end for;
end configuration-name;

Configuration instantiation
Formal Definition
A component instantiation statement defines a subcomponent of the design entity in
which it appears, associates signals or value with the ports of that subcomponent, and associates
values with generics of that subcomponent.

Simplified syntax
Label: Configuration configuration-name
Generic map (generic-association-list);
Port map (port-association-list);

Package
Formal Definition
A package declaration defines the interface to a package.
Simplified syntax
Package package-name is
Package declarations
End [package] package-name;
Package body
Formal Definition

A package body defines the bodies of subprograms and the values of deferred constants
declared in the interface to the package.
Simplified syntax:
Package body package-name is
Package-body-declarations
Subprogram bodies declarations
End [package body] package-name;

Attributes
Attributes are of two types: user defined and predefined.
User defined
Formal Definition
A value, function, type, range, signals, or constant that may be associated with one or more
named entities in a description.
Simplified syntax
Attribute attribute-name: type;

--attribute declaration

Attribute attribute-name of item: item-class is expression attribute specification

Description
Attributes allow retrieving information about named entities: types, objects, subprograms etc.
Users can define mew attributes and then assign them to named entities by specifying the entity
and the attribute values for it.
Predefined
Formal Definition
A value, function, type, range, signals, or constant that may be associated with one or more
named entities in a description.
Simplified syntax: objects attribute-name

Process statement
Formal Definition
A process statement defines an independent sequential process representing the behavior of
some portion of the design
Simplified syntax:

[process-label:] process [(sensitivity-list)];

Process-declarations
begin
Sequential-statements
end process [process-label];

Function
Formal Definition
A function call is a subprogram of the form of an expression that returns a value.
Simplified syntax
Function function name(parameters) return type

-- function declaration

Function function-name(parameters) return type is --- function definition.

Begin
Sequential statements
End [function] function-name;

Port
Formal Definition
A channel for dynamic communication between a block and its environment.
Simplified syntax:
Port (port-declaration, port-declaration,-----);
----port declarations:
Port-signal-name: in port-signal-type: =initial-value
Port-signal-name: out port-signal-type: =initial-value
Port-signal-name: in out port-signal-type: =initial-value
Port-signal-name: buffer port-signal-type: =initial-value
Port-signal-name: linkage port-signal-type: =initial-value

Sensitivity list
Formal Definition

A list of signals a process is sensitive to.

Simplified syntax:
(Signal-name, signal-name, ---)
Formal Definition

Standard logic
Formal Definition
A nine-value resolved logic type.
Std-logic is not a part of the VHDL standard. It is defined in IEEE Std 1164.
Simplified syntax:
Type std-ulogic is

(U, -- Uninitialized
X, -- Forcing Unknown
0, -- Forcing 0
1, -- Forcing 1
Z -- High Impedance
W--Weak Unknown
L--Weak 1
---Dont Care);

Type std-ulogic-vector is array (natural range <>) of std-ulogic

Function resolved (s: std-ulogic-vector) return std-ulogic;
Subtype std-logic is resolved std-ulogic;

Data Types
There are many data types available in VHDL. VHDL allows data to be represented in terms of
high-level data types. These data types can represent individual wires in a circuit, or can
represent collections of wires using a concept called an array.

The preceding description of the comparator circuit used the data types bit and bit vector for its
inputs and outputs. The bit data type (bit vector is simply an array of bits) values of '1' and '0'
are the only possible values for the bit data type. Every data type in VHDL has a defined set of
values, and a defined set of valid operations. Type checking is strict, so it is not possible, for

example, to directly assign the value of an integer data type to a bit vector data type. (There are
ways to get around this restriction, using what are called type conversion functions.) VHDL is
rich language with many different data types.

The most common data types are listed below:

Bit: a 1-bit value representing a wire. (Note: IEEE standard 1164 defines a 9-valued
replacement for bit called std_logic.)
Bit vector: an array of bits. (Replaced by std_logic_vector in IEEE 1164.)
Boolean: a True/False value.
Integer: a signed integer value, typically implemented as a 32-bit data type.
Real: a floating-point value.
Enumerated: used to create custom data types.
Record: used to append multiple data types as a collection.
Array: can be used to create single or multiple dimension arrays.
Access: similar to pointers in C or Pascal.
file: used to read and write disk files. Useful for simulation.
Physical: used to represent values such as time, voltage, etc. using symbolic units of measure
(such as 'ns' or 'ma').

Packages and Package Bodies

A VHDL package declaration is identified by the package keyword, and is used to collect
commonly used declarations for use globally among different design units. You can think of a
package as being a common storage area, one used to store such things as type declarations,
constants, and global subprograms.

A package can consist of two basic parts: a package declaration and an optional package body.
Package declarations can contain the following types of statements:
Type and subtype declarations
Constant declarations

Global signal declarations

Function and procedure declarations
Attribute specifications
File declarations
Component declarations
Alias declarations
Disconnect specifications
Use clauses

Items appearing within a package declaration can be made visible to other design units through
the use of a use statement.
If the package contains declarations of subprograms (functions or procedures) or defines one or
more deferred constants (constants whose value is not given), then a package body is required in
addition to the package declaration. A package body must have the same name as its
corresponding package declaration, but can be located anywhere in the design.
The relationship between a package and package body is somewhat akin to the relationship
between an entity and its corresponding architecture. While the package declaration provides
the information needed to use the items defined within it (the parameter list for a global
procedure, or the name of a defined type or subtype), the actual behavior of such things as
procedures and functions must be specified within package bodies.

CHAPTER 3:

Introduction to AES:

The Advanced Encryption Standard (AES), also referenced as Rijndael[4][5] (its original
name), is a specification for the encryption of electronic data established by the U.S. National
Institute of Standards and Technology (NIST) in 2001.
AES is based on the Rijndael cipher[5] developed by two Belgian cryptographers, Joan Daemen
and Vincent Rijmen, who submitted a proposal to NIST during the AES selection process.[7]
Rijndael is a family of ciphers with different key and block sizes. For AES, NIST selected three
members of the Rijndael family, each with a block size of 128 bits, but three different key
lengths: 128, 192 and 256 bits.
AES has been adopted by the U.S. government and is now used worldwide. It supersedes the
Data Encryption Standard (DES),[8] which was published in 1977. The algorithm described by
AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and
decrypting the data. In the United States, AES was announced by the NIST as U.S. FIPS PUB
197 (FIPS 197) on November 26, 2001.[6] This announcement followed a five-year
standardization process in which fifteen competing designs were presented and evaluated,
before the Rijndael cipher was selected as the most suitable (see Advanced Encryption Standard
process for more details).
AES became effective as a federal government standard on May 26, 2002 after approval by the
Secretary of Commerce. AES is included in the ISO/IEC 18033-3 standard. AES is available in
many different encryption packages, and is the first publicly accessible and open cipher
approved by the National Security Agency (NSA) for top secret information when used in an
NSA approved cryptographic module (see Security of AES, below).
AES is based on a design principle known as a substitution-permutation network, combination
of both substitution and permutation, and is fast in both software and hardware.[10] Unlike its
predecessor DES, AES does not use a Feistel network. AES is a variant of Rijndael which has a
fixed block size of 128 bits, and a key size of 128, 192, or 256 bits. By contrast, the Rijndael
specification per se is specified with block and key sizes that may be any multiple of 32 bits,
both with a minimum of 128 and a maximum of 256 bits.

AES operates on a 44 column-major order matrix of bytes, termed the state, although some
versions of Rijndael have a larger block size and have additional columns in the state. Most
AES calculations are done in a special finite field.

The key size used for an AES cipher specifies the number of repetitions of transformation
rounds that convert the input, called the plaintext, into the final output, called the ciphertext.
The number of cycles of repetition are as follows:

10 cycles of repetition for 128-bit keys.

12 cycles of repetition for 192-bit keys.

14 cycles of repetition for 256-bit keys.

Each round consists of several processing steps, each containing four similar but different
stages, including one that depends on the encryption key itself. A set of reverse rounds are
applied to transform ciphertext back into the original plaintext using the same encryption key.
High-level description of the algorithm

KeyExpansionsround keys are derived from the cipher key using Rijndael's key schedule.
AES requires a separate 128-bit round key block for each round plus one more.
InitialRound
AddRoundKeyeach byte of the state is combined with a block of the round key using
bitwise xor.
Rounds
SubBytesa non-linear substitution step where each byte is replaced with another
according to a lookup table.
ShiftRowsa transposition step where the last three rows of the state are shifted cyclically
a certain number of steps.
MixColumnsa mixing operation which operates on the columns of the state, combining
the four bytes in each column.
AddRoundKey
Final Round (no MixColumns)
SubBytes
ShiftRows
AddRoundKey.

The SubBytes step

In the SubBytes step, each byte in the state is replaced with its entry in a fixed 8-bit lookup
table, S; bij = S(aij).

In the SubBytes step, each byte a_{i,j} in the state matrix is replaced with a SubByte S(a_{i,j})
using an 8-bit substitution box, the Rijndael S-box. This operation provides the non-linearity in
the cipher. The S-box used is derived from the multiplicative inverse over GF(28), known to
have good non-linearity properties. To avoid attacks based on simple algebraic properties, the Sbox is constructed by combining the inverse function with an invertible affine transformation.
The S-box is also chosen to avoid any fixed points (and so is a derangement), i.e., S(a_{i,j})

\neq a_{i,j} , and also any opposite fixed points, i.e., S(a_{i,j}) \oplus a_{i,j} \neq \text{0xFF} .
While performing the decryption, Inverse SubBytes step is used, which requires first taking the
affine transformation and then finding the multiplicative inverse (just reversing the steps used in
SubBytes step).
The ShiftRows step
In the ShiftRows step, bytes in each row of the state are shifted cyclically to the left. The
number of places each byte is shifted differs for each row.

The ShiftRows step operates on the rows of the state; it cyclically shifts the bytes in each row
by a certain offset. For AES, the first row is left unchanged. Each byte of the second row is
shifted one to the left. Similarly, the third and fourth rows are shifted by offsets of two and three
respectively. For blocks of sizes 128 bits and 192 bits, the shifting pattern is the same. Row n is
shifted left circular by n-1 bytes. In this way, each column of the output state of the ShiftRows
step is composed of bytes from each column of the input state. (Rijndael variants with a larger
block size have slightly different offsets). For a 256-bit block, the first row is unchanged and the
shifting for the second, third and fourth row is 1 byte, 3 bytes and 4 bytes respectivelythis
change only applies for the Rijndael cipher when used with a 256-bit block, as AES does not
use 256-bit blocks. The importance of this step is to avoid the columns being linearly
independent, in which case, AES degenerates into four independent block ciphers.
The MixColumns step
In the MixColumns step, each column of the state is multiplied with a fixed polynomial c(x).

In the MixColumns step, the four bytes of each column of the state are combined using an
invertible linear transformation. The MixColumns function takes four bytes as input and outputs
four bytes, where each input byte affects all four output bytes. Together with ShiftRows,
MixColumns provides diffusion in the cipher.

During this operation, each column is multiplied by a fixed matrix:

\begin{bmatrix} 2 & 3 & 1 & 1 \\ 1 & 2 & 3 & 1 \\ 1 & 1 & 2 & 3 \\ 3 & 1 & 1 & 2
\end{bmatrix}

Matrix multiplication is composed of multiplication and addition of the entries, and here the
multiplication operation can be defined as this: multiplication by 1 means no change,
multiplication by 2 means shifting to the left, and multiplication by 3 means shifting to the left
and then performing XOR with the initial unshifted value. After shifting, a conditional XOR
with 0x1B should be performed if the shifted value is larger than 0xFF. (These are special cases
of the usual multiplication in GF(28).) Addition is simply XOR.

In more general sense, each column is treated as a polynomial over GF(28) and is then
multiplied modulo x4+1 with a fixed polynomial c(x) = 0x03 x3 + x2 + x + 0x02. The
coefficients are displayed in their hexadecimal equivalent of the binary representation of bit
polynomials from GF(2)[x]. The MixColumns step can also be viewed as a multiplication by
the shown particular MDS matrix in the finite field GF(28). This process is described further in
the article Rijndael mix columns.
The AddRoundKey step
In the AddRoundKey step, each byte of the state is combined with a byte of the round subkey
using the XOR operation ().

In the AddRoundKey step, the subkey is combined with the state. For each round, a subkey is
derived from the main key using Rijndael's key schedule; each subkey is the same size as the
state. The subkey is added by combining each byte of the state with the corresponding byte of
the subkey using bitwise XOR.
Optimization of the cipher

On systems with 32-bit or larger words, it is possible to speed up execution of this cipher by
combining the SubBytes and ShiftRows steps with the MixColumns step by transforming them
into a sequence of table lookups. This requires four 256-entry 32-bit tables, and utilizes a total
of four kilobytes (4096 bytes) of memory one kilobyte for each table. A round can then be
done with 16 table lookups and 12 32-bit exclusive-or operations, followed by four 32-bit
exclusive-or operations in the AddRoundKey step.[11]

If the resulting four-kilobyte table size is too large for a given target platform, the table lookup
operation can be performed with a single 256-entry 32-bit (i.e. 1 kilobyte) table by the use of
circular rotates.
Using a byte-oriented approach, it is possible to combine the SubBytes, ShiftRows, and Mix
Columns steps into a single round operation.[12]

CHAPTER 4
SOFTWARE DESCRIPTION
6.1 Overview

The HDL Designer Series tools provide a highly automated environment for managing and
exploring HDL designs. The design data is maintained as source VHDL or Verilog files which
can be created or edited using HDL text or graphical editors.
The main design manager window provides library management, data exploration, and design
flow control facilities. You can explore the logical or physical design objects defined by the
source HDL including any associated side data objects. You can display the structure and
hierarchy below any design object and compile VHDL or Verilog for individual views or
hierarchies.
Structural HDL views can be rendered as a graphical block diagram or IBD view. If a state
machine is defined in the source HDL code, it can be rendered as a state diagram and other nonstructural HDL can be displayed as a flow chart. New design views can be created using the
HDL text or graphical editors at any level of the hierarchy.
Typically the top level of a design may be represented by a block diagram, IBD view, or HDL
text view which represents the connections between the functional blocks. This view can be
split into lower level design units represented by block or component design units. Each block
(or component) can be further decomposed or its behavior described by a state diagram, truth
table, flow chart or behavioral HDL text view.
Interoperability and consistency across design styles and coding practices for developers and
development teams creating complex designs can be ensured through the DesignChecker static
checker and analysis flow.

Version control management is supported using supplied versions of RCS and CVS or can be
configured to use Rational ClearCase, Synchronicity DesignSync, ClioSoft SOS and Microsoft
or Mainsoft Visual SourceSafe.
Close integration with downstream tools for HDL simulation and synthesis allows you to
simulate the behavioral model of your design, refine and synthesize the design using compatible
tools and proceed rapidly to test and implementation.

The Design Manager Window

The design manager window is displayed when you invoke any HDL Designer Series tool.

The design manager window normally remains open throughout your working session and
cannot be closed.

The default design manager layout displays the Design Explorer window with supporting menu
bar, toolbars, shortcut bar, status bar and a tabbed side sub-window which can be hidden or
shown according to your preference.

The Design Browsers

The main source browser is always present. The source browser allows you to manage
library mapping and view the relationship between the graphical or HDL text views in the
libraries.
o
The source browser provides a design explorer for setting up library mapping and
managing libraries which is described in Projects and Libraries on page 45. Separate design
explorers can be opened to browse the contents of each library as described in Using Design
Explorers on page 74.

The sub browser displays the Side Data Browser and the Downstream browser in two
vertical panes. If the sub browser is not shown, it can be displayed by setting Side
Data/Downstream in the SubWindows cascade of the View or popup menu.

o
The side data browser displays additional design or user data associated with selected
design objects as described in Using the Side Data Browser on page 128.

o
The downstream browser does not normally contain any browsable files until you have
compiled HDL or run a downstream tool. Separate tabs are displayed for each downstream
library mapping. For example, ModelSim, LeonardoSpectrum and VCS. The downstream
browser is described in Using the Downstream Browser on page 131.

The resource browser provides a task manager tab for configuring and invoking tasks
which is described in Using the Task Manager on page 255 and a template manager tab for
maintaining HDL text templates which is described in Using the Template Manager on page
149. If the resource browser is not shown, it can be displayed by using the
button or by
setting Tasks and Templates in the Tasks menu or in the SubWindows cascade of the View or
popup menu.
The LaunchPad
The LaunchPad helps you understand the key concepts of HDS and how to apply them through
a set of demos and instructions.
Do one of the following:
o Set LaunchPad in the SubWindows cascade of the View or popup menu.
o Select the LaunchPad tab from the design manager tabbed side subwindow. The following
icons are used in the LaunchPad subwindow:

Table 1-1. LaunchPad Icons

Icon Description
Move back to previously visited pages
Move forward to recently visited pages
Return to the home page
Refresh the active page
Invoke a task
Icon Description
Run a Flash Demo
Display web page showing a set of manual
Instructions
To use the LaunchPad:

1. Make sure you have a web browser configured to display Macromedia Flash applications
installed on your system in order to be able to view the flash demos.
2. Click on any of the topic links in the LaunchPad.
3. A new page is displayed showing a list of subtopics. Each subtopic is demonstrated by a set
of links. Each link triggers one of the following:
o A Self-running flash demo.
o A web page displaying a set of manual instructions.
o A task described by the subtopic.
Changing the Design Manager Layout

The shortcut bar and design browsers can be resized by dragging the resize sashes between the
panes. The browsers are normally tiled to share the available window area but you can use the
following buttons to change the layout:

Expand browser horizontally to full width of window

Return browser to normal horizontal tiling

Expand browser vertically to full height of window

Return browser to normal horizontal tiling

You can use the

button to close a design explorer window.

Note
Tip: Horizontal or vertical scroll bars are automatically displayed when the contents of a
browser are larger than its current size.

The Menu Bar

The following pulldown menus are provided in the design manager:

A short message describing the associated command is displayed in the status bar when the
cursor is moved over any pulldown menu.

Many commands are also available in a context-sensitive popup menu which is displayed when
you press and release the Right mouse button.

Many menu items can be accessed by a keyboard shortcut using the F10 or Alt key and the
underlined mnemonic letter. For example, to save the current view, you can use the keyboard
shortcut: F10+F+S.

There are additional keyboard shortcuts defined for standard commands (such as saving a view)
using the Ctrl and Shift keys.

Toolbars

The most commonly used commands are available from toolbars in each window. Four toolbars
are normally displayed in the design manager. If they are not displayed, the toolbars can be
enabled by setting Standard, Design Manager, HDL and Tasks in the Toolbars cascade of the
View menu.

Tip: The Toolbars menu can also be displayed as a popup by clicking the Right mouse button in
the background of the toolbar area.

You can control whether tooltips are shown when you move the cursor over a toolbar button by
setting Tooltips in the Toolbars cascade of the View menu.

The toolbars and tooltips can also be enabled by using the Toolbars dialog box which is
displayed when you choose Settings from the Toolbars cascade of the View menu:

A Version Management toolbar may be displayed when a version management interface is

enabled. Refer to Version Management Toolbar on page 440 for information about this
toolbar.

The following commands are available from the Standard toolbar:

Table 1-2. Standard Toolbar

Button

Description
Create a new view, library mapping or project file
Open a view
Print the current window
Document and Visualize the selected design
Move selection to the clipboard
Copy selection to the clipboard
Paste the contents of the clipboard
Delete selected objects
Display the Properties dialog box for the selected design object

You can display a pulldown menu on the

library or project file.

button to create a new design view, test bench,

You can display a pulldown palette on the

button to document and visualize the selected

HDL declaration on a single level, hierarchically

(indicated by

), or hierarchically

through design root

(indicated by ). If any of these buttons is clicked without having a
library opened in the design explorer (or if a library is opened but does not include any design
units), a dialog box is opened prompting you to either import an existing design or create a new
design object. The same applies on clicking the Document and Visualize button in the Main
shortcut bar; refer to The Shortcut Bar on page 28 for further details.

The following commands are available from the Design Manager toolbar:

Table 1-3. Design Manager Toolbar

Button Description
Toggle the hierarchy view in the design explorer
Highlight related design objects
Explore the library selected in the design manager
Change the design explorer display mode
Display the design explorer viewpoint management
window
Display the Find tool or the Advanced Find dialog box
Show the component browser
Invoke the DesignPad text editor
Refresh the active design manager window

You can cycle through the display modes by clicking the

design units button to display

design units,
HDL files button to display the HDL files mode or the
button to display the logical objects mode in the active design explorer.

logical objects

The following commands are available from the HDL Tools toolbar:

Table 1-4. HDL Tools Toolbar

Button Description
Convert HDL view to graphical design objects
Visualize the HDL declaration as a graphical view
View generated HDL
Run design rule checks (in block diagram and ASM chart
editor only)
You can display a pulldown palette on the
(indicated by

button to choose single or

) conversion of the selected HDL text view.

You can display a pulldown palette on the

diagram

hierarchical

, IBD view

button to visualize the text view as a block

, state diagram

or flow chart

When you select one of the palette options for these buttons, it becomes the default operation
for the button.

The following commands are available from the Tasks toolbar:

Table 1-5. Tasks Toolbar

Button

Description
Hide or Show the task and template managers
Run DesignChecker flow
Run the LeonardoSpectrum synthesis flow
Run the ModelSim simulation flow
Run the Precision Synthesis flow
Run the QuestaSim simulation flow
Generate HDL from graphical views

You can display a pulldown palette on the

,
,
,
,
and
button to
operate on a single design level, hierarchically through blocks (indicated by the
overlay),
hierarchically through components (indicated by
) or hierarchically through components

from the design root (indicated by

default operation for the button.

).When you select one of these options, it becomes the

Refer to Adding a Task Shortcut on page 264 for information about adding commands to this
toolbar.
Docking and Undocking Toolbars
You can undock a toolbar by double-clicking the Left mouse button over the toolbar handle
one of the vertical separators between the toolbar buttons.

or

The toolbar is immediately undocked and appears in a floating window that can be moved
independently anywhere on the display screen.
If you double-click on the title bar above an undocked toolbar, it snaps back to the window
margin in which it was last docked.
You can also select and drag a ghosted image of a toolbar by holding the Left mouse button
down with the cursor over the toolbar. The ghosted image changes to a vertical rectangle when
you are over the left or right window margin and if released the toolbar snaps into the window
margin. A toolbar can also be docked into the bottom margin if the ghosted image is released
with the cursor between the window scroll bars and status bar. While a toolbar is undocked, you
can reshape its window and rearrange the buttons as a square or rectangular matrix.

You can hide an undocked toolbar by using the

button. The toolbar will revert to single row

(or column) format in the docked position.

The following picture illustrates an undocked Design Manager toolbar arranged as a two rows.

The Shortcut Bar

The shortcut bar provides quick access shortcuts for common setup operations, design explorer
operations, tasks and accessing viewpoints.

A single Project group is displayed when the project manager is active. Separate Explore, Tasks
and Viewpoints groups can be displayed by clicking on the group name when a design explorer
is active.

The following commands are available from the Project group in the shortcut bar:
Table 1-6. Project Shortcut Bar

Shortcut Description
Create a new project using the New Project wizard

Open a project
Create a new library using the New Library wizard
Edit the mappings for the selected library
Set the selected library to be the default library
Open a design explorer for the selected library or libraries
Create new objects or add existing design files
Set options for version management
Close the current project

The following commands are available from the Main group in the shortcut bar:

Table 1-7. Main Shortcut Bar

Shortcut

Description
Create new objects using the Design Content Creation wizard
or add existing design files
Run Design Checker flow

Run the installed Simulation tool flow

Run the installed Synthesis tool flow

Document design data as HTML and Visualize HDL views

On clicking the Document and Visualize button while not having a library opened or while the
opened library does not include any design units, a dialog box called Add a Design or Create
New Object is displayed.

The dialog box enables you to Add a Design and in this case the Add Existing Design Wizard is
opened, or you can Create a new design object and in this case the Design Content Creation
Wizard is opened.

The following commands are available from the Explore group in the shortcut bar:

Table 1-8. Explore Shortcut Bar

Shortcu Description
t
Create new objects or add existing design files
Toggle the hierarchy view for the selected object
Expand all objects below the selected object
Collapse all objects below the selected object
Search for a text string in the active design explorer
Display the viewpoint management window
Convert HDL view to graphical design objects
Visualize HDL declaration as a graphical view

The following commands are available from the Tasks group in the shortcut bar:

Table 1-9. Tasks Shortcut Bar

Shortcu Description
t
Invoke the Altera MegaWizard
Generated HDL wrapper for C or C++ views
Generate HDL from graphical views through
components
Run
the
LeonardoSpectrum flow
through
components

Table 1-9. Tasks Shortcut Bar (cont.)

ShortcuDescription
t
Generate HDL and run the LeonardoSpectrum flow
Compile HDL using ModelSim
Generate HDL and run the ModelSim flow through
components
Invoke the ModelSim simulator
Run the Precision Synthesis flow through
components
Generate HDL and run the Precision Synthesis flow
Compile HDL using QuestaSim
Generate HDL and run the QuestaSim flow through
components
Invoke the QuestaSim simulator
Invoke the Xilinx CORE generator
Run DesignChecker flow
Refer to Adding a Task Shortcut on page 264 for information about adding shortcuts to the
Tasks group.

The following command are available from the Viewpoints group in the shortcut bar:

Table 1-10. Viewpoints Shortcut Bar

Shortcut

Description
Display the viewpoint management window

Refer to Adding a Viewpoint Shortcut on page 96 for information about adding shortcuts to
the Viewpoints group. You can change the order of shortcuts by dragging a shortcut up or down
the bar. The
and
buttons are displayed if there are more shortcuts than can be displayed
and can be used to scroll down or up through the available commands. You can hide or show the
shortcut bar by setting Shortcut Bar in the View menu.
Keyboard Shortcuts

Many commands are defined as shortcuts using standard character keys, function keys and
menu accelerator key sequences which can be used as alternatives to the toolbar buttons and
menus. The standard keyboard keys can be often used to execute a command directly. For
example F3 displays the component browser. Additional commands can be executed using the
Shift, Ctrl or Alt modifier keys. For example, Ctrl+A pressed together, executes the Select All
command. Refer to the Quick Reference Index in the Help and Manuals tab of the HDS
InfoHub for lists of the keyboard shortcuts supported in each window. To open the InfoHub,
select Help and Manuals from the Help menu.

Menu Accelerator Keys

Accelerator key sequences are defined for most menu commands (indicated by an underlined
character beneath the key letter in the menu) and can be activated by using the F10 key. For
example, pressing F10&V&T&S in succession is equivalent to selecting Settings from the
Toolbars cascade of the View menu.
Dialog Box Shortcuts

In general, the
or Enter key corresponds to clicking the default button in a dialog box.
This is usually the OK button which confirms and closes the dialog box.

The Esc key corresponds to clicking the Cancel or No button. The

move to the next button or entry field in the dialog box.
Mouse Buttons

key can be used to

The mouse is the basic input device used for pointing, selecting and executing toolbar or menu
commands.

The mouse buttons are referred to as Left, Middle and Right although many workstations allow
the buttons to be changed for the convenience of left-handed users.

Note
The Middle mouse button function can be executed by using the Left and Right buttons
together on a two-button mouse.
Status Bar

The status bar provides information about the current status of the associated window. It
typically includes information about the current command and warning messages when you
attempt an invalid operation. The status bar also displays the function of the button or menu
option under the cursor. You can choose to hide the status bar by toggling the Status Bar option
in the View menu.
Object Tips

When you move the cursor over any object in the design manager windows, summary
information about the object is displayed in a popup object tip window. The tip remains
displayed until the cursor is moved to another object. This feature can be disabled or enabled by
setting the Object Tips option in the View menu.

File Browser

The standard Windows file browser is used on a PC to locate files (for example when saving a
project file or reading a HDL source file list in the HDL Import wizard). However an internal
browser is used on UNIX systems.

For example, the following picture shows the file browser used to save a HDS project file at:
/mnts/project/Designs/hds.hdp:

This browser initially displays the directories and files in the currently selected directory. You
can move down into a directory by double-clicking on a folder icon or go directly to a different
directory by entering a partial pathname in the Filename entry box and using the
button. You
can move up through the directory structure by selecting an entry from the Look in pull-down or
move up one directory by using the button.
Directory Browser
The standard Windows directory browser is used on a PC to browse folders (for example when
setting library mapping or locating HDL source files in the HDL Import wizard). However an
internal browser is used on UNIX systems. For example, the following picture shows the
directory browser used to create and rename a directory at: /tmp/hds_scratch/NewDirectory:

This browser initially displays the currently selected directory. You can move down into a
directory by double-clicking on a folder icon or go directly to a different directory by entering a
partial pathname in the Directory entry box and using the
button. You can move up through
the directory structure by selecting an entry from the Look in pull-down or move up one
directory by using the
button. You can use the Create Directory button to create a new
directory (with the default name NewDirectory) and rename a directory by selecting its name
and clicking again to edit the name in place.
HTML Browser

HDL Designer Series includes HTML format help files for the batch command language and
Module ware part descriptions. These files can be opened in your default Web browser on
Windows systems. If you click on a HTML link on UNIX or Linux systems, your search path is
checked for a recognized web browser program. If no web browser is found or more than one
browser is recognized, the Select a Program to View HTML dialog box is displayed.

For example, the following dialog box is displayed when the Konqueror, Mozilla and Netscape
browsers are available on a Linux system:

You can access the dialog box to change your HTML browser by choosing HTML Browser
from the Options menu.
Editor Windows

A separate editor window is opened when you open a HDL text, block diagram, IBD view,
symbol, tabular IO, state diagram, flow chart or truth table view. Each window can be moved,
resized or iconized and has its own menu bar, one or more toolbars and a status bar. Any open
window can be de-iconized or popped to the front of your workstation display by selecting its
name from the Window menu.
You are prompted to save any changes to the active view when you close a window which is the
last open view of a diagram or table and prompted to exit from the tool if the window is the last
open window. Refer to the Design Pad Text Editor User Guide for information about the built-in
HDL text editor or the Graphical Editors User Manual for information about the graphical
editors. You can optionally set the HDL text editor interface to use one of the alternative Text
Editors described in Appendix D.
Log Window
The log window is used to display information messages and enter Tcl (Tool Control Language)
commands. There is normally a Console tab for general invoke and preference information and
separate Task Log tabs which transcript messages from HDL Import, generation, compilation
and other downstream tasks. The log window is automatically displayed when error or warning
messages are encountered or can be opened at any time by choosing HDS Log Window or Task
Log Window from the Window menu in the design manager or any graphic editor.

The standard Window controls for your workstation can be used to iconize or close the log
window and additional controls are provided by a dockable toolbar.
Log Window Toolbar
The following commands are available from the Log Window toolbar:

Table 1-11. Log Window Toolbar

Button Description
Saves the log window contents to a specified file
Moves the selected text to the paste buffer
Copies the selected text to the paste buffer
Pastes contents of the paste buffer on the command line
Clears all lines in the current log window tab
Close the current tab
Go to previous error message
Go to next error message
Go to previous warning message
Go to next warning message
Display source object corresponding to selected message
Display generated HDL corresponding to selected
message
Disables automatic display of log window when updated

You can disable automatic display of the Log window by using the
button in any tab. When
shown pressed, automatic display is disabled and the log window will remain closed (or
minimized) until explicitly displayed from the Window menu. Error messages are highlighted in
red and warning messages in blue. You can use the
button to move to the next error or the
button to return to the previous error. Similarly you can use the button to move to the next
warning message or the

button to return to the previous warning.

You can select any word by double-clicking with the Left mouse button or an entire text line by
triple-clicking. Multiple lines can be selected by using the Shift+Left (extend selection) keys or
by dragging with the Left mouse button to select the required text. You can select all text in the
active tab by using the Ctrl+A shortcut.

You can use the

button to save the contents of the active tab to a specified file and use the

button to copy the selected text to the window system clipboard.

You can clear the entire contents of the current tab (except for the command prompt in the
Console tab) by using the

button.

Console Log
The main Console tab displays information notes, errors or warnings encountered while loading
preferences and resource files. The Console tab can be opened at any time by choosing HDS
Log Window from the Window menu in the design manager or any graphic editor. It can also be
displayed by clicking the Console tab when the Task Log tab is already open.
A console prompt is displayed at the bottom of the Console tab after any note, warning or error
messages. The prompt comprises the name of your current working directory enclosed in
parentheses followed by an integer (which increments when a command is entered) and the %
character. For example:

(Designs) 1 %

The console command line accepts all standard Tcl commands plus extended API (Application
Program Interface) commands which support the HDL design process. The API commands are
described in a HTML manual which can be opened in your Web browser by choosing Tcl
Command Reference from the Help menu. Information about standard Tcl commands can be
found on the Tcl Developer Xchange web site at: http://www.tcl.tk/man/tcl8.4/
You can also run any other executable program that is accessible in your default search path
(specified by the $PATH variable).

The following color conventions are used in the Console tab:

Table 1-12. Console Tab Color Conventions

Description

Color

Error messages
Warning messages

red
blue

Note messages

dark green

User entry recognized as a command

green

User entry recognized as a command argument

wheat background

Unrecognized user entry

navy blue

Other text such as prompts and script output

black

You can use the

clipboard or the

button to move text on the command line in the Console tab to the
button to copy text from the clipboard to the command line.

You can also use the

line.

mouse button to paste the current selection directly to the command

Partially entered commands, variables and files in the current working directory can be
automatically expanded by using the Esc or

keys. You can also use this feature to expand

environment variables. For example, if you enter set HDS_HO and press
expanded to:

, the command is

set env(HDS_HOME)
You can recall recently used commands using the

key or by entering the Tcl history

command. The following shortcuts are also supported:

!!
Repeats the last command
!n
Repeats command number n
!string
Repeats the last command matching string
You can change the working directory using the cd command.

Note
Note that the exit command exits from the console and terminates the HDL Designer
Series session.

Task Log

The Task Log tab is automatically displayed to monitor generation, compilation or other task
operations including any error or warning messages detected by the HDL parser or downstream
compiler. The Task Log tab can be displayed at any time by choosing Task Log Window from
the Window menu or by clicking the Task Log tab when the main Log tab is already open.

Messages in the Task Log marked by the

icon are cross-referenced to the corresponding
source object and generated HDL. You can automatically display the source object by doubleclicking over the message or by selecting the message and using the
button to open the
corresponding source editor. When a diagram is displayed, the associated object is shown in the
middle of the diagram and the window is zoomed if necessary. However, if the object is hidden
or normally only accessed from a dialog box, you may need to display the dialog box before it
can be edited. If the source object is a HDL text view, the HDL file is opened at the appropriate
line in the text editor.

You can also display the generated HDL corresponding to a Task Log message by using the
button. The generated HDL is displayed in the text editor but should not normally be modified.
It is better to correct the error in the source view and regenerate the HDL.

An existing Task Log tab is re-used if the last generation or downstream activity has been
completed. However, multiple tabs may be displayed when concurrent activities are required.
(For example, if the previous HDL compilation is still in progress.)

An
icon is shown before the title for any log tab which has been updated since it was last
viewed. For example, Task Log 2 and Task Log 3 in the picture above. You can close the
active tab using the
closed.

button. However the two default tabs (Log and Task Log) cannot be

Batch Command Language

Batch commands are supported using the same Tcl interpreter that is supported by the log
window Console tab and can include any standard Tcl commands or extended HDL Designer
Series API (Application Program Interface) commands.
Command Files
A HDL Designer Series tool can be invoked in batch mode by using the -tcl switch to load a
Tcl script containing API commands.
For example:
hdl_designer -tcl my_batch_script.tcl
You can also load a Tcl script when you are invoking the graphical user interface by
specifying the pathname using the HDS_TCL environment variable or by using the -do
switch.
For example:
hdl_designer -do my_load_script.tcl
The Tcl script can also include any standard Tcl commands such as the source command (to
run another script) or the puts command (to output text).
Redirecting Output

It is often useful to redirect the output from a batch command script to a file. This can be
done in a UNIX Bourne shell or Windows command prompt by using the operator > to
redirect stdout to the file log.txt, then redirect the stderr output to the same place as stdout
using the operator
2>&1. For example:
Run a command script and redirect the log to a file:
hdl_designer -tcl batch.tcl > log.txt 2>&1

The standard output stream can be filtered using a tool such as the MKS tee utility if you
want to display a transcript (including the output from any puts commands) in the shell and
also write into a file. For example: Run a script and display the results in the shell and also
redirect into a file:
Closing Windows and Exiting HDS
You can close the current editor window by choosing Close Window from the File menu.
Hierarchical, concurrent or clone windows are not closed. You can also close all graphical
editor and DesignPad windows from the design manager by choosing All Editor Windows
from the Close cascade of the File menu. If a graphical editor window has been edited and the
window is the last open window view, you are prompted whether to save the diagram or
table.
You can exit from the application by choosing Exit from the File menu in any window or by
closing the window with the Shift+
keys held down. All open graphic editor, design
manager or help windows will be closed. You are prompted whether to save any open
diagrams which have been modified since they were last saved.
Any HDL text views opened in the DesignPad text editor are automatically closed when you
exit from a HDL Designer Series tool. However, HDL text windows are not closed
automatically if you are using an alternative editor. If you close the last window in the
session, you are prompted whether to exit from the application.
The position and size of each window is remembered and re-used when the window is reopened. The displayed view is also remembered for the design explorer and the graphical
editor windows.
The libraries displayed in the design manager are automatically re-opened when you next
invoke the tool. Expanded libraries and design units are shown as they were displayed when
the window was exited.