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ELSEVIER
Electric
Power
Systems
Research
36 (1996)
SYSTEf7lS
RESERRCH
45-55
of
27 July
1995
Abstract
This paper describes a digital technique for detecting internal faults in stator windings of synchronous generators. The technique
uses positive- and negative-sequence models of the synchronous generator, and voltages and currents measured at the generator
terminals. It does not need information concerning the machine parameters and is applicable to all types of generators, irrespective
of their size. Fault discrimination
characteristics and a digital algorithm based on the proposed technique are described. The
performance of the proposed technique was evaluated using fault data generated by simulations using an electromagnetic transient
program. EMTDC.
Fault data were also acquired by subjecting a laboratory generator to internal and external faults. Results of
the studies using simulated and experimental data are included in the paper. The results indicate that the proposed technique can
detect faults including open circuits and faults that short-circuit windings of one phase.
Digital
Keywords:
techniques;
Fault
detection;
Synchronous
generators;
1. Introduction
Electric
power
utilities
and
industrial
plants
tradi-
currents
for detecting
phase faults.
The
Hope
protec-
C 1996 Elsevier
0378-7796(95)01013-D
Science
reserved
Stator
winding
protection
100% stator
winding
protec-
paper
describes
the development
of a digital
tech-
generators.
The
technique
uses a simple
2. The technique
The two-machine
system of Fig. 1 is used to describe
the technique. In Fig. 1, Gx is the generator being
protected and the external network is represented by a
transmission
line. Z,, and an equivalent source Gy.
- ( YJprc,iu,t
(1)
(2)
where ( Vx,)prrf:ault and (Zxl)prefau,t are the positivesequence voltage and current
at bus X prior to
the occurrence
of the fault, and ( Vx,)postf.u,t and
(4 I )postfault are the positive-sequence voltage and current
at bus X after the occurrence of the fault.
Consider an impedance-measuring
relay, installed at
bus X, which looks into the generator and uses the
incremental positive-sequence
voltage and current. The
relay voltage and current are given, respectively, by
Vre,ay = A Vx, = - Z,,,AZ,,
(3)
and
Fig. I. Single-line
diagram
of a two-machine,
three-phase
power
system. Z,, and Z,, are the neutral grounding
impedances
of generators Gx and Gy, respectively.
Reference
Bus
N1
(4)
Lay = - AL,
Substituting
Vrrlay = -qdelay
(5)
Reference
Bus
N1
(IX I)post-fault
Bus Y
(b)
Vrrlay
L?lar
sxl
(6)
(7)
and
hay = - 42
(8)
Bus Y
Bus X
w
Fig. 2. Positive-sequence
networks
for the power system of Fig. I
(external
fault): (a) prefault,
(b) postfault,
and (c) Tht-venins
equivalent circuit.
V&y = Z&lay
(9)
the
~relav z
I,,I,, = 5X2
(10)
Electric
Power
S~~.siems Rtwarch
Vrd iv
L_=
I
-a,
16 (1996)
45-55
41
+Z,,,)
(15)
and
Jrc,ay = AI,,
(16)
3. Fault discrimination
Fig. 3. Positive-sequence
networks
for the power system of Fig. I
(internal
fault): (a) prefault.
(b) postfault.
and (c) Thkvenins
equivalent circuit. (Note 1: this is a crude machine representation
which is
used only for the purpose of developing
the proposed
technique.)
(11)
and
Lay = Ai,,
(12)
48
Power
Re[Zl
Fig.
4. Fault
discrimination
characteristics.
tally very small compared with their reactive components and, as a result, large errors can be encountered
in the estimation
of the resistive portion
of the
impedance. Only the reactive portion of the impedance,
therefore, is used for fault discrimination.
Fig. 4 depicts
the zones of discrimination
in the impedance plane for
internal and external faults.
4. The algorithm
The fault detection technique outlined in the previous
section was used to develop a digital algorithm for AC
generator stator winding protection. Generator terminal voltages and currents, sampled simultaneously at a
predefined rate, are used by the algorithm. Specifically,
the following steps are performed.
Step 1. Initialize the trigger signal, TRIGGER,
and
the two trip counters, TCOUNTl
and TCOUNT2,
to
zero.
Step 2. Test if TRIGGER
is one. If if has been one
for two consecutive sampling intervals, save the most
recent cycle of prefault phasors to a holding buffer and
proceed to Step 7. Otherwise proceed to Step 3.
Step 3. Obtain the next set of three phase voltages
and three phase currents at the machine terminals.
Step 4. Calculate the 60 Hz voltage and current
phasors for the three phases.
Step 5. Compute the positive- and negative-sequence
phasors and store them in the processors memory.
Step 6. Compare the most recent voltage and current
samples with voltage and current samples from the
previous cycle. If the change is greater than a predefined threshold,
V PMARG
for voltage and C
PMARG
for current, then set the trigger indicator,
TRIGGER,
to one. Otherwise, set TRIGGER
to zero.
Revert to Step 2.
Step 7. Compute the positive- and negative-sequence
incremental voltages and currents.
Step 8. Compute the impedances seen by the relay
using the incremental voltages and currents.
Step 9. Test if the positive-sequence
reactance is
positive.
If it is, decrement
the trip counter,
S.ystrrz.s
Research
36 (1996)
45 55
TCOUNTl,
by one. If TCOUNTl
becomes negative,
then set it to zero.
Step IO. Test if the positive-sequence
reactance is
negative. Also, test if the magnitudes of both the positive-sequence voltage and current are greater than a
predetined minimum value, EPSILON.
If these two
conditions
are met, increment
the trip counter,
TCOUNTI.
by one; otherwise, TCOUNTl
retains its
previous value.
Step 11. Test if the negative-sequence reactance is
positive.
If it is, decrement
the trip counter,
TCOUNT2,
by one. If TCOUNT2
becomes negative,
then set it to zero.
Step 12. Check if the negative-sequence reactance is
negative. Also, test if the magnitudes of both the negative-sequence voltage and current are greater than a
predefined minimum value, EPSILON.
If these two
the trip counter,
conditions
are met, increment
TCOUNT2.
by one; otherwise, TCOUNT2
retains its
previous value.
Step 13. Test if either TCOUNTl
or TCOUNT2
has
exceeded a prespecified value, THRESHD.
If either has
exceeded THRESHD,
then issue a trip command; otherwise, proceed to Step 14.
Step 14. Wait for the next set of samples and acquire
them. Calculate the 60 Hz voltage and current phasors
for the three phases. Calculate the positive- and negative-sequence phasors. Return to Step 7.
5. Generation
of test data
The performance
of the proposed algorithm
was
tested using fault data. Data needed for testing were
generated by simulations
as well as by subjecting a
laboratory generator to different types of faults.
5.1. Simuluted
dutu
Powrr
S~mms
Research
._..............
Emtdc
Data
Ra
1x3
: xd
1 xd
=
s
=
=
: xq
=0.31
Generator
0.003
1.46
0.48
0.36
49
ohms (0.002pu)
ohms
(0.92~~)
duns (0.3opu)
obmn (0.22pu)
ohms
Tdo= 0.029
Tqo= 0.034
- -
(O.Slpu)
ohms (0.29pu)
eawnds
~eeonds
wzond~
Location
of Applied
Internal
Location
of Applied
External
( Close-in
Faulta
File
Unit
( Step-up
) Transformer
Transmission
(lOOkIn)
Lie
13.3kV,
rms, line-line
23OkV,
mw, line-line
Bus
Fig.
3-phase
model
Faulta
Generation
5COMVA
8ource.
5. System
External
Fault
Bulk
equivalent
of Applied
( Distant
TransmissianL.iie
(lOokIn)
Faults
:
I
Location
Fault
Thevetis
45-55
xs = 0.46
1 Tdo=5.2
120 MVA
Unit
36 (1996)
for simulating
data using
EMTDC.
duta
50
Power
Systems
Research
36 (1996)
45-55
6. Test results
(e)
Trip
voltage
bus
Fig. 6. An experimental
set-up for acquiring
on a laboratory
generator.
data during
staged faults
lO=Orr,
l=on)
$11
0
10
20
30
40
Sample
50
M)
10
Number
0-J
Fig. 7. Performance
circuit on phase A.
eonrunt
Signal
of the proposed
technique
for an internal
open
1::
10
sipnd
20
to-off,
l-on)
30
40
Samph Number
50
60
70
(a)
Poaitire
ssqus.ce
Imped.oes
~Ra121
Ei
-s -0.3
-1ImlZl
-0.6
0
10
20
30
Sample
40
60
so
70
Number
(b)
-saFare03
I
-3,:
MZI
JmIZl
SO
60
70
50
60
70
tc)
Positive
1
Sequence
Trip
Count
!I]
0
10
20
30
40
Sample Number
Cd)
Negative
SequenceTrip
Count
%I-M
10
20
so
Sample
40
Number
w
Trip signal
CO=&,
l=cm,
i?:i
0
10
20
30
40
50
60
70
SampleNumber
(0
S!~stnns
Resrurch
36 (1996)
45.-55
51
52
Power
k:l:
_.
signd
(0=&r,
System
Research
36 (1996)
45-55
Trigger
signal
(O=off,
1=on)
f]
0
10
20
30
40
Sample
50
60
70
Number
(a)
Pceitive
Sequence
Impedance
0
I 4.15
-ReRe[z1
d=
-IIm[Zl
4.3
-0.45
0
10
20
30
Sample
40
Number
Izoo)
50
60
70
(b)
Negative
Sequence
Impedance
10
20
30
40
Sample Nnmber
60
50
70
(a)
1 4.2
Re[Zl
% -0.4
ImIZl
a.6
0
10
30
--Re[Zl
--+--
30
Sample
40
Im[Zl
20
30
Sample
40
Number
60
60
Sequence
70
Sequence
Trip
30
40
Count
70
j
tjp/
0
(b)
Negative
60
w
Positive
10
50
Number
10
30
Sample
Impedance
50
60
70
50
60
70
50
60
70
a fault
that
Number
63
Negative
Trip
Count
i EJp-
-ReRez1
-----b
Sequence
Im[Zl
10
20
30
Sample
40
Number
(e)
0
10
20
30
40
Number
Sample
50
60
70
Trip
w
Positive
Trip
Count
10
~
10
20
30
Sample
Sequence
yj;1
50
60
10
20
Trip
30
50
60
70
50
60
70
Number
(d
Trip
Signal
(O=off,
l=on)
iq
0
10
20
30
Sample
40
Number
(6
Fig. 9. Performance
of the algorithm
phase-to-ground
fault on phase A.
30
Sample
40
Number
for
of the proposed
of phase C.
technique
for
Count
40
Sample
al
70
~
0
l=on)
0-J
40
Number
w
Negative
(O=off.
Lq
Sequence
j$
0
Signal
a close-in
external
single
the negative-sequence trip counter exceeding the predefined threshold of 15. The positive-sequence trip
counter was incremented for a short duration while the
positive-sequence reactance dipped slightly below zero
for a few samples. However, when the positive-sequence
reactance became positive again, the positive-sequence
trip counter was decremented to zero. The total time to
trip from fault inception, including filter delay, was
approximately 31 ms or 1; cycles.
A phase-to-phase fault was applied at the generator
terminals. Fig. 12 shows the results of this test. The
fault occurred at sample number 32 and a trigger signal
53
Trigger
siid
co=dr,
30
Sample
40
Number
.H
0
20
10
Positive
.squence
20
Positive
--Rez1
-
-0.25
-0.5 1
0
60
70
1
10
20
30
40
Sequence
Impedance
-Re[Zl
Impedance
--bIm[Zl
-0.5 J
0
10
20
30
Sample
40
Number
50
60
70
Cc)
-0.5 t
1
0
70
0.75
60
d -0.26
I
0.25
4.25
50
Number
0.25
0.5
t
5
Im[ZI
(W
30
40
50
Sample
Number
(a)
Sequence
70
Impedance
3
B
Negative
10
60
0.25
60
(a)
Sample
!:I..
l-an)
Positive
10
30
20
40
Number
Sample
50
60
z-
Sequence
Trip
Count
70
(b)
Negative
Sequence
10
20
30
Sample
Impedance
40
Number
50
60
70
50
60
70
50
60
70
(4
Negative
Sequence
Trip
Count
-ReRe[z1
b
:;I-
Im[Zl
0
0
10
20
30
Sample
40
Number
Positive
50
60
Trip
20
30
Sample
50
60
10
Sequence
Trip
10
20
30
Sample
40
Number
50
60
70
50
60
70
(e)
nip
Signal
(O=off,
l=an)
s;]
0
10
20
30
Sample
40
Number
(f-l
20
30
Sample
40
Number
of the proposed
technique for a phase-to-phase
terminals
between phases B and C.
Count
p]/
0
( 0 = MT, 1 = on )
(f-l
70
Cd)
Negative
Signal
$;I
Count
40
Number
40
Number
63
10
30
Sample
70
(c),.I
0
20
Trip
Sequence
j El
10
technique
for an internal
single
A double phase-to-ground
fault involving phases B
and C was applied external to the generator. The
voltage and current waveforms
recorded at the terminals of the generator for this condition are shown in
Fig. 13. The results showing the performance of the
algorithm for this test are shown in Fig. 14. The fault
occurred at sample number 31. Fig. 14(a) shows that
the trigger signal was activated at sample number 33.
The sequence impedances were calculated from sample
33 onward and and are depicted in Fig. 14(b) and (c).
Both sequence reactances remained positive, which kept
both the positive- and negative-sequence trip counters
54
Powr
S,ystms
Research
45-55
TriggE
siid
co.oIT,
1-m)
11
%01
0
a3
10
30
40
sample
50
60
70
Number
(a)
Panitive
7. Conclusions
36 (1996)
10
Sequence
20
Impedance
30
40
Sample
Number
50
60
70
(b)
27
1
.3
o 0.
rk[Zl
-Im[Z]
-1 1
0
10
20
30
Sample
40
Number
50
60
70
Cc)
Fbsitive
Sequence
ji$
Trip
Count
-~
0
10
20
40
30
Negative
Sequence
pJ
Trip
50
60
70
50
60
70
50
60
70
Count
~
0
10
20
30
sample
40
Number
(e)
31
Sample
41
Number
Trip
signal
(O=ofr,
l=on)
E;l
0
@I
la
11
21
It-
31
Sample
41
Number
-1c
51
10
61
71
(b)
Fig. 13. Filtered and resampled (a) voltage and (b) current waveforms
at the relay for an external
double phase-to-ground fault involving
phases B and C.
20
30
Sample
40
Number
of the proposed
technique
for an external
fault involving
phases B and C.
References
[I]
M.S. Sachdev
lio~z Systems.
(Coordinator),
IEEE Tutorial
Microprocessor
Course Text.
Relays
Power
and ProtecEngineering
T.S. Sidh
[2]
[3]
[4]
[5]
[6]
et crl. , Electric
Poner
Society
Special Publ. No. 88 EHO269-I-PWR.
IEEE, Piscataway. NJ. USA, 1988.
M.S. Sachdev and D.W. Wind, Generator
ditrerential
protection
using a hybrid
computer,
IEEE
Trams. Power Appar-. Syst.,
PAS-92 (1973) 2063-2072.
G.S. Hope,
P.K. Dash and O.P. Malik.
Digital
differential
protection
of a generating
unit scheme and real-time
test results,
IEEE Trans. Power Appar. Syst.. PAS-96
(1977) 502-512.
H. Tao and I.F. Morrison,
Digital
winding protection
for large
generators,
J. Eiecfr. Electron.
Eng. Ausf.. 3 (1983) 316-321.
P.K. Dash, O.P. Malik and G.S. Hope, Fast generator
protection against internal
asymmetrical
faults. IEEE Trans. Po~mer
Appar. Syst., PAS-96 (1977) 1498~1506.
G. Benmouyal,
S. Barceloux
and R. Pelletier,
Field experience
with a digital
relay for synchronous
generators,
/EEE Truns.
Power Delivery,
7 (4) (1992) 1984- 1992.
Svstems
Research
36 (1996)
45 -55
55