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EE282 Lab 2

Adder and Magnitude Comparator


2.1 Objectives
Complete the design, construction, and test of a 4-bit binary to excess-3 code converter.
Complete the design of a design of a signed number adder with overflow detection.
2.2 Components needed
7483 4-bit binary adder
7485 4-bit magnitude comparator
7404 inverter
7410 triple 3-input NAND gate
Five LEDs (use those in lab kit)
One 4-position DIP switch (use the lab kit)
2.3 Theory on 4-bit Excess-3 Code
An excess-3 code uses 4 bits to encode a 4-bit BCD number. The resulted code is 3 greater than the corresponding
binary code. To do the conversion, we either add 0011 or 1001 to the binary input number. When the binary number
is between 0000 and 1001, we need to add 0011 to the number. If the number is greater than 1001, we should add
1001. The partial schematic for performing BCD to excess-3 conversion is given in Figure 2.1.
2.4 Lab procedure
Complete the connection to B3..B0 and C0 so that the given circuit in Figure 2.1 can convert the input BCD code
into Excess-3 code. Wire the circuit and test the input with all possible input combinations and then fill out Table
2.1.
Hint. Take your inputs from A<B, A=B, or A>B outputs of the comparator 7485. The signal A (carry) is shown in
Figure 2.1.

2.5 Overflow Detection


Fixed-point signed numbers are stored in most computers in the manner illustrated in Table 2.2. Positive numbers
are stored in true form and negative numbers are stored in 2s complement form. If two numbers with the same sign
are added, the answer can be too large to be represented with the number of bits available. This condition, called
overflow, occurs when an addition operation causes a carry into the sign bit position. This occurs when the most
significant bit of the sum is different from the sign bits of two numbers. This situation is illustrated in Figure 2.2.
As a result, the sign bit will be in error, a condition easy to detect. When two numbers with opposite sign are added,
overflow cannot occur, so the sign bit will always be correct.
Start with the 7483A adder and LEDs and resistors as shown in Figure 2.3.

Consider the problem of detecting an overflow error. We need consider only the sign bit for each number to
be added and the sign bit for the answer.
Complete the Karnaugh map of the output (shown in Figure 2.4) to see whether minimization is possible.

Write the Boolean expression for detection of an overflow error in your report.
Note that the signals going into the box in Figure 2.3 are A4, B4, and 4. If you apply DeMorgans theorem
to your Boolean expression, you can draw a circuit that uses only these inputs. Draw the circuit in the box.
Build and test your circuit.

The circuit of Figure 2.5 should turn on the LED whenever the input number is less than 8 or greater than 12.
Complete the design by showing where each of the remaining inputs, including the cascading inputs, is connected.
Equation for Error is X = ______________________________

A
input

A3
A2
A1
A0
B3
B2
B1
B0
A <B
A =B
A >B

A3
A2
A1
A0
B3
B2
B1
B0
A <B
A =B
A >B

7485
A <B
5.0V
A =B

A >B

330

7402

7485
A <B

A =B

A >B

Figure 4.5 Circuit for detecting numbers greater than 12 and less than 8