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Digital System Design with PLDs and FPGAs

Kuruvilla Varghese
DESE
Indian Institute of Science
Kuruvilla Varghese

Your Idea or Expectation

What is your idea of this course?

Why are you learning this course?
What do you think should be taught?

Kuruvilla Varghese

Course Objective

Digital Systems Design

Specifications to Implementation
Algorithm to Architecture (Front end design)
Partitioning, Design of blocks, Timing Analysis
Device Technology: PLD, FPGA
Design entry: VHDL
Case studies (Communications, Embedded Systems,
Computer Architecture)
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Pre-requisite

Digital Systems

Boolean Algebra, Minimization

Gates, Combinational Logic
Flip-flops, Registers, Counters
Timing
CMOS circuits

Basics of Micro-processors
Basics of Computer Architecture
Basics of Communication Networks
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Course Contents

Advanced Digital Design

Top-down Design, Data path, Controllers, Timing,

Programmable Logic Devices (PLDs)

Architecture, Applications, Optimal Design,

Field Programmable Gate Arrays (FPGAs)

Architecture, Applications, Optimal Design,

VHDL (VHSIC-Hardware Description Language)

VHDL for Synthesis

Case Studies
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At the end of the course

System Level
Given a set of specifications for a digital system,
you will be able to design the system meeting the
specifications.
In particular, given an algorithm you will be able
to design the datapath and the controller(s) to
implement the functionality.
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At the end of the course

Digital Systems
You will be able to design the datapath using
higher level combinational and sequential blocks.
You will be able to solve the functional and timing
problems in the datapath.
You will be able to resolve various issues related
to the controller design.
You will be able to resolve synchronization issues.
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At the end of the course

VHDL
You will be able to write a VHDL code to implement a
particular design/block.
You will be able to analyze a VHDL code and infer what
circuit a synthesis tool might generate out of a code.
You will know how the VHDL simulation tool simulates the
code.
You will be able to write test benches to automate the
verification process.
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At the end of the course

PLDs
You will be able to choose a particular PLD for a
particular application.
You will be able to design and code to exploit the
architectural features of PLD

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At the end of the course

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FPGAs
You will be able to choose a particular FPGA for a
particular application.
You will be able to use FPGAs in your design,
meeting the area and delay constraints and estimate
the power consumption.
You will be able to design and code to exploit the
architectural features of FPGA.
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Exercises

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Suggest Exercises for you to work

Exercises covers various aspects covered in course,
deal with concepts
Mini Project
Use PLD, FPGA Free Tools from Xilinx, Altera,
Atmel, Lattice etc.
If possible, try to work on PLD/FPGA kits
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References

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John F Wakerly, Digital Design: Principles and

Practices, Prentice Hall
Kevin Skahil, VHDL For Programmable Logic,
Addison Wesley.
Zainalabedin Navabi, VHDL. Analysis and
Modelling of Digital Systems, McGraw-Hill
Neil H E Weste, David Harris, Ayan Banerjee,
CMOS VLSI Design, Pearson Education.
Papers, FPGA Data sheets
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Digital System Design with PLDs and FPGAs

Overview
Kuruvilla Varghese
DESE
Indian Institute of Science
Kuruvilla Varghese

Hierarchy

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Learning
Bottom up
Transistor => Gates => Combinational => Sequential =>
Computing Blocks/Controllers => System

Design

Top down
Processor => ALU, Reg, =>
ALU => Adder, Sub
Adder => Gates => Transistors
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Learning: Level 0 - MOS Transistors

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Learning: Level 1 - Gates

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A

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Learning: Level 2 - Full Adder

A
0
0
0
0
1
1
1
1

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B
0
0
1
1
0
0
1
1

Cin
0
1
0
1
0
1
0
1

S
0
1
1
0
1
0
0
1

Co
0
0
0
1
0
1
1
1

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Learning: Level 3 - Adder

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Learning: Level 4 - Multiplier

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Design: Top Down

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Level 0

Level 2

Level 1

Level 3

Level 4

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Digital Design: Major Constituents

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Function / Logic
Combinational
Boolean Algebra, Minimization, Functions, Gates,
Encoders, Decoders, Multiplexers, Demultiplexers,
Parity circuits, Comparators, Priority encoders, Opendrain outputs, and Tri-state outputs, Schmitt-trigger
inputs, Adders, Subtractors, Incrementer, Decrementer,

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Major Constituents: Functionality / Logic

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Sequential

Flip-Flops, Latches
Counters, Registers, Shift Registers
Finite State Machines (FSM)
ROM, EPROM, EEPROM
SRAM, SSRAM
DRAM, SDRAM
FIFO
CAM
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Minimization

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Karnaugh Maps
Graphical tool, for humas

Quine-McCluskey (QM)
Minimal solution, Complexity

Espresso
Heuristic based on QM, Faster
Near minimal solution
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Minimization

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Multi-Level minimization
Decomposition (in to multiple terms)
Extraction of common sub-expressions of multiple
outputs
Factoring
Substitution
Flattening
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Functions and Gates: AND

A

1
1

0
1

0
1

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A, B and Y Active High

A
B

A, B and Y Active Low

A
B
Y=AB
Y/ = A/ + B/

De Morgans Theorem

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Functions and Gates: AND

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AND Gate AND, and OR Functions

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Functions and Gates: NAND

A
0
0
1
1
A
0
0
1
1

B
0
1
0
1
B
0
1
0
1

Y
1
1
1
0
Y
1
1
1
0

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A, B Active High and

Y Active Low - AND
A
B

A, B Active Low, Y Active High

- OR
A
B

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Functions and Gates: NAND

A
0
0
1
1

B
0
1
0
1

Y
1
1
1
0

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Invert
A

NAND Universal Gate

AND, OR and Invert functions

NAND Gate AND, OR, and Invert Functions

AND Gate AND and OR Functions
NOR Gate AND, OR, and Invert Functions
OR Gate AND and OR Functions
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Functions and Gates

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AND - OR

NAND - NAND

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Functions and Gates

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Y = (A/ + B/) C/
A
B
Y
C

A
B
Y

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Encoder

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In a binary encoder, distinct inputs are coded in to binary

outputs (e.g. 8 inputs are encoded to 3 binary bits).
Implementation uses OR gates
When we assign priority to inputs, then the encoder is
called priority encoder
I0
I1

O2
O1
O0

I7
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Encoder

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An encoder can encode some input code to another

code but, the number of output bits will be less
than input bits

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Decoder

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In a binary decoder, binary inputs are decoded to produce

distinct outputs (e.g. 3 bit binary number is decoded to
produce 8 distinct outputs). Implementation uses AND gates
A general decoder can convert a code to another code and
number of bits in input will be less than the number of bits
in the output
O0
O1
I2
I1
I0
O7
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Tri-State Gates
EN
Y

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0, 1, Z (High Impedance)
Multiplexing
Buses

EN/
A

EN

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Multiplexer

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0 1 2 3

A
B
C
D

sel

4 to 1 Mux (1 bit), 4 AND gates of 1+2 inputs, an OR gate

of 4 inputs
2n to 1 Mux (1 bit), 2n AND gates of 1+n inputs, and an OR
gate of 2n inputs
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De-Multiplexer

3 2 1 0

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W
X
Y
Z

sel

1 to 4 De-Mux (1 bit), 4 AND gates of 1+2 inputs

1 to 2n De-Mux (1 bit), 2n AND gates of 1+n inputs

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Multiplexer / De-multiplexer
A
B
C
D

3 2 1 0

0 1 2 3

A
B
C
D

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sel

sel

Text book Picture

Real Systems
May not be symmetrical or ordered
You may not see a explicit de-multiplexers
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Latch / Flip Flop

Latch
D

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Flip-Flop

CK

CK

D
CLK
QL
QD

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Major Constituents: Timing

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Combinational Circuits
tpd: Propagation delay
tPLH: tpd when output switches from L to H
tPHL: tpd when output switches from H to L

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Flip-Flop Timing
D

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ts: Setup time: Minimum time
input must be valid before the
active clock edge

CK

th: Hold time: Minimum time

input must be valid after the
active clock edge

CLK
D

ts

tco: Propagation delay for

input to appear at the output
from active
clock edge

th

tco
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Major Constituents: Timing

5 ns

5 ns

5 ns

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5 ns
Y

Static-0 Hazard
A
B

Static-1 Hazard
OR Gate
A: 1 0

Y
50

55

60

65

70

t ns

Model

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Timing: Static-0 Hazard Real Life

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Interconnect / Logic delay

A
Y

B
C

C: 1, B: 0

1, A: 1

Unbalanced path delay, Switching / glitches at Y

May not be problem in synchronous sequential circuits
Power dissipation
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Dynamic Hazard

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10 ns

Y 0

5 ns
Z 1

X 1

5 ns

A
X
Y
Z
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50

55

60

t ns

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Electrical Characteristics

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Voltages, Currents, Power dissipation

VOH, VOL, IOH, IOL
VIH, VIL, IIH, IIL
VOH = VDD IOH * RON
VDD
IOH

VOHmin @ IOHmax
VOL = IOL * RON

IOL

VOLmax @ IOLmax
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Electrical Characteristics

VOHmin
VIHmin

NMH

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Fanout
Min (IOHmax /IIHmax ,
IOLmax/IILmax)

VILmax
VOLmax

NML

Power Dissipation
PD = C * V2DD * f

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Low Power Design

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PD = C * V2DD * f

Transistor Level (Feature size)

Circuit Level (e.g. Balanced Path delay)
System level (Power down, Clock freeze)
Architecture
Algorithms
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High Frequency Designs

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Transmission Lines
Reflections
Cross talk
Ground loops
Back end Tools

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Device Technology

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Full Custom (ASIC)

High NRE Cost, High Volume

Large Turn around time
Custom design from scratch
Use of library cells

Semi Custom (Mask Programmable / Standard Cell)

Design in terms of standard blocks
Medium NRE Cost, Medium Volume
Medium Turn around time
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Device Technology

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Field Programmable (FPGA)

Low NRE Cost, Low-Medium Volume
Low Turn around time

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VLSI Technology

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PMOS is getting faster (hole mobility)

Strained silicon
Current Feature Size 22 nm (Intel Core i3, i5, i7)
Future Feature Size 14 nm
Inverter Delay
5-7 ps

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Design Methodology

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Front-end design
Specifications => Gate and Flip-flop Net list
Algorithm => Architecture => Circuit

Back-end design
Gate and Flip-flop Net list => Chip Masks
Circuit => Transistor Level Circuit => Chip masks
Circuit => Configuration pattern (FPGA)

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Design Methodology

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Data Path (Registers, Combinational)

Controller(s) (FSMs)
Metric, Constraints: Area, Delay, Power

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Sequential Circuits: Data Path

FF

Comb

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FF

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Controller: Finite State Machine

Next
State
Inputs

NSL

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Present
State

FF

OL

Outputs

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System on Chip / Intellectual Property

System on Board

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System on Chip

Embedded System on Chip

Reduced power dissipation
Reduced chip interconnects
Reduced device size

Programmable System on Chip

ASIC Domain

FPGA Domain
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SoC (Typical)

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One ore more processor cores

Control, Communication, DSP

Number of peripherals
Timer, I/Os, Memory controllers, UART, USB,

On-Chip Bus Architecture

Network Interfaces
Custom Hardware
Codec's, Packet processing, Signal processing etc.
Firmware
RTOS, Protocol stacks, Application software
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Intellectual Property (Digital Hardware)

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Soft IP
HDL Design

Firm IP
Synthesized Circuit

Hard IP
Place and Routed IP

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Dynamic / Runtime Reconfiguration

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FPGA / ASIC
A part of the Device is reprogrammed to implement a
different functionality
Other part may or may not be used
Saves area, power and achieve lower delay
Reconfiguration time is important
Granularity is important
Flexibility is important
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System Modeling

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Architecture Exploration, Performance Modeling, High

level Synthesis
Hardware-Software partitioning
Cost-performance trade-offs
Hardware: Concurrent, Higher performance, Higher cost
Software: Sequential, Lower performance, More flexible
SystemC
SystemVerilog: Verification
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Application Areas

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Communication Networks
Physical layer (Mixed-mode design)
Data link layer (Digital, Mostly in hardware, control in OS
Drivers)
Network layer (Processing in Hardware for Network elements
like Switches and Routers)

Signal Processing
Filters, Codecs, Compression, etc.

Computer Architecture
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