Standalone Circuit Converts Square Waves To Sine Waves

Many microcontrollers or PICs will have uncommitted digital-to-analog converter (DAC) outputs that can be used to generate
sine waves. But these are generally low resolution (8 to 10 bits), yielding a total harmonic distortion (THD) in the 1% range.
Or, using a fifth- or seventh-order switched-capacitor filter with a square-wave output ties up two I/O pins on the MCU. One
output is used for the filter input and one for the filter clock. Also, the two outputs must be square waves and track at a 100:1
ratio.
Because the MCU will have more processes to handle than just generating a sine wave, tying up two timers or one timer
and firmware usually requires too much system overhead. Therefore, the system designer is forced to use a faster or more
expensive MCU.
Here's a better approach: Use an RDD104 selectable four-decade CMOS divider and an MSFS5 switched-capacitor filter to
create a two-chip, 0.2%-distortion sine-wave source. The RDD104 has two pins that select one of four dividers: divide-by-10,
divide-by-100, divide-by-1000, and divide-by-10k. The device can be used either with an external clock on pin 5 or with a
crystal. The maximum frequency range is 1.5 MHz at 5 V dc.
The figure shows the schematic for the square-wave-to-sine-wave converter. A crystal and a 10-MO resistor are connected
across pins 5 and 6 of the RDD104. A 100-pF capacitor (C5) is tied to pin 5. The input capacitance of the MSFS5 and the
connection between pin 6 of the RDD104 and pin 4 of the MSFS5 provides equal capacitance on pin 2 of the crystal. With
DIV_SEL_1 tied low and DIV_SEL_2 tied high, the 100:1 divider is selected.
The MSFS5 is a pin-selectable, seventh-order, low-pass/six-pole bandpass switched-capacitor filter. The eight-pin IC can
set for Butterworth, Bessel, or elliptic low-pass filters; or for full, 1/3- and 1/6-octave bandpass filters. Clock_Out of the
RDD104 is ac-coupled to the Clock input of the MSFS5. The MSFS5 is set for 1/6-octave bandpass operation for maximum
attenuation of square-wave harmonics without attenuating the fundamental. Bandpass and 1/6-octave configuration is
obtained by tying FSEL and TYPE to VDD. The filter is configured for single-supply operation, with VDD at 5 V, VSS at 0 V, and
GND tied to mid-supply with two resistors (R4 and R5). A 0.1-µF capacitor decouples the input. The output of the RDD104 is
attenuated with two 10-kO resistors and ac coupled to the filter input of the MSFS5.
With this configuration, a 10-kHz, 1-V rms sine-wave output is achieved. Total current consumption is less than 2 mA at 5 V
dc, making this solution ideal for portable applications. THD is at 0.2% for a bandwidth from 400 Hz to 300 kHz (measured
with an AP Portable One Plus Access).