PROJECT REPORT

On
UART
(Universal Asynchronous Receiver Transmitter)
Submitted to

ABSTRACT
A Universal Asynchronous Receiver/Transmitter, abbreviated UART, is a piece of computer
hardware that translates data between parallel and serial forms. UARTs are commonly used in
conjunction with communication standards such as EIA, RS-232, RS-422 or RS-485.
The universal designation indicates that the data format and transmission speeds are
configurable. The electric signaling levels and methods (such as differential signaling etc.)
are handled by a driver circuit external to the UART.
A UART is usually an individual (or part of an) integrated circuit used for serial
communications over a computer or peripheral device serial port. UARTs are now commonly
included in microcontrollers. A dual UART, or DUART, combines two UARTs into a single
chip. An octal UART or OCTART combines eight UARTs into one package, an example
being the NXP SCC2698. Many modern ICs now come with a UART that can also
communicate
synchronously;
these
devices
are
called USARTs (universal
synchronous/asynchronous receiver/transmitter).
We started off with exploring UART and various ICs that use this technology. After going
through many forums, websites and reference data sheets, we made this project on UART.
UART has its successors as: USART & EUSART. After referring many codes we tried and
tested it in our lab, made modifications and finally concluded our code on HDL designer and
ModelSim and generated the waveforms which we will hereby describe.

Topics

Content
UART and Structure
Transmitting and Receiving Serial Data
Final VHDL Code
Waveforms (step-wise)
Codes Referred

Page
3
4-6
7-12
13-23
24-34

About UART
A Universal Asynchronous Receiver/Transmitter, abbreviated UART, is a piece
of computer hardware that translates data between parallel and serial forms. UARTs are
commonly used in conjunction with communication standards such as EIA, RS-232, RS422 or RS-485. The universal designation indicates that the data format and transmission
speeds are configurable. The electric signalling levels and methods (such as differential
signalling etc.) are handled by a driver circuit external to the UART.
A UART is usually an individual (or part of an) integrated circuit used for serial
communications over a computer or peripheral device serial port. UARTs are now commonly
included in microcontrollers. A dual UART, or DUART, combines two UARTs into a single
chip. An octal UART or OCTART combines eight UARTs into one package, an example
being the NXP SCC2698. Many modern ICs now come with a UART that can also
communicate
synchronously;
these
devices
are
called USARTs (universal
synchronous/asynchronous receiver/transmitter).

Structure
A UART usually contains the following components:

a clock generator, usually a multiple of the bit rate to allow sampling in the middle of
a bit period.

input and output shift registers

transmit/receive control

read/write control logic

transmit/receive buffers (optional)

parallel data bus buffer (optional)

First-in, first-out (FIFO) buffer memory (optional)

Transmitting and Receiving serial data

The Universal Asynchronous Receiver/Transmitter (UART) takes bytes of data and transmits
the individual bits in a sequential fashion. At the destination, a second UART re-assembles
the bits into complete bytes. Each UART contains a shift register, which is the fundamental
method of conversion between serial and parallel forms. Serial transmission of digital
information (bits) through a single wire or other medium is less costly than parallel
transmission through multiple wires.
The UART usually does not directly generate or receive the external signals used between
different items of equipment. Separate interface devices are used to convert the logic
level signals of the UART to and from the external signalling levels. External signals may be
of many different forms. Examples of standards for voltage signalling are RS-232, RS422 and RS-485 from the EIA. Historically, current (in current loops) was used in telegraph
circuits. Some signalling schemes do not use electrical wires. Examples of such are optical
fibre, IrDA (infrared), and (wireless) Bluetooth in its Serial Port Profile (SPP). Some
signalling schemes use modulation of a carrier signal (with or without wires). Examples are
modulation of audio signals with phone line modems, RF modulation with data radios, and
the DC-LIN for power line communication.
Communication may be simplex (in one direction only, with no provision for the receiving
device to send information back to the transmitting device), full duplex (both devices send
and receive at the same time) or half duplex (devices take turns transmitting and receiving).

Character framing
The right-most (least significant) data bit is always transmitted first. If parity is present, the
parity bit comes after the data bits but before the stop bit(s).
Bit
1
number

10

Start
bit

58 data bits

Start

Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Stop

11 (Not
Used)

Stop bit(s)

The idle, no data state is high-voltage, or powered. This is a historic legacy from telegraphy,
in which the line is held high to show that the line and transmitter are not damaged. Each
character is sent as a logic low start bit, a configurable number of data bits (usually 8, but
users can choose 5 to 8 or 9 bits depending on which UART is in use), an optional parity bit if
the number of bits per character chosen is not 9 bits, and one or more logic high stop bits.
The start bit signals the receiver that a new character is coming. The next five to nine bits,
depending on the code set employed, represent the character. If a parity bit is used, it would
be placed after all of the data bits. The next one or two bits are always in the mark (logic
high, i.e., '1') condition and called the stop bit(s). They signal the receiver that the character is
completed. Since the start bit is logic low (0) and the stop bit is logic high (1) there are
always at least two guaranteed signal changes between characters.
4

If the line is held in the logic low condition for longer than a character time, this is a break
condition that can be detected by the UART.

Transmitter
Transmission operation is simpler since it is under the control of the transmitting system. As
soon as data is deposited in the shift register after completion of the previous character, the
UART hardware generates a start bit, shifts the required number of data bits out to the line,
generates and appends the parity bit (if used), and appends the stop bits. Since transmission
of a single character may take a long time relative to CPU speeds, the UART will maintain a
flag showing busy status so that the host system does not deposit a new character for
transmission until the previous one has been completed; this may also be done with an
interrupt. Since full-duplex operation requires characters to be sent and received at the same
time, UARTs use two different shift registers for transmitted characters and received
characters.

Receiver
All operations of the UART hardware are controlled by a clock signal which runs at a
multiple of the data rate, typically 8 times the bit rate. The receiver tests the state of the
incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent
start bit lasts at least one-half of the bit time, it is valid and signals the start of a new
character. If not, it is considered a spurious pulse and is ignored. After waiting a further bit
time, the state of the line is again sampled and the resulting level clocked into a shift register.
After the required number of bit periods for the character length (5 to 8 bits, typically) have
elapsed, the contents of the shift register are made available (in parallel fashion) to the
receiving system. The UART will set a flag indicating new data is available, and may also
generate a processor interrupt to request that the host processor transfers the received data.
Communicating UARTs usually have no shared timing system apart from the communication
signal. Typically, UARTs resynchronize their internal clocks on each change of the data line
that is not considered a spurious pulse. Obtaining timing information in this manner, they
reliably receive when the transmitter is sending at a slightly different speed than it should.
Simplistic UARTs do not do this, instead they resynchronize on the falling edge of the start
bit only, and then read the centre of each expected data bit, and this system works if the
broadcast data rate is accurate enough to allow the stop bits to be sampled reliably.
It is a standard feature for a UART to store the most recent character while receiving the next.
This "double buffering" gives a receiving computer an entire character transmission time to
fetch a received character. Many UARTs have a small first-in, first-out FIFO buffer memory
between the receiver shift register and the host system interface. This allows the host
processor even more time to handle an interrupt from the UART and prevents loss of received
data at high rates.

Special receiver conditions

5

Overrun error
An "overrun error" occurs when the receiver cannot process the character that just came in
before the next one arrives. Various devices have different amounts of buffer space to hold
received characters. The CPU must service the UART in order to remove characters from the
input buffer. If the CPU does not service the UART quickly enough and the buffer becomes
full, an Overrun Error will occur, and incoming characters will be lost.

Under run error

An "under run error" occurs when the UART transmitter has completed sending a character
and the transmit buffer is empty. In asynchronous modes this is treated as an indication that
no data remains to be transmitted, rather than an error, since additional stop bits can be
appended. This error indication is commonly found in USARTs, since an under run is more
serious in synchronous systems.

Framing error
A "framing error" occurs when the designated "start" and "stop" bits are not found. As the
"start" bit is used to identify the beginning of an incoming character, it acts as a reference for
the remaining bits. If the data line is not in the expected state (hi/lo) when the "stop" bit is
expected, a Framing Error will occur.

Parity error
A Parity Error occurs when the parity of the number of 1 bits disagrees with that specified by
the parity bit. Use of a parity bit is optional, so this error will only occur if parity-checking
has been enabled.

Break condition
A "break condition" occurs when the receiver input is at the "space" level for longer than
some duration of time, typically, for more than a character time. This is not necessarily an
error, but appears to the receiver as a character of all zero bits with a framing error.
Some equipment will deliberately transmit the "break" level for longer than a character as
an out-of-band signal. When signalling rates are mismatched, no meaningful characters can
6

be sent, but a long "break" signal can be a useful way to get the attention of a mismatched
receiver to do something (such as resetting itself). Unix-like systems can use the long "break"
level as a request to change the signalling rate, to support dial-in access at multiple signalling
rates.

Final VHDL Code

--- VHDL Architecture Sushant_Mongia_Project1_lib.uart.rtl
--- Created:
--

By - SUSHANT MONGIA.UNKNOWN (SUSHANT)

--

at - 23:28:23 10/13/2013

--- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)

--------------------------------------------------------- Design Name : uart
-- File Name : uart.vhd
-- Function
-- Coder

: Simple UART
: SUSHANT MONGIA

------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity uart is
port (
reset

:in std_logic;

txclk

:in std_logic;

ld_tx_data :in std_logic;

tx_data

:in std_logic_vector (7 downto 0);

tx_enable :in std_logic;

tx_out

:out std_logic;
8

tx_empty
rxclk

:out std_logic;

:in std_logic;

uld_rx_data :in std_logic;

rx_data

:out std_logic_vector (7 downto 0);

rx_enable :in std_logic;

rx_in

:in std_logic;

rx_empty

:out std_logic

);
end entity;
architecture rtl of uart is
-- Internal Variables
signal tx_reg

:std_logic_vector (7 downto 0);

signal tx_over_run

:std_logic;

signal tx_cnt

:std_logic_vector (3 downto 0);

signal rx_reg

:std_logic_vector (7 downto 0);

signal rx_sample_cnt :std_logic_vector (3 downto 0);

signal rx_cnt

:std_logic_vector (3 downto 0);

signal rx_frame_err :std_logic;

signal rx_over_run

:std_logic;

signal rx_d1

:std_logic;

signal rx_d2

:std_logic;

signal rx_busy

:std_logic;

signal rx_is_empty

:std_logic;

signal tx_is_empty

:std_logic;

begin
-- UART RX Logic
process (rxclk, reset) begin
if (reset = '1') then

rx_reg

<= (others=>'0');

rx_data

<= (others=>'0');

rx_sample_cnt <= (others=>'0');

rx_cnt

<= (others=>'0');

rx_frame_err <= '0';

rx_over_run <= '0';
rx_is_empty <= '1';
rx_d1

<= '1';

rx_d2

<= '1';

rx_busy

<= '0';

elsif (rising_edge(rxclk)) then

-- Synchronize the asynch signal
rx_d1 <= rx_in;
rx_d2 <= rx_d1;
-- Uload the rx data
if (uld_rx_data = '1') then
rx_data <= rx_reg;
rx_is_empty <= '1';
end if;
-- Receive data only when rx is enabled
if (rx_enable = '1') then
-- Check if just received start of frame
if (rx_busy = '0' and rx_d2 = '0') then
rx_busy

<= '1';

rx_sample_cnt <= X"1";

rx_cnt

<= X"0";

end if;
-- Start of frame detected, Proceed with rest of data

10

if (rx_busy = '1') then

rx_sample_cnt <= rx_sample_cnt + 1;
-- Logic to sample at middle of data
if (rx_sample_cnt = 7) then
if ((rx_d2 = '1') and (rx_cnt = 0)) then
rx_busy <= '0';
else
rx_cnt <= rx_cnt + 1;
-- Start storing the rx data
if (rx_cnt > 0 and rx_cnt < 9) then
rx_reg(conv_integer(rx_cnt) - 1) <= rx_d2;
end if;
if (rx_cnt = 9) then
rx_busy <= '0';
-- Check if End of frame received correctly
if (rx_d2 = '0') then
rx_frame_err <= '1';
else
rx_is_empty <= '0';
rx_frame_err <= '0';
-- Check if last rx data was not unloaded,
if (rx_is_empty = '1') then
rx_over_run <= '0';
else
rx_over_run <= '1';
end if;
end if;
end if;

11

end if;
end if;
end if;
end if;
if (rx_enable = '0') then
rx_busy <= '0';
end if;
end if;
end process;
rx_empty <= rx_is_empty;
-- UART TX Logic
process (txclk, reset) begin
if (reset = '1') then
tx_reg

<= (others=>'0');

tx_is_empty <= '1';

tx_over_run <= '0';
tx_out

<= '1';

tx_cnt

<= (others=>'0');

elsif (rising_edge(txclk)) then

if (ld_tx_data = '1') then
if (tx_is_empty = '0') then
tx_over_run <= '0';
else
tx_reg <= tx_data;
tx_is_empty <= '0';
end if;
end if;
if (tx_enable = '1' and tx_is_empty = '0') then

12

tx_cnt <= tx_cnt + 1;

if (tx_cnt = 0) then
tx_out <= '0';
end if;
if (tx_cnt > 0 and tx_cnt < 9) then
tx_out <= tx_reg(conv_integer(tx_cnt) -1);
end if;
if (tx_cnt = 9) then
tx_out <= '1';
tx_cnt <= X"0";
tx_is_empty <= '1';
end if;
end if;
if (tx_enable = '0') then
tx_cnt <= X"0";
end if;
end if;
end process;
tx_empty <= tx_is_empty;
end architecture;

Waveforms (step-wise)

13

14

15

16

17

18

19

20

21

22

23

Codes Referred
--- VHDL Architecture Sushant_Mongia_Project1_lib.UART1.BHV
--- Created:
--

by - SUSHANT MONGIA.UNKNOWN (SUSHANT)

--

at - 22:23:07 10/ 6/2013

--- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)

---**************************************************************************
-------------------------------------------------------- Design Name : UART
24

-- File Name : UART.vhd

-- Function
-- Coder

: UART
: SUSHANT MONGIA

-------------------------------------------------------

--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity UART1 is
port(rst : in STD_LOGIC;
clk : in STD_LOGIC;
uartclk : in STD_LOGIC;
memadl : in STD_LOGIC_VECTOR (7 downto 0);
memadh : in STD_LOGIC_VECTOR (7 downto 0);
upp0 : inout STD_LOGIC_VECTOR (7 downto 0);
upwr : in STD_LOGIC;
uprd : in STD_LOGIC;
trx : out STD_LOGIC);
end UART1;

--**************************************************************************--

25

architecture BHV of UART1 is

constant CZ_8 : STD_LOGIC_VECTOR (7 downto 0) := "ZZZZZZZZ";

constant C1_8 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";

-- uart state type

type STATE_TYPE is (IDLE, START_BIT, STOP_BIT, BIT0, BIT1, BIT2,
BIT3, BIT4, BIT5, BIT6, BIT7);

-- uart data and ack addresses

constant REGS_ADDRH : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant REG1_ADDRL : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant REG2_ADDRL : STD_LOGIC_VECTOR (7 downto 0) := "00000001";

-- signals for communication between the cpu write and uart transmit process
signal uart_ack : STD_LOGIC;
signal uart_en : STD_LOGIC;
signal uart_data : STD_LOGIC_VECTOR(7 downto 0);

-- signals used in the uart transmit process

signal state : STATE_TYPE;

begin
--- cpu read/write
-process(rst, clk)

26

begin
if( rst = '0' ) then
uart_en <= '0';
uart_data <= "00000000";
upp0 <= C1_8;
elsif( clk'event and clk = '1' ) then
upp0 <= CZ_8;

-- ????

if( upwr = '0' ) then

if( memadh = REGS_ADDRH and memadl = REG1_ADDRL ) then
-- ????
end if;
elsif( uprd = '0' ) then
if( memadh = REGS_ADDRH and memadl = REG2_ADDRL )
then
-- ????
end if;
end if;
end if;
end process;

--- UART serial transmit process

-process(rst, uartclk)
begin
if( rst = '0' ) then
27

uart_ack <= '1';

trx <= '1';
state <= IDLE;
---

elsif( uartclk'event and uartclk = '1' ) then

case state is
-- ????
-- end case;
end if;

end process;

end BHV;

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