ISBN: 978-15-076833-85

Proceedings of International Conference on Recent Innovations in Engineering & Technology

Date: 24.1.2015

GLITCH-FREE NAND-BASED DIGITALLY CONTROLLEDDELAY-LINES

P RAKESH, K. Dhanunjaya
Email: potluru.rakesh@gmail.com, hod.ece@audisankara.com
AUDISHANKARA COLLEGE OF ENGINEERING AND TECHNOLOGY GUDUR

India. Email: hod.ece@audisankara.com

Abstract: The recently proposed NAND-based digitally controlled delay-lines (DCDL) present a glitching problem which may limit their
employ in many applications. This paper presents a glitch-free NAND-based DCDL which overcame this limitation by opening the employ
of NAND-based DCDLs in a wide range of applications. The proposed NAND-based DCDL maintains the same resolution and minimum
delay of previously proposed NAND-based DCDL. The theoretical demonstration of the glitch-free operation of proposed DCDL is also
derived in the paper. Following this analysis, three driving circuits for the delay control-bits are also proposed. Proposed DCDLs have been
designed in a 90-nm CMOS technology and compared, in this technology, to the state-of-the-art. Simulation results show that novel circuits
result in the lowest resolution, with a little worsening of the minimum delay with respect to the previously proposed DCDL with the lowest
delay. Simulations also confirm the correctness of developed glitching model and sizing strategy. As example application, proposed DCDL is
used to realize an All-digital spread-spectrum clock generator (SSCG). The employ of proposed DCDL in this circuit allows to reduce the
peak-to-peak absolute output jitter of more than the 40% with respect to a SSCG using three-state inverter based DCDLs.
Index Terms: All-digital delay-locked loop (ADDLL), all-digital phase-locked loop (ADPLL), delay-line, digitally controlled oscillator
(DCO), flip-flops, sense amplifier, spread-spectrum clock generator (SSCG)
I. INTRODUCTION
The steady improvement of components for digital signal processing applications, more applications pertaining to processing signals are
experiencing a shift from the analog to the digital domain. The digital domain compared to the analog domain provide manifold benefits like
easy calibration, higher accuracy, better predictability and the probability to increase the complexity without the need for tedious adjustments
or calibrations. Thus the digital domain certainly provides a better edge over analog domain which attracts more research and
experimentation in this field of study. Due to high integration of very-large-scale integration (VLSI) systems, PLLs often operate in a very
noisy environment. The digital switching noise coupled through power supply and substrate induces considerable noise into noise-sensitive
analog circuits. Many analog approaches are proposed to improve the jitter performance of PLLs, such as choosing a narrow bandwidth or
using a low-gain voltage-controlled oscillator (VCO). Synthesizers for mobile applications are fractional N-based PLLs. However, those
analog approaches often result in long lock-in time and increasing design complexity of the PLLs. The associated fractional spurs must be
suppressed, which requires large RC filters and precise loop-gain control when traditional analog techniques are applied. Rapid scaling of
CMOS technology enables all-digital PLLs (ADPLLs) implementation. Digital loop filters replace area-consuming RC filters, and the loop
gain can be calibrated digitally. However, nonlinear switching and digital transient noise degrade the spur performance. The frequency
synthesizer is a key block used for both up-conversion and down-conversion of radio signals and has been traditionally based on a chargepump PLL, which is not easily amenable to integration. Recently, a digitally controlled oscillator (DCO), which deliberately avoids any
analog tuning voltage controls, was first ever presented for RF wireless applications. This allows for its loop control circuitry to be
implemented in a fully digital manner as first proposed and then demonstrated as a novel digital-synchronous phase-domain all-digital PLL
(ADPLL) in a commercial 0.13m CMOS single-chip Bluetooth radio. The phase-locked loop (PLL) has various applications infrequency
synthesis, digital modulation, and synchronization. The PLL can be implemented with analog/mixed signal circuits, or all-digital circuits. The
analog/mixed signal PLL can supply high-frequency outputs, but its performance highly depends on the pressure-voltage temperature
manufacture conditions. In addition, the phase noise of an analog/mixed-signal PLL may is difficult to control. In contrast to the
analog/mixed-signal PLL, the all digital PLL (ADPLL) can be realized with a digital VLSI process, and its performance is easier to control.
Moreover, the ADPLL can be easily integrated with a digital circuit system that is useful for many applications such as the base band
communications or electronic equipments.
Recently, all-digital phase-locked loops (ADPLLs) have become more attractive because they yield better testability, programmability,
stability, and portability over different processes, and they can reduce the system turnaround time. The need for an Field Programmable Gate
Array (FPGA) based All Digital Phase locked loop (ADPLL) was required basically because the microprocessors do not have enough
processing power at such high frequencies even though with integrated analog to digital converters (ADCs) and digital to analog converters
(DACs). Thus the system becomes redundant in this case. The design of an application specific integrated circuit (ASIC) is not suitable for
this purpose because the quantity involves is less and thus the fabrication process would be very expensive. The FPGA is an ideal solution to
the problem because it combines the speed and computational power of ASICs as well as the flexibility of microprocessors. Thus an FPGA
based ADPLL is needed.
One of the key components in the design of an ADPLL system is the phase detector. In the present scenario most VLSI implementation
uses the phase frequency detectors (PFDs). The design of the ADPLL must intend to have a phase detection system with higher phase
accuracy for minimum phase error. The design should also have easy programmability and calibration along with reduced complexity of the
circuit. The project is based on the basis of being the ADPLL being FPGA realizable. Thus the logic for the ADPLL used should be
transferable to FPGA logic and the design of the ADPLL should be hardware implementable. The main aim of the project is to design and
implement ADPLL on FPGA with reducing delay with desired frequency 62.5MHZ.

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Proceedings of International Conference on Recent Innovations in Engineering & Technology

Date: 24.1.2015

II. ALL DIGITAL PHASE LOCKED LOOP

The basic aim of this paper is to avoid glitches present in the circuit which is constructed using universal gate. Power is also analyzed to
maintain low power consumption. Many methods are used to remove glitches present in the circuit. Delay has been reduced by using delay
cell in each element of circuit and power consumption also reduced by micro wind technology. Presence of glitch may cause unwanted
transition in the circuit result. Jitter also because undesirable deviation of periodic signal it may also results glitches in the circuit. Jitter may
be caused by interference of the signal and crosstalk with carriers of other signals. Digital to analog converters or analog to digital converters
used and time between samples varies. Time resolution of digital signal is higher than the voltage resolution of analog signal. Digitally
controlled delay technique plays a role in analog to digital converters in circuit. In each element of circuit delay cell is constructed to reduce
the output delay. A delay element is discrete element which allows signal to be delayed number of samples. Power consumption of both
NAND and NOR circuit is analyzed and it is less existing NAND based circuit. Minimizing the delay of circuit depends on the number of
delay. Output capacitance and drivability of delay elements are the key parameters for designing low jitter delay elements. Each circuit can
be constructed using NAND and NOR gate maintain same resolution with minimum delay produced. Delay element constructed using
regular cascade of cells. It has simple layout organization with low nonlinearity effects. Hence removal of glitch in circuit and low power
consumption of universal circuit has proposed.
A. A Portable Digitally Controlled Oscillator Using Novel Varactor.
A portable digitally controlled oscillator by two input NOR gate as a digitally controlled varactor in fine tuning delay cell design. It uses
gate capacitance under different digital control inputs with delay resolution 256 times better than single resolution time. Phase locked loop
used in many communication systems to clock and data recovery or frequency synthesis. To process high resolution digitally controlled
oscillator by using NAND /NOR gate as novel varactor. Resolution is non-uniform and sensitive to power supply variation. It has high
portability and short design turnaround cycle and also has small size of varactor. The driving strength can be changed by using capacitance
loading.
B. Low Cost Variable Delay Line for Impulse Radio Ultra Wide Band Architecture
It introduces delay line circuit suitable for impulse radio ultra wideband architecture. Fine synchronization used to be related to relative
high cost devices. Low power architecture has been tested by commercial off the shelf breadboard. This achieves good performance and
delay step in nanosecond range. Its band width is greater than 0.25MHz which is more than radiated spectrum. Additional circuit is needed to
perform full clock cycle. Reference voltage can be adjusted with digital to analog converter. High data rate and low power system of wireless
networking developed by using local area networking. This technique is based on broadcasting of very low power signals. Simple hardware
is added to reduce latency. Delay is up to 40% of pulse width. Incoming signal delay depends on threshold voltage. Design is simple and fast
circuit implementation.
C. All Digital Phase Locked Loop for High Speed Clock Generator
It uses both a digital control mechanism and ring oscillator can be implemented with standard cells. Power dissipation is about 100mW
with 3.3 power supply. Phase locked loop is widely used for frequency synthesis application. Jitter is less than 4% of clock cycle and also it
avoid functional failure of the system. Adaptive algorithm can be used to achieve fast lock in time. It yield better testability, programmability,
stability and portability over difficult process and reduces turnaround time. Loop filter detects the maximum and minimum control code.
Resolution improved about 5ps by adding fine tuning delay cell. It has fine tuning range. Controllable range of fine tuning delay cell should
cover coarse tuning. Control code has small variation due to input jitter. Fast locking achieves 41 refresh cycles has better portability. It is
suitable for on chip application. Pulse amplifier effectively minimize dead zone of the signal.
D. A Anti Reset all Digital Delay Locked Loop
Input clock frequency changes significantly, the dynamic frequency detector relocks digital locked loop without any external reset
signal. Binary time to digital converter used to reduce the hardware requirement. It takes six cycles to synchronize input and output signals. It
used to de skew buffer and clock generator and also achieves low cost, wide operating frequency, low jitter and low power consumption. It
has short lock time, easy migration with poor jitter performance. Process sensitive characteristics make them difficult to migrate in advanced
technology. The residual phase error can be corrected by phase detector and counter. However it increases lock time. Power consumption is
about 10mW. Peak to peak jitter is about 11.78ps. Internal reset is active to relock pulse. Delay is closed to half period of input clock,
residual phase error between input and output is small. In existing method glitch is removed by using NAND gate and delay is reduced in
digital manner. Power consumption is more. In proposed system universal gate is used for low power consumption of circuit.
E. Removal of Glitch in circuit
Glitching problem will occur when the control code of circuit struck at some values and it gives error values at the output. Glitching
problem can be solved by raising the control values of the cells in each element of the circuit.

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Proceedings of International Conference on Recent Innovations in Engineering & Technology

Date: 24.1.2015

Fig.1. Inverting Glitch Free Circuit of NAND Gate

The circuit eliminates the presence of glitches by using dummy cells in each element of circuit. Control bits can in one of the three
possible states. In pass state the circuit with universal gate of third element gives output 1 and fourth element makes the signal propagate to
low level of gates in the circuit. In this figure all the NAND gates present same load and gives same delay.
Delay is given by
= 2t
Where t

+ 2t
= (t

.C
LH + t

HL)/2

While tnand LH and tnand HL represent the delay of each NAND gate for low to high and high to low output commutation respectively.
When delay cell is passed to output of third element of gate it becomes post turn state and all other state become turn state. Signal propagates
from input to output of the circuit through gates. Dummy cells are used to maintain load balancing in the circuit. The NAND gate is used to
reduce the hardware of circuit. Any gate can be constructed with help of NAND gate. It is very useful for construction of digital circuits.

Fig.2. Non Inverting Glitch Free Circuit of NAND Gate.

In many applications output glitching can be avoided by synchronizing both input and output values minimizing the arrival time of
control bit values than input values to reduce the delay time of each element.
F. Power Analyses for Circuit using NAND gate:
Table 1
Power analyses for NAND gate Circuit

Power consumption for the circuit constructed using NAND gate is reduced than existing method with help of 45nm technology.
Performance of circuit is also maintained same by removing the glitches and results obtained for both circuit. In 45nm technology leakage
current is reduced. It has higher density and higher switching performance. Power consumption of NAND gate is than the power
consumption of circuit with combination of AND and INVERTER gates.
III. IMPLEMENTATION OF CIRCUIT USING NOR GATE
Circuit is also neither implemented using NOR gate to reduce the power consumption of the circuit. Power consumption of NOR gate is
less than the power consumption of NAND gate and it increases the speed of operation of given circuit. Implementation of circuit using
universal gate reduce hardware its required delay is the length of time it takes for a signal to travel to its destination. Digital circuits and
digital electronics, the propagation delay, or gate delay, is the length of time which starts when the input to a logic gate becomes stable and
valid, to the time that the output of that logic gate is stable and valid. In gate delay transistors within a gate take a finite time to switch. This
means that a change on the input of a gate takes a finite time to cause a change on the output. Reducing gate delays in digital circuits allows
them to process data at a faster rate and improve overall performance. The difference in propagation delays of logic elements is the major
contributor to glitches in asynchronous circuits as a result of race conditions. The principle of logical effort utilizes propagation delays to
compare2015:
designs
implementing
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Date: 24.1.2015

Propagation delay increases with operating temperature, marginal supply voltage as well as an increased output load capacitance. The
latter is the largest contributor to the increase of propagation delay. If the output of a logic gate is connected to a long trace or used to drive
many other gates (high fan-out) the propagation delay increases substantially. Logic gates can have propagation delays ranging from more
than 10 ns down to the Pico second range, depending on the technology being used. In the case of an electric signal, it is the time taken for
the signal to travel through a wire. There are other different types of delay also source delay, network delay, insertion delay, transition delay,
path delay, intrinsic delay, phase delay. A digital delay line is a discrete element in digital filter theory, which allows a signal to be delayed
by a number of samples. If the delay is an integer multiple of samples digital delay lines are often implemented as circular buffers. This
means that integer delays can be computed very efficiently. Digital delay lines are widely used building blocks in methods to simulate room
acoustics, musical instruments and digital audio effects. The DCDL are designed glitch free and it is implemented in the application for the
better performance. A necessary condition to avoid glitching is designing a DCDL which have no-glitch in presence of a delay control-code
switching. This is a major issue at the DCDL-design level. This project carries out with the glitch free NAND based delay elements which
have good resolution so that the better performances can be obtained in the digital applications. Application used in this project was delay
locked loop(DLL).This paper contribute to the glitch free DCDL with the driving circuits for the delay control bits of the glitch free DCDL
implemented in the delay locked loop(DLL).
The following figure shows the block diagram of the existing NAND based DCDL. It consists of a NAND based lattice delay units which
is cascaded for larger delay lines in application

Fig.3. Block diagram of the conventional DCDL with one control bit
This conventional DCDL was designed with NAND cell as lattice structure .In the Fig.3 the cell which is denoted by A is the fast
input of the NAND gate. Gates denoted by D is the dummy cell for the load balancing. These delay elements are controlled by one bit
control code c to propagate the delay. When the delay control code C increased by 1, multiple propagation path within the DCDL structure
generates leads to more glitching in the delay line. The control bit Si = 0 (pass state), Si = 1 (turn state). In DCDL applications, to avoid
DCDL output glitching, the switching of delay control-bits is synchronized with the switching of the input signal. Glitching is avoided if the
control bits arrival time is lower than the arrival time of the input signal of the first DE which switches from or to the turn-state.
The structure proposed in this Fig.4 has control bits to control the delay elements .In thatAdenotes the fast input of the NAND gate,
D denotes the dummy cell for the load balancing. Two control bits Ti and Si are used to synchronize the arrival of the input and the arrival
of the control bits. It has three possible states.

Fig.4. Block diagram of the Glitch free DCDL with two control bit
Table 2
Logic states of each DE in proposed DCDLs

The DEs i<c with are in pass-state (Si =0, Ti =1). In this state the NAND 3 output is equal to 1 and the NAND 4 allows the signal
propagation in the lower NAND gates chain. The DE with i=c is in turn-state (Si=Ti=0). In this state the upper input of the DE is passed to
the output of NAND 3. The next DE (i=C+1) is in post-turn-state .In this DE the output of the NAND 4 is stuck-at 1, by allowing the
propagation, in the previous DE (which is in turn-state), of the output of NAND 3 through NAND 4. All remaining DEs (for i>C+1)
are again in turn-state .The three possible DE states of proposed DCDL and the corresponding Si and Ti values are summarized in Table 2.
The simulation results shows that the proposed NAND based DCDL confirms the glitch free propagation in the delay elements.

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Proceedings of International Conference on Recent Innovations in Engineering & Technology

Date: 24.1.2015

IV. RESULTS
Conventional DCDL

Fig.5. Block diagram of the conventional DCDL with one control

In the Fig.5 the cell which is denoted by A is the fast input of the NAND gate. Gates denoted by D is the dummy cell for the load
balancing. These delay elements are controlled by one bit control code c to propagate the delay. When the delay control code C increased by
1, multiple propagation path within the DCDL structure generates leads to more glitching in the delay line. The control bit Si = 0 (pass state),
Si = 1 (turn state). In DCDL applications, to avoid DCDL output glitching, the switching of delay control-bits is synchronized with the
switching of the input signal. Glitching is avoided if the control bits arrival time is lower than the arrival time of the input signal of the first
DE which switches from or to the turn-state.

Conventional DCDL in reduced blocks

Fig.6. Block diagram of the Glitch free DCDL with two control bit
The above Fig.6 the DEs i<c with are in pass-state (Si =0, Ti =1). In this state the NAND 3 output is equal to 1 and the NAND 4 allows
the signal propagation in the lower NAND gates chain. The DE with i=c is in turn-state (Si=Ti=0). In this state the upper input of the DE is
passed to the output of NAND 3. The next DE (i=C+1) is in post-turn-state .In this DE the output of the NAND 4 is stuck-at 1, by allowing
the propagation, in the previous DE (which is in turn-state), of the output of NAND 3 through NAND 4. All remaining DEs (for i>C+1) are
again in turn-state .The three possible DE states of proposed DCDL and the corresponding Si and Ti values are summarized in Table I. The
simulation results shows that the proposed NAND based DCDL confirms the glitch free propagation in the delay elements.

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Proceedings of International Conference on Recent Innovations in Engineering & Technology

Date: 24.1.2015

Proposed

Fig.7. Non Inverting Glitch Free Circuit of NAND Gate.

In above Fig.7 non inverting DCDL .as many applications output glitching can be avoided by synchronizing both input and output values.
Minimizing the arrival time of control bit values than input values to reduce the delay time of each element

Proposed with reduced area

Fig.8. a non-inverting DCDL by modifying only the first DE

In this circuit the NAND gates 1 and 2 of the first DE have been deleted, together with signal. The signal of the second DE is now
equal to in; therefore the whole behavior of the DCDL is non-inverting

V. CONCLUSION AND FUTURE SCOPE

The glitch free DCDL is implemented in the ADDLL circuit. Glitches in the delay units are avoided by the above discussed timing
constraints of the control code. Arrival of the input control code is designed as that the propagation of the signal through the gates does not
produce glitches. Driving circuits for the control codes are also designed that the difference in the driving control bits are designed with the
proper timing constraint and delay. The implemented ADDLL is registering based DLL. The glitch free DCDL is implemented in the
ADDLL circuit. Glitches in the delay units are avoided by the above discussed timing constraints of the control code. Arrival of the input
control code is designed as that the propagation of the signal through the gates does not produce glitches. Driving circuits for the control
codes are also designed that the difference in the driving control bits are designed with the proper timing constraint and delay. Thus with this
the NAND based delay line is implemented with glitches and without glitches for the comparison of the output. Thus with this the glitches
can be well studied and analyzed for the better delay circuits.

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Date: 24.1.2015

Future scope
Circuit is can also be neither implemented using NOR gate to reduce the power consumption of the circuit. Power consumption of NOR
gate is less than the power consumption of NAND gate and it increases the speed of operation of given circuit. Implementation of circuit
using universal gate reduce hardware its requirement.
VI. REFERENCES
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[3] R. B. Staszewski and P. T. Balsara, All Digital Frequency Synthesizer in Deep Submicron CMOS. New York: Wiley, 2006.
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[6] P. L. Chen, C. C. Chung, J. N. Yang, and C. Y. Lee, A clock generator with cascaded dynamic frequency counting loops for wide
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[7] B. M. Moon, Y. J. Park, and D. K. Jeong, Monotonic wide-range digitally controlled oscillator compensated for supply voltage
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[8] J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65
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[9] K. H. Choi, J. B. Shin, J. Y. Sim, and H. J. Park, An interpolating digitally controlled oscillator for a wide range all digital
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