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http://electroiq.

com/blog/2006/07/soc-vs-mcm-vs-sip-vs-sop/
Challenges and tradeoffs of SOC vs SIP (Challenges and Trade-offs of SOC vs SIP
SESSION 5)
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1358735
Past present and future
Timeline: http://www.computerhistory.org/semiconductor/timeline.html
http://www.mckinsey.com/~/media/mckinsey/dotcom/client_service/Semiconductors/
Issue%204%20Autumn%202014/PDFs/MoSC2014_Advancedpackaging_technologies_The_implications_for_first_movers_and_fast_followers.ashx
Process flow SIP
https://www.ll.mit.edu/mission/electronics/qiin/cmos-technology/3d-integration-ofCMOS.html
SOP paper
(2004 Electronic Components and Technology Conference)
http://users.ece.gatech.edu/~etentze/ECTC2004_Sundaram.pdf
System-on-a-Package (SOP) Substrate and Module with Digital, RF and Optical
Integration Venky Sundaram*, Rao Tummala, George White, Kyutae Lim, Lixi Wan,
Daniel Guidotti, Fuhan Liu, Swapan Bhattacharya, Raj M. Pulugurtha, Isaac Robin
Abothu, Ravi Doraiswami, Raghuram V. Pucha, Joy Laskar, Manos Tentzeris, G. K.
Chang, Madhavan Swaminathan Packaging Research Center, Georgia Institute of
Technology * vsunda@ece.gatech.edu, 404-894-9394, 404-894-3842 (Fax)

Packaging types images


http://web.ece.ucdavis.edu/~bbaas/116/notes/Handout.packaging.pdf
Presentation by Dr Jones FIU
http://web.eng.fiu.edu/~jonesweb/EML%204561-%20spring%2010/EML%204561-PackagingOverview-Electrical.pptx
web.eng.fiu.edu

System in Package trends


http://www.springer.com/cda/content/document/cda_downloaddocument/9783642285219-c2.pdf?SGWID=0-0-451338322-p174307159

TSV Manufacturing Yield and Hidden Costs for 3D IC Integration


http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5490828
978-1-4244-6412-8/10/$26.00 2010 IEEE
2010 Electronic Components and Technology Conference

New start
COGNETTI, C. The impact of semiconductor packaging technologies on system integration an overview.
2009 Proceedings of the European Solid State Device Research Conference. 24, Jan. 2009. ISSN:
9781424443512.
TUMMALA, R. Packaging: past, present and future. 2005 6th International Conference on Electronic
Packaging Technology. 3, Jan. 2005. ISSN: 9780780394490
PR, Newswire. "System in Package (SiP) Market worth $18.10 Billion by 2020." PR Newswire US 30 Apr.
2014: Regional Business News. Web.
7. JONES, RE; et al. Fabrication and Modeling of Gigahertz Photodetectors in Heteroepitaxial Ge-on-Si
Using a Graded Buffer Layer Deposited by Low Energy Plasma Enhanced CVD. INTERNATIONAL
ELECTRON DEVICES MEETING. 793-796, 2002. ISSN: 01631918.
9. Liao, W. S., et al. "3D IC heterogeneous integration of GPS RF receiver, baseband, and DRAM on CoWoS with
system BIST solution." VLSI Circuits (VLSIC), 2013 Symposium on. IEEE, 2013.
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6578710&isnumber=6578626
11. Chen, S. M., et al. "High-performance inductors for integrated fan-out wafer level packaging (InFO-WLP)." VLSI
Technology (VLSIT), 2013 Symposium on. IEEE, 2013.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6576680&isnumber=6576594
12.Yu, Doug CH. "New System-in-Package (SiP) Integration technologies."Custom Integrated Circuits Conference
(CICC), 2014 IEEE Proceedings of the. IEEE, 2014.
14. Chung-Hao Tsai; Jeng-Shien Hsieh; Monsen Liu; En-Hsiang Yeh; Hsu-Hsien Chen; Ching-Wen Hsiao;
Chen-Shien Chen; Chung-Shi Liu; Mirng-Ji Lii; Chuei-Tang Wang; Doug Yu, "Array antenna integrated
fan-out wafer level packaging (InFO-WLP) for millimeter wave system applications," Electron Devices
Meeting (IEDM), 2013 IEEE International , vol., no., pp.25.1.1,25.1.4, 9-11 Dec. 2013
doi: 10.1109/IEDM.2013.6724687

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