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Implementation with
SystemVerilog
Module #2: SystemVerilog
Michael A. Warner
Worldwide Consulting Manager
Copyright 2001-2003,
Copyright 1999-2009,
Model Technology
Mentor Graphics Corporation
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SystemVerilog Training
Agenda
Verification Planning
Testbench Architecture
Testbench Implementation
SystemVerilog Basics
OOP with SystemVerilog
OVM Introduction
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Lexmark, June 25, 2007
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SystemVerilog Basics
Introduction to SystemVerilog
Data Types, Arrays & Literals
Behavioral Modeling
Design Structure & Hierarchy
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Copyright 2001-2003,
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What is SystemVerilog?
SystemVerilog is a standard set of extensions to the IEEE
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Copyright 2001-2003,
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SystemVerilog
2005
Verilog 2001
Verilog 1995
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SystemVerilog Basics
Introduction to SystemVerilog
Data Types
Behavioral Modeling
Design Structure & Hierarchy
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Copyright 2001-2003,
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int
longint
byte
bit
logic
reg
integer
time
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SystemVerilog Training
String Type
String literals in SystemVerilog same as Verilog
SV also provides string type
Strings can be arbitrary length
No truncation
Equality
str1 != str2
Inequality
Comparison
Concatenation
{multiplier{str1}}
str1[index]
Replication
Indexing Returns ASCII code at index (byte)
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Copyright 2001-2003,
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String Methods
SystemVerilog has a robust set of string methods
str.len()
str.putc()
str.getc()
str.Toupper()
str.Tolower()
str.compare()
str.icompare()
str.substr()
str.atoi()
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SystemVerilog Training
str.atooct()
str.atobin()
str.atoreal()
str.itoa()
task itoa(integer i)
str.hextoa()
task hextoa(integer i)
Inverse of atohex
str.octtoa()
task octtoa(integer i)
Inverse of atooct
str.bintoa()
task bintoa(integer i)
Inverse of atobin
str.realtoa()
task realtoa(real i)
Inverse of atoreal
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types
// create a new type
typedef int inch;
// declare two new variables of type inch
inch foot = 12, yard = 36;
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SystemVerilog Training
Type Operator
The SystemVerilog type operator improves parameterized
models
module DFF #(parameter type data_t = int)(
input data_t D,
input clk, rst,
output data_t Q);
Ports specified
using the type
parameter
Cast literal to
the type
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Data Organization
Desire to organize data
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SystemVerilog Training
Grouping
Not restricted to
struct {
addr_t SrcAdr;
addr_t DstAdr;
data_t Data;
} Pkt;
Pkt.SrcAdr = SrcAdr;
if (Pkt.DstAdr == Adr)
local_data = Pkt.Data;
yields longer
expressions but
facilitates more
meaningful code
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Arrays
SystemVerilog adds many new types and operations
on arrays
Packed/Unpacked arrays
Array querying functions
Dynamic arrays
Associative arrays
Queues
Array manipulation methods
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memories:
unpacked arrays
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SystemVerilog Training
Dynamic Arrays
A dynamic array is a one-dimensional array with NO range
specified at declaration
No space allocated until sized during runtime
Increase or decrease size any time during simulation
Check memory size any time during simulation
logic [7:0] mem [];
initial begin
mem = new[128];
#10 mem[62] = 8h8f;
#10 mem[131] = 8h16;
#10 mem = new[mem.size * 2] (mem);
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SystemVerilog Training
Copyright 2001-2003,
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Associative Arrays
User-defined index type
Memory allocated as elements are written
Associative arrays are very useful during verification
Out of order scoreboards
Random access read/write
Model Sparse memories
Conserve memory
Simple coverage information
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Associative Arrays
Index specifier can
be any datatype
typedef enum {
Read, Write, FullWR
} OPERATIONS;
int Operation_Cnt[OPERATIONS];
Operation_Cnt[Write]++;
Operation_Cnt.delete(Write);
Operation_Cnt.delete;
Increment count
Delete one index
Delete all indexes
Copyright 2001-2003,
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SystemVerilog Basics
Introduction to SystemVerilog
Data Types
Behavioral Modeling
Design Structure & Hierarchy
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Copyright 2001-2003,
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Increment Operators
The ++ and -- operators have been added to
SystemVerilog
j = i++
j = ++i
j = i--
j = --i
statement
i++; // synthesizable
sum = i++; //not synthesizable
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Assignment Operators
All assignment operators behave as blocking assignments
RHS = Right-hand side LHS = Left-hand side
+=
-=
*=
/=
%=
&=
|=
^=
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>>=
<<<=
>>>=
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Equality Operators
==
!=
===
!==
=?=
!?=
=?=
=?=
=?=
=?=
0101
010X
XXX0
X1XX
//True
//True
//True
//False
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Processes
Verilog provides a simple process spawning capability via
fork
fork
join
join_any
join_none
Doesnt block
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NOTE:
No longer require
begin/end on tasks
or functions
Match names for
task & endtask
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Functions
In SystemVerilog functions now use the return statement
to return a value
Old:
New:
function int mult (input int a, b)
return (a * b);
Return type inferred by
endfunction : mult
function type
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Enhanced Loops
The foreach construct allows you to easily iterate
$display(Value is %d,i);
end
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Use when you know you will execute the loop at least
once
Same synthesis rules that apply to while loops apply to
do..while loops. Generally are not synthesizable due to
their dynamic nature.
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Mailboxes
Used for inter-process communication
mailbox #(packet_t) m_channel = new(25);
m_channel accepts
up to 25 objects of
type packet_t
Put the packet P into
the mailbox
Get the next packet
on the stack out of
the mailbox & place it
in P
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Mailbox Methods
new()
num()
get()
try_get()
peek()
try_peek()
put()
try_put()
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Semaphore
Provides control of shared resources for multiple processes
system bus or memory
Conceptually a bucket with a fixed set of keys
Processes using a semaphore need to procure a key or
semaphore want_to_control;
want_to_control = new();
want_to_control.get();
want_to_control.put();
want_to_control.try_get();
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SystemVerilog Training
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SystemVerilog Basics
Introduction to SystemVerilog
Data Types
Behavioral Modeling
Design Structure & Hierarchy
36
SystemVerilog Training
03/04/2010
Copyright 2001-2003,
Copyright 1999-2009,
Model Technology
Mentor Graphics Corporation
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Packages
Provides support for sharing throughout design
nets
variables, types, package imports
tasks, functions, dpi_import_export
classes, extern constraints, extern methods
parameters, local parameters, specparams
properties, sequences
anonymous program
and SystemVerilog
Compile with vcom/vlog -mixedsvvh
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Package Declaration
Define new types
package ComplexPkg;
typedef struct {
Create global variables
float i, r;
} Complex;
NOTE: Assignments are
Complex C_data = {i:2.0, r:5.7};
done before any initial or
function Complex ADD (Complex a, b)
always blocks are started
ADD.r = a.r + b.r;
ADD.i = a.i + b.i;
endfunction : ADD
function Complex MULT (Complex a, b)
MULT.r = (a.r * b.r) + (a.i * b.i);
MULT.i = (a.r * b.i) + (a.i * b.r);
Define functions to
endfunction : MULT
operate on the new
endpackage : ComplexPkg
types
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Using Packages
SystemVerilog provides several ways to use the contents
of packages
Scope resolution operator
ComplexPkg::C_data = ComplexPkg::MULT(a, b);
Explicit import
import ComplexPkg::C_data;
initial C_data = {i:6.0,r:2.7};
Wildcard import
import ComplexPkg::*;
Initial C_data = ADD(a, b);
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Copyright 2001-2003,
Copyright 1999-2009,
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Mentor Graphics Corporation
03/04/2010
Copyright 2001-2003,
Copyright 1999-2009,
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Mentor Graphics Corporation
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Copyright 2001-2003,
Copyright 1999-2009,
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