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Keywords: nanoelectronics,
non-classical CMOS, SOI,
transport enhanced FETs,
Multi-gate transistor, high-k
gate dielectric, short channel
effect, gate tunneling,
non-CMOS memory and
logic, MEMS, NEMS, SoC,
variability, low power.
Moores law: Moores law is
an empirical observation and
extrapolation made by
Gorden Moore in 1965 the
component density on an
integrated circuit doubles
every year. Although there
has been an exponential
growth in the component
density in the last four
decades, as predicted by
Moores law, the growth rate
has decreased with the
component density doubling
every two to three years.
issues of growing power dissipation and increasing device to device variability in the chips
should be overcome for the successful realization of complex systems in nanoelectronics
technologies. A brief overview of the non-CMOS memory and logic device architecture is
provided. The opportunities in building hybrid systems on chips by combining sensors and
actuators along with the compute and storage functions on a single chip are described.
1. Introduction
The growth in electronics industry since the
invention of the first Integrated Circuit (IC) chip
in 1958 [1], is probably unparalleled by any other
industry sector. The cumulative aggregate growth
rate (CAGR) is about 15% in the last 5 decades [2].
This has been possible due to the exponential
increase in the component density integrated on a
single chip, as predicted by Moores law [3,4]. An
implicit assumption in the Moores law is that we
can shrink the feature size of the transistor the
basic building block of an IC at an exponential
rate. The compound annual reduction rate of
the transistor dimension is more than 10%, over
the last 5 decades. In 1999, the transistor gate
length crossed the 100nm barrier, leading to the
volume production of the nanoelectronics chips.
Today, nanoelectronics has been the most successful
commercial manifestation of the nanotechnology,
with the 65 nm CMOS technology in volume
production.
The history of silicon technology development
underscores several innovations that enabled
Journal of the Indian Institute of Science VOL 87:1 JanMar 2007 journal.library.iisc.ernet.in
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Navakanta Bhat
System Architecture
Application
Domain
Circuit Design
Device Physics
Technology
Domain
Process Technology
Journal of the Indian Institute of Science VOL 87:1 JanMar 2007 journal.library.iisc.ernet.in
Silicon CMOS
Performance
1960
2000
2020
Traditional Scaling Path (shrinking feature size)
Technology Drivers: Memory and Logic
Technology Drivers: Memory and Logic
Materials : Silicon coexisting with variety
Materials : Silicon and its derivatives
of materials to enable new devices
such as SiO2, Si3N4 etc.
Device Architecture: Non Classical CMOS
Device Architecture: Classical CMOS
(short term) and Non CMOS (long term)
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2.1. Non classical CMOS
2.1.1. High-k gate dielectrics
Figure 5(a) shows the SiO2 gate oxide thickness
scaling trend in CMOS technology. For the 65 nm
technology node, the SiO2 thickness is about 1nm
which is essentially two mono-layers of SiO2 film.
Figure 5(b) shows the energy band diagram of
the NMOS structure in the vertical direction for a
positive applied bias. (This discussion holds good
for the negative gate bias as well, except that the
gate Fermi level, Ef, will be above the substrate
and the electrons will be tunneling from the gate
electrode). Typically, the conduction across the
SiO2 insulator layer is negligible due to very large
band offset (3.1eV) between the conduction
band of gate/substrate and the conduction band
of the oxide. However, for an ultra-thin gate
oxide with T ox < 5 nm, carriers can quantum
mechanically tunnel through the oxide and result
in large gate leakage current. Furthermore, the
tunneling probability increases exponentially with
decrease in T ox . Figure 6 shows the gate leakage
current density for different gate oxide thickness.
The gate leakage current density of 100 A/cm2
indicates that, the transistor with 50 nm gate length
results in a gate leakage of 50 nA per unit micron
width (50 nA/m). This is more than 20% of
the total off state leakage current budget of the
transistor. Hence it is not possible to scale T ox any
further. This calls for replacement of SiO2 with an
alternate gate insulator which has higher dielectric
constant (k). The high-k dielectric of thickness
of T k is equivalent
to effective oxide thickness of
EOT = 3.9 k T k , where SiO2 dielectric constant
is 3.9. Hence, it is possible to use thicker insulator
and reduce the gate tunneling current (Fig. 7),
while maintaining capacitive coupling of the gate
electric field to the channel that is equivalent to
thinner oxide. Table 2 lists the properties of some
potential gate insulators that are being explored.
In addition to high-k, the insulator should also
have other important properties such as very good
interface with Si resulting in minimal interface
traps, thermodynamic stability, large band gap and
band offset with Silicon. Among the various high-k
dielectrics, HfO2 and some of the rare earth metal
oxides are very promising at this time [1014]. The
high-k gate dielectrics are expected to be introduced
in the 45 nm CMOS technology node.
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Navakanta Bhat
Table 1: Projected technology nodes from International Technology Roadmap for Semiconductors. The technology nodes are scaled by a factor of 0.7,
corresponding to doubling of device density (except the year 2020). Note that the transistor size in any given technology node is significantly smaller
than the node nomenclature.
Year of Production
2007
2010
2013
2016
2019
2020
65
45
32
22
16
14
25
18
13
12
12
18
18
18
18
33
35
37
37
39
39
1.1
2.2
4.4
8.8
17.7
17.7
15
16
17
17
18
18
1088
1450
1930
2568
3418
3760
1.1
1.0
0.9
0.8
0.7
0.7
9.3
15.1
23
39.7
62.4
73.1
189
198
198
198
198
198
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Bandgap (eV)
SiO2
3.9
3.15
Si3 N4
7.9
5.3
2.4
Al2 O3
10
8.8
2.8
HfO2
1630
4.56
1.5
ZrO2
1216
5.8
1.5
TiO2
80170
3.05
ReO2 *
1230
2.55.5
13
Material
Figure 3: The cross section of NMOS transistor and typical dimensions in 65 nm CMOS technology.
Lg
n+ Poly
Gate
50 nm
SiO2
100 nm
SiO2 thickness
1 nm
Source/Drain depth:
extension and deep region
40 nm and 100 nm
Source/Drain doping
~1020/cm3
Substrate doping
~1017/cm3
n+
Source
n+
Drain
P type Si substrate
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Navakanta Bhat
Figure 5: (a) Gate oxide thickness trend as a function of technology scaling; (b) Energy band diagram for
NMOS with positive gate voltage.
(a)
(b)
Tox
Tox (nm)
TUNNELING
Ec
1.5
Ef
Ev
Ef
1.0
Gate
50
66
100
Oxide
Silicon
Lg (nm)
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104
102
100
Tox = 1.4 nm
= 1.5 nm
= 1.8 nm
10-2
10-4
Symbols Data
Solid line Model
10-6
0.5
Chalcogenides: The
compounds consisting of
chalcogen element group
VI element in the periodic
table can be switched
between a high resistance
amorphous phase and a low
resistance crystalline phase. A
very common chalcogenide
used in phase change
memory is Telurium (Te)
compound GeSbTe.
1.5
2
Gate voltage (V)
2.5
1E 2
1E 0
1E-2
1E-4
1E-6
1E-8
1E-10
1
2
Physically effective oxide thickness (nm)
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need different gate work functions, complicating
the integration of the gate metal in the CMOS
technology [25]. The work function engineering
of the gate electrode will play an important role
in deciding the V t of the transistor and hence the
choice of the appropriate material.
The combination of all these techniques may
become essential to enable scaling of the CMOS
device technology to an ultimate limit of about 5
nm physical gate length by the year 2020. However
several innovations are required in semiconductor
process technology to enable such devices. The
detailed discussion of the process technology
requirements is beyond the scope of this article.
One of the key process technology requirements
is the scalability of the photolithography process
beyond 65 nm technology node. In the immediate
future, 193 nm UV with immersion technique
may be sufficient. However, alternative lithography
techniques such as Extreme UV lithography, mask
less lithography, imprint lithography, electron beam
lithography may be necessary to reach the ultimate
CMOS scaling limit.
2.2. Non CMOS architectures
The non-CMOS architectures will be required
to continue the performance enhancement of
nanoelectronics systems beyond the ultimately
scaled CMOS. Some of these device structures
will also require completely different information
processing paradigms. Any electronics system
fundamentally does two tasks: computation and
storage. The computational element is referred
to as Logic block and the storage element is
referred to as Memory block. A particular system
architecture combines these blocks to yield the
required functionality. For example, the current
CMOS technology is utilized to build systems based
on digital boolean architectures, operating on the
binary variable.
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Navakanta Bhat
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Journal of the Indian Institute of Science VOL 87:1 JanMar 2007 journal.library.iisc.ernet.in
Si film
(100nm)
SOI technology
Insulator
500m
Si wafer
Si wafer
REVIEW
classes of problems addressed by CMOS computing
architecture are amenable for quantum computing
architecture.
The molecular transistor, or the possibility of
creating a switching device on a single molecule, has
raised the expectations for the fascinating field
of Molecular electronics [41]. These devices
can potentially result in very high density with
the device size of the order of 1nm. However,
some of the major issues include assembling
these devices on giga-scale and interconnecting
them appropriately to yield complex systems. In
fact, a completely different system architecture
may be required to utilize these devices. Another
important issue relates to the fabrication of these
devices. These devices will likely be fabricated
using chemical synthesis, i.e. atoms-up approach,
rather than the conventional top-down approach
using photolithography. This could be a disruptive
technology that can enhance the nanoelectronics
system performance very significantly beyond the
ultimately scaled CMOS.
It is expected that none of the non-CMOS
architectures can really replace the ultimately scaled
CMOS. Instead, CMOS architectures will co-exist
with a variety of other device technologies and
enable the nanoelecronics system performance
enhancement beyond 2020.
3. Circuits and Systems Design
The two important issues in realizing the giga-scale
integrated circuits is the exponential increase in
the power dissipation and the device variability. It
is absolutely essential to manage these issues for a
successful scaling of the CMOS technology to reach
the ultimate limit by 2020. Although some of the
novel device technologies are attempting to address
these issues to some extent, novel design techniques
at the circuits and systems level are considered to be
very important.
log (Ids)
Vt1 < Vt
Vgs
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Navakanta Bhat
Figure 12: 3-Dimensional FinFET structure. The current flows from source
(S) to drain (D) in lateral direction, through the channel wrapped around
by the gate fin (G).
102
101
Active Power
Power (W)
100
10-1
386
486DX
CPU
Pentium R II
Processor
10-2
10-3
10-4
Standby Power
(Transistor T=110C)
10-5
10-6
1.0
0.8
0.6
.35
Technology Generation (m)
.25
.18
Oxidation
Deposition
Implantation
Diffusion
70
P
R
O
C
E
S
S
Tox
Id
Tsp
CL
Na
Vt
Xj
Vt
Speed
C
I
R
C
U
I
T
Dynamic power
Static power
Yield
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VDD
Signal amplitude
Vt
6Vt
Technology
1m
0.1m
ACOUSTIC MEMS
Ultra sound sensor
Microphone
INERTIAL MEMS
Accelerometer
Gyroscope
Pressure sensor
RF MEMS
Resonator
Switch
Phase-shifter Antenna array
OPTICAL MEMS
Micromirror
Cross connects
Grating
Switch
Varactor
Bio sensor
BIO MEMS
Micro probes DNA chips PCR Cell-culture
CHEMICAL / GAS SENSORS
Trace elements
Hazardous gases
POLYMER ELECTRONICS
LED
Photovoltaic diode
Polymer IC
Micro heater
Energy harvesting
Super capacitor
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4. Hybrid Systems on a Chip
Traditionally, the electronics system performance
has been enhanced in the context of Moores law by
increasing the computing performance and storage
capacity of the chips. However, for the past few years,
it is becoming increasingly important to exploit
the silicon technology infrastructure into other
application domains. Specifically, the functional
integration of nonelectronic domain components
onto the chip is being driven by, what is popularly
known as, the More than Moore philosophy. These
chips are also referred to as Hybrid Systems on Chips
because there is on chip interaction of multiple
energy domains.
Figure 16 illustrates the different possibilities
in terms of functional integration. In a majority
of these cases the same set of semiconductor
processes that are traditionally used to build
transistors, are utilized to create micro/nano
machined (MEMS/NEMS) structures on silicon.
These structures can act as sensors and actuators
and interface with the on chip electronics. Silicon
has excellent mechanical properties, which enables
the creation of robust mechanical building blocks
such as beams, membranes, rigid masses, etc [57].
The success of such hybrid SOCs can be illustrated
through some of these chips that have penetrated
the consumer applications. Most of the airbag
release systems deployed in automobiles employ
a MEMS accelerometer chip [58]. It consists of
a suspended poly-silicon proof mass created on
top of Silicon substrate through surface micromachining technique. The mass is configured as
one of the plates of the capacitor, and hence the
capacitance changes in response to acceleration. The
movement of the proof mass is measured through
capacitance sensing using the electronics interface
circuit on the chip. This integration results in high
reliability, low cost and high performance solution
which can be deployed in a variety of applications.
Another great success story has been the Digital
Micromirror Display (DMD) device in the optical
MEMS domain [59] which is routinely used to
replace the LCD projectors. In this case, the pixel
array of suspended micromirrors is created on top
of electronics chip which provides the information
to be displayed. Each of the micromirror is electrostatically actuated to control the reflection of the
light to produce the appropriate grey level for the
pixel. Similar opportunities exist in various other
domains as illustrated in Fig. 16. These systems are
also expected to be autonomous through harvesting
the energy from the environment. Eventually the
convergence of electronics and biology for lab-on-achip applications in diagnostics and therapy may
be the biggest technological revolution in the 21st
century.
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Navakanta Bhat
5. Conclusions
The Silicon CMOS technology will continue to
be scaled to an ultimate limit of about 5 nm
physical gate length of a transistor, albeit requiring
several innovations in process technology, materials
engineering, and exploitation of new device physics.
The nanoelecronics system performance is expected
to scale according to the predictions of Moores law
along this path. However, the circuit and system
level issues of power management and variability
tolerance should be addressed through novel
techniques. After the end of the CMOS roadmap,
beyond 2020, radically new device technologies
will be required for further enhancement of system
performance. The performance enhancement of
the SOCs will also evolve along a new trajectory
of functional integration to include non electrical
domain components. The sensors and actuators
integrated along with the conventional compute
and storage functions will open up new application
domains.
A. Centre of Excellence in Nanoelectronics
The Ministry of Communication and Information
Technology (MCIT), Government of India, has
initiated an ambitious project to set-up two Centres
of Excellence in Nanoelectronics at the Indian
Institute of Science, Bangalore and the Indian
Institute of Technology, Bombay. This project has
an outlay of Rs. 100 crores over 5 years (20062010)
to create comprehensive nanofabrication facilities
(nanofabs) at these two institutes. These nanofabs
will act as nodal centres in the country to facilitate
the state-of-the-art experimental research. The
nanofab infrastructure will enable the fundamental
exploration in several areas of nano science and
engineering and it is also expected to seed new
technologies that will have societal and commercial
impact.
At IISc, a large number of faculty members from
various disciplines of science and engineering are
involved in this project. The institute has taken a lead
to foster this interdisciplinary effort by initiating the
creation of a new building to support the nanofab
infrastructure. The nanofab is expected to be fully
functional by 2008. When completed, it would be
on-par with some of the best university nanofabs
elsewhere. The facility will also be available for
other researchers in the country through the Indian
Nanoelectronics Users Program (INUP).
Received 07 December 2006; revised 31 January 2007.
References
1. The Chip that Jack Built Changed the World, http://www.ti.
com/corp/docs/kilbyctr/jackbuilt.shtml
72
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Embedded Computing Systems (TECS), p. 321, 2006.
46. Marcel J. M. Pelgrom, Hans P. Tuinhout and Maarten Vertregt,
Transistor Matching in Analog CMOS Applications, IEDM
Tech. Dig., 1998, pp. 915918.
47. H. C. Srinivasaiah and Navakanta Bhat, Mixed Mode
Simulation Approach to Characterize the Circuit Delay
Sensitivity to Implant Dose Variations, IEEE Transactions on
CAD of Integrated Circuits and Systems, Vol. 22. No.6, June
2003.
48. H. C. Srinivasaiah and Navakanta Bhat, Monte Carlo Analysis
of the Implant Dose Sensitivity in 0.1m NMOSFET, Solid
State Electronics, Volume 47, pp. 1379 1383, Aug. 2003.
49. B.P. Harish, Mahesh B. Patil and Navakanta Bhat, On A
Generalized Framework for Modeling the Effects of Process
Variations on Circuit Delay Performance To appear in IEEE
Transactions on Computer Aided Design of Integrated Circuits
and Systems
50. R. Singh and N. Bhat, An Offset Compensation Technique for
Latch Type Sense Amplifier in High Speed Low Power SRAMs,
IEEE Transactions on VLSI Systems, pp. 652657, June 2004.
51. N. Bhat and S. Mukherjee, Yield and Speed Enhancement of
Semiconductor Integrated Circuits using Post Fabrication
Transistor Mismatch Compensation Circuitry, US patent
#6934200 , 2005.
52. S. Narendra, A. Keshavarzi, B. A. Bloechel, Shekhar Borkar,
and Vivek De, Forward Body Bias for Microprocessors in 130nm Technology Generation and Beyond, IEEE J. of Solid-State
Circuits, p. 696, May 2003.
53. A. Gupta and N. Bhat, Asymmetric Cross-Coupled
Differential Pair Configuration to Realize Neuron Activation
Function and its Derivative, IEEE Transactions on Circuits
and Systems Part II: Express Briefs, Vol. 52, No. 1, pp. 10-13,
January 2005
54. A. Gupta and N. Bhat, Back-Gate Effect to Generate
Derivative of Neuron Activation Function, Analog Integrated
Circuits and Signal Processing, Kluwer 41 (1), pp. 89-92,
October 2004
55. Heath, J. R., et al. A Defect Tolerant Computer Architecture:
Opportunities for Nanotechnology, Science, p. 1716, 1998.
J. H. Lee, X. Ma, and K. Likharev. Neuromorphic
56. Turel, O,
architectures for nanoelectronic circuits, Int. J. Circuit Theory
and Applications, p. 277 , 2004.
57. K. E. Peterson, Silicon as a mechanical material, Proc. IEEE,
vol. 70, pp. 420457, May 1982.
58. Analog Devices Products, http://www.analog.com/index.
html
59. M.R.Douglass, DMD reliability: a MEMS success story
http://www.dlp.com/dlp technology/images/dynamic/
white papers/153 Reliability paper.pdf
Navakanta Bhat Navakanta Bhat received
his B.E. in Electronics and Communication
from University of Mysore in 1989, M.Tech.
in Microelectronics from I.I.T. Bombay in
1992 and Ph.D. in Electrical Engineering from
Stanford University, Stanford, CA in 1996.
Then he worked at Motorolas Networking and
Computing Systems Group in Austin, TX until
1999. At Motorola he worked on logic technology development
and he was responsible for developing high performance transistor
design and dual gate oxide technology. He joined the Indian
Institute of Science, Bangalore in 1999 where he is currently an
Associate Professor in the Electrical Communication Engineering
department. His current research is focused Nano-CMOS
technology and Integrated CMOS-MEMS sensors. The work
spans the domains of process technology, device design, circuit
design and modeling. He has several research publications in
international journals and conferences and 3 US patents to his
credit. He has received the Young Engineer Award (2003) from the
Indian National Academy of Engineering. He is also the recipient
of the Swarnajayanti fellowship (2005) from the Department of
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