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November 2008
Copyright 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
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UG-MF9504-4.0
Contents
1-1
1-1
1-1
1-2
1-3
1-3
1-3
1-4
1-4
iv
Contents
Chapter 3. Specifications
Ports and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Additional Information
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-1
Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-2
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-2
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-2
Introduction
As design complexities increase, use of vendor-specific Intellectual Property (IP)
blocks have become a common design methodology. Altera provides parameterizable
megafunctions that are optimized for Altera device architectures. Using
megafunctions instead of coding your own logic saves valuable design time.
Additionally, the Altera-provided functions may offer more efficient logic synthesis
and device implementation. You can scale the megafunctions size by setting
parameters.
Arria GX
Stratix IV
Stratix III
Stratix II
Stratix II GX
Stratix GX
Stratix
Cyclone III
Cyclone II
Cyclone
HardCopy II
HardCopy Stratix
APEX II
APEX 20KC
APEX 20KE
Features
The ALTLVDS megafunction implement either an LVDS deserializer receiver or an
LVDS serializer transmitter and offer many additional features:
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Dynamic Phase Alignment (DPA) mode support in Stratix IV, Stratix III, Stratix II
GX, Stratix II and Stratix GX receivers.
Ability to share fast phase-locked loops (PLLs) between transmitter and receivers.
Support for separate PLL in Stratix IV, Stratix III, Stratix II, Stratix II GX,
Cyclone III, Cyclone II, Cyclone, and HardCopy II devices.
Soft Clock-Data Recovery (CDR) mode support for Stratix IV and Stratix III
devices.
General Description
The ALTLVDS megafunction is provided in the Quartus II software, through the
MegaWizard Plug-In Manager. The ALTLVDS megafunction instantiates LVDS
transmitters (ALTLVDS_TX) and LVDS receivers (ALTLVDS_RX). The ALTLVDS_TX
megafunction implements a serialization transmitter, and the ALTLVDS_RX
megafunction implements a deserialization receiver. These megafunctions can be
used to take advantage of the dedicated SERDES circuitry for high-speed differential
data transfer applications in Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix GX,
Stratix, HardCopy II, and HardCopy Stratix devices. The ALTLVDS megafunction can
also be used to implement SERDES circuitry using logic elements (LEs) and PLLs in
Cyclone III, Cyclone II and Cyclone devices. By using the LVDS megafunctions, you
can customize and control the LVDS data received or transmitted to many source
synchronous channels. The ALTLVDS megafunction has features that are unique to
each supported device family.
To achieve high data transfer rates, the Stratix IV, Stratix III, Stratix II, Stratix II GX,
Stratix GX, Stratix, HardCopy II, and HardCopy Stratix devices support True-LVDS
differential I/O interfaces that have dedicated SERDES circuitry for each differential
I/O pair.
f
For transmitting and receiving data rates for respective devices, refer to the specific
device data sheets.
On the receiver side, the high-frequency clock generated by the PLL shifts the serial
data through a shift register (also called the deserializer). The parallel data is clocked
out to the logic array that is synchronized with the low frequency clock.
On the transmitter side, the parallel data from the logic array is first clocked into a
parallel-in, serial-out shift register that is synchronized with the low-frequency clock,
and then transmitted out by the output buffers.
The dedicated phase alignment (DPA) circuitry supports multiple SERDES factors.
Each channel has its own DPA circuit that provides independent data alignment for
each channel; therefore, DPA can reduce channel-to-channel skew as well as
clock-to-channel skew.
Cyclone series (Cyclone III, Cyclone II, and Cyclone) devices do not support the
dedicated DPA circuitry.
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Cyclone series (Cyclone III, Cyclone II, and Cyclone) devices also allow the SERDES
implementation at certain data rates for a specific device. For the LVDS transmitter
and receiver, the ALTLVDS megafunction implements serialization and
deserialization using LEs and PLLs.
f
For supported data rates, refer to the specific device data sheets.
Clock Forwarding
The Stratix IV and Stratix III LVDS block supports clock forwarding to the core. In soft
CDR mode, the DPA clock is forwarded to the core after being divided by the
deserialization factor. The divclkout output signal from the LVDS block holds the
forwarded clock signal. The signal is routed to the new periphery clock (PCLK)
network.
The DPA block determines the optimal DPA clock, which is forwarded to the core. In
normal DPA operation, the DPA block selects an optimal phase to sample the data.
The captured data is passed to the bitslip block, then to the deserializer. The
deserializer divides the DPA clock and the data by the deserialization factor. The
newly divided clock signal is placed on the PCLK network, which carries the clock
signal to the core. In Stratix IV and Stratix III devices, each LVDS channel can be in
soft CDR mode and can drive the core using the PCLK network.
f
The PCLK network originates in the DPA block of a Stratix IV or a Stratix III device.
For more information about PCLKs, refer to the Clock Networks and PLLs in Stratix IV
Devices chapter in volume 1 of the Stratix IV Device Handbook and the Clock Networks
and PLLs in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook.
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You can specify the ppm value using two new simulation-only parameters for the
ALTLVDS megafunction. The value of NET_PPM_VARIATION is the absolute value of
the drift, and the IS_NEGATIVE_PPM_DRIFT parameter specifies whether the drift is
positive or negative. The Quartus II simulator simulates the ppm variation by shifting
the recovered data and clock based on the user-specified ppm value.
Common Applications
The SERDES interface is used to transmit and receive high-speed differential data.
This enables moving data from board-to-board or box-to-box with great efficiency.
This high performance consumes minimum power, is relatively immune to noise, and
is cost effective. Typical applications of LVDS technology are common in PC
computing (such as flat panel displays and monitor links), telecommunication and
data-communication systems (such as routers, hubs, and switches) and other common
consumer and commercial applications (such as set-top boxes and in-flight
entertainment).
The Stratix IV and Stratix III LVDS block supports a new soft CDR mode. This mode
supports the widely-used SGMII protocol. A clock-data recovery removes the clock
from the clock-embedded data, a capability required for the SGMII support. This new
mode is called soft CDR mode because the CDR circuitry is implemented in the LEs.
f
For additional information about common applications supported, and for full details
on the I/O standards and high-speed protocols supported, refer to the applicable data
sheet or device handbook for each device family.
For more information about the PLL parameters, refer to the ALTPLL Megafunction
User Guide.
All Stratix families support the Use Shared PLL(s) for Receiver and Transmitter
option to place both the LVDS transmitter and the LVDS receiver in the same device
I/O bank. The Quartus II software lets the transmitter and the receiver share the same
fast PLL when both use the same input clock frequency. Although you must separate
the transmitter and receiver modules in your design, the Quartus II software merges
the fast PLLs, when appropriate, and gives you the following message:
Info: Receiver fast PLL <lvds_rx PLL name> and transmitter fast PLL
<lvds_tx PLL name> are merged together
The Quartus II software displays the following message when it cannot merge the fast
PLLs for the LVDS transmitter and receiver pair in the design:
Warning: Can't merge transmitter-only fast PLL <lvds_tx PLL name>
and receiver-only fast PLL <lvds_rx PLL name>
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For Stratix device families, the side I/O banks contain dedicated SERDES circuitry,
which includes the fast PLLs, serial shift registers, and parallel registers. The transmit
and receive functions use varying numbers of LEs depending on the number of
channels, serialization and deserialization factors. For best performance, these LEs
must be placed in columns as close to the SERDES circuitry and LVDS pins as
possible. This is done by the Quartus II software automatically during
place-and-route.
Cyclone III, Cyclone II, and Cyclone devices use DDIO registers as part of the
SERDES interface. Since data is clocked on both the rising and falling edge, the clock
frequency must be half the data rate; therefore, the PLL runs at half the frequency of
the data rate. The core clock frequency for the transmitter is data rate divided by the
serialization factor (J). For the odd serialization factors, depending on the output
clock-divide factor (B) and device family, an optional core clock frequency of data rate
divided by two times the serialization factor (J) is also available.
Use Table 11 and Table 12 to determine the clock and data rate relationships.
Table 11. Cyclone III, Cyclone II, and Cyclone ALTLVDS Receiver Clock Relationships
Clock Type
J = Even
J = Odd
Fast Clock
Data Rate / 2
Data Rate / 2
Data Rate / J
Data Rate / J
Table 12. Cyclone III, Cyclone II, and Cyclone ALTLVDS Transmitter Clock Relationships
Clock Type
J = Even
J = Odd
Fast Clock
Data Rate / 2
Data Rate / 2
Data Rate / 2 * B
Data Rate / 2 * B
Core Clock
Data Rate / J
Data Rate / J
The Quartus II software reports the number of LEs used per ALTLVDS function in the
Fitter Resource Utilization by Entity section within the Resource section of the
Compilation Report file.
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2. Getting Started
Introduction
The most efficient way to customize your ALTLVDS megafunction is the
MegaWizard Plug-In Manager . Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix,
Stratix GX, HardCopy II, and HardCopy Stratix devices each have different features
available when using the dedicated serializer/deserializer (SERDES) circuitry.
Cyclone III, Cyclone II, and Cyclone devices do not have dedicated SERDES
circuitry; therefore, the functions are implemented in registers using logic elements
(LEs). The wizard displays only the features that are appropriate to the selected
device family. Within each selected device, certain features are available, depending
on the modes that you specify.
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When working in the Block Editor, from the Edit menu, click Insert Symbol as
Block, or right-click in the Block Editor, point to Insert, and click Symbol as
Block. In the Symbol window, click MegaWizard Plug-In Manager.
Start the stand-alone version of the MegaWizard Plug-In Manager by typing the
following command at the command prompt:
qmegawiz r
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For online help, click the Documentation button to view the Quartus II Help file for
the LVDS transmit or receive megafunction.
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On page 3, several options can be customized for the transmitter settings. The options
are described in Table 21.
Table 21. ALTLVDS Transmitter Settings Page Options and Descriptions (Page 3)
Option
Description
Comments
Implement Serializer/Deserializer
circuitry in logic cells
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Page 4 of the MegaWizard Plug-In Manager is the Frequency/PLL settings page. This
page appears only if an internal PLL is used.
Table 22 describes the options you have on page 4 to customize the frequency and
PLL settings.
Table 22. ALTLVDS Transmitter Frequency/PLL Settings Page Options and Descriptions (Page 4)
Option
What is the output data rate?
(Part 1 of 2)
Description
Comments
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Table 22. ALTLVDS Transmitter Frequency/PLL Settings Page Options and Descriptions (Page 4)
Option
Description
(Part 2 of 2)
Comments
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Page 5 is the Transmitter settings page. It is used to specify the transmitter settings
options. The options for this page are described in Table 23.
Table 23. ALTLVDS Transmitter Settings Page Options and Descriptions (Page 5)
Option
Use tx_outclock output port
(Part 1 of 2)
Description
Comments
When outclock_divide_by = 1, or
When outclock_divide_by =
deserialization_factor (for odd
factors only) and outclock_duty_cycle
is 50.
deserialization_factor is 5, 7 or 9
outclock_divide_by =
deserialization_factor
outclock_multiply_by is 2.
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Table 23. ALTLVDS Transmitter Settings Page Options and Descriptions (Page 5)
Option
Description
(Part 2 of 2)
Comments
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For more information about external PLL options, refer to the AN 409: Design Example
Using the ALTLVDS Megafunction & the External PLL Option in Stratix II Devices.
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If you use an Arria GX, Stratix II, Stratix II GX, or HardCopy II device, clock your
LVDS transmitter using an external PLL, and implement the SERDES for the
transmitter using a dedicated SERDES block, a different notification window pops up
after you enter these settings on page 3 of the MegaWizard Plug-In Manager
(Figure 22).
Figure 22. MegaWizard Plug-In Manager Notification for Other Devices (LVDS Transmitter)
For Stratix, Stratix GX, and HardCopy Stratix devices, if you implement the SERDES
for your LVDS transmitter using a dedicated SERDES block, you do not have the
option to use an external PLL.
The Cyclone series of devices (Cyclone III, Cyclone II, and Cyclone devices) do not
have a dedicated SERDES block available for use by your LVDS transmitter.
Therefore, you do not have the option to use a dedicated SERDES block in these
devices.
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After you select Use External PLL and do not select Implement
Serializer/Deserializer circuitry in logic cells on page 3 of the MegaWizard Plug-In
Manager, and click Next, the Transmitter settings page appears. If you choose to use
an external PLL, this page appears only if you choose to implement SERDES in a
dedicated SERDES block.
This page is the same as the Transmitter settings page that appears when you choose
to use an internal PLL, except the options to create tx_locked and tx_coreclock
output ports are not available. The options that appear in the Transmitter settings
page are described in Table 23 on page 26.
LVDS Transmitter Using External PLL and SERDES in LEs
If you use an Arria GX, Stratix series, Cyclone series, HardCopy II, or
HardCopy Stratix device, clock your LVDS transmitter using an external PLL, and
implement the SERDES for the transmitter using logic cells, a notification window
pops up after you enter these settings on page 3 of the MegaWizard Plug-In Manager
(Figure 22).
Figure 23. MegaWizard Plug-In Manager Notification for SERDES in LEs (LVDS Transmitter)
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Table 24. ALTLVDS Receiver Settings Page Options and Descriptions (Page 3)
Option
Description
Comments
Implement Serializer/Deserializer
circuitry in logic cells
Page 4 of the MegaWizard Plug-In Manager is the Frequency/PLL settings page. This page
appears only if an internal PLL is used.
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Table 25 describes the options you have on page 4 to customize the frequency and PLL settings,
depending on the device and options you selected on previous pages. These options are different
than those described in Table 22 on page 24 for the LVDS transmitter.
Table 25. ALTLVDS Receiver Frequency and PLL Settings Options (Page 4)
Option
(Part 1 of 3)
Description
Comments
This value determines the allowed input
clock rate values.
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Table 25. ALTLVDS Receiver Frequency and PLL Settings Options (Page 4)
Option
Use pll_areset input port
(Part 2 of 3)
Description
This option gives you control over the
asynchronous reset port of the fast PLL
that is used with this function.
Comments
When the transmitter shares the PLL
with the receiver and the pll_areset
port is used, this port must be used in
both megafunction instantiations and the
two signals must be tied together in the
design file. If the pll_areset port is
used in one megafunction instance and
not the other, the PLLs are not shared,
and a warning appears during
compilation.
The PLL must be reset in order for the
output clock phase relationships to be
set correctly when the PLL loses lock or
if the PLL input reference clock is not
stable when the device completes the
configuration process.
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Table 25. ALTLVDS Receiver Frequency and PLL Settings Options (Page 4)
Option
(Part 3 of 3)
Description
Comments
If the DPA mode is enabled, the DPA settings 1 and DPA settings 2 pages appear. The
DPA mode is supported by Arria GX, Stratix IV, Stratix III, Stratix II, Stratix II GX,
Stratix GX, and HardCopy II devices only.
The options on the DPA settings 1 page are described in Table 26.
Table 26. ALTLVDS Receiver DPA Settings 1 Page Options and Descriptions (Page 5) (Part 1 of 2)
Option
Description
Comments
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Table 26. ALTLVDS Receiver DPA Settings 1 Page Options and Descriptions (Page 5) (Part 2 of 2)
Option
Description
Comments
The options on the DPA Settings 2 page are described in Table 27.
Description
Comments
The DPA circuit must be retrained
after it is reset using this port.
After power up or reset, the
rx_dpa_locked signal is asserted
This option selects the initial phase setting. This option is available for Stratix IV
and Stratix III devices only.
Specify whether to enable this option and
its value. Simulation honors this phase
selection in simulating the forwarded clock.
For more information about the DPA receiver circuit, refer to the AN 236: Using
Source-Synchronous Signaling with DPA in Stratix GX Devices.
The options on the Receiver settings page are described in Table 28.
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Table 28. ALTLVDS Receiver Settings Page Options and Descriptions (Page 7) (Part 1 of 2)
Parameter
Description
Comments
Register outputs
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Table 28. ALTLVDS Receiver Settings Page Options and Descriptions (Page 7) (Part 2 of 2)
Parameter
Description
Comments
For more information about external PLL, refer to AN 409: Design Example Using the
ALTLVDS Megafunction & the External PLL Option in Stratix II Devices.
LVDS Receiver Using External PLL and Dedicated SERDES Block
The ability to use a dedicated SERDES block in your LVDS receiver and to clock the
transmitter using an external PLL is device-dependent, just as it is for an LVDS
transmitter.
If you use a Stratix IV or a Stratix III device, clock your LVDS receiver using an
external PLL, and implement the SERDES for the receiver using a dedicated SERDES
block, a notification window pops up after you enter these settings on page 3 of the
MegaWizard Plug-In Manager Figure 24).
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Figure 24. MegaWizard Plug-In Manager Notification for Stratix III Device (LVDS Receiver)
If you use an Arria GX, Stratix II, Stratix II GX, or HardCopy II device, clock your
LVDS receiver using an external PLL, and implement the SERDES for the receiver
using a dedicated SERDES block, a different notification window pops up after you
enter these settings on page 3 of the MegaWizard Plug-In Manager (Figure 25).
Figure 25. MegaWizard Plug-In Manager Notification for Other Devices (LVDS Receiver)
In Stratix, Stratix GX, and HardCopy Stratix devices, if you implement the SERDES
for your LVDS receiver using a dedicated SERDES block, you do not have the option
to use an external PLL.
The Cyclone series of devices (Cyclone III, Cyclone II, and Cyclone devices) do not
have a dedicated SERDES block available for use by your LVDS receiver. Therefore,
you do not have the option to use a dedicated SERDES block in these devices.
After you select Use External PLL and do not select Implement
Serializer/Deserializer circuitry in logic cells on page 3 of the MegaWizard Plug-In
Manager, and then click Next, the DPA settings 1 page or the Receiver settings page
appears.
This page is the same as the Receiver settings page that appears when you choose to
use an internal PLL, except different options are disabled. The options that appear in
the Receiver settings page are described in Table 28 on page 215.
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The Receiver settings page appears with only the Use rx_data_align input port
option available.
For more information about the ports and parameters for the ALTLVDS
megafunction, refer to Chapter 3, Specifications.
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A sample instantiation template for the language of the variation file (_inst.v,
_inst.vhd, or _inst.tdf)
Component Declaration File (.cmp) that can be used in VHDL Design Files
ADHL Include File (.inc) that can be used in Text Design Files (.tdf)
Quartus II Block Symbol File (.bsf) that can be used in schematic designs
Verilog HDL module declaration file that can be used when instantiating the
megafunction as a black box in a third-party synthesis tool (_bb.v)
For more information about the wizard-generated files, refer to the Quartus II Help or
to the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.
For more information about using megafunctions in your third-party synthesis tool,
refer to the appropriate chapter in the Synthesis section in volume 1 of the Quartus II
Handbook.
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Altera strongly recommends that you use the MegaWizard Plug-In Manager for
complex megafunctions. The MegaWizard Plug-In Manager ensures that you set all
megafunction parameters properly.
Refer to Chapter 3, Specifications for a list of the megafunction ports and parameters.
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Example 21 contains the VHDL code from a Stratix LVDS receiver. This template can
be used for any VHDL ALTLVDS function. Substitute appropriate ports and
parameters as needed in your design.
Example 21. VHDL Code from the Stratix LVDS Receiver
INCLUDE "altlvds_rx.inc";
SUBDESIGN stratix_rx
(
rx_in[0..0] : INPUT;
rx_inclock : INPUT = GND;
rx_pll_enable : INPUT = VCC;
rx_data_align : INPUT;
pll_areset : INPUT = GND;
rx_out[3..0] : OUTPUT;
rx_locked : OUTPUT;
rx_outclock : OUTPUT;
)
VARIABLE
ALTLVDS_rx_component : altlvds_rx WITH (
INTENDED_DEVICE_FAMILY = "Stratix",
NUMBER_OF_CHANNELS = 1,
DESERIALIZATION_FACTOR = 4,
LPM_TYPE = "altlvds_rx",
COMMON_RX_TX_PLL = "ON",
OUTCLOCK_RESOURCE = "AUTO",
INCLOCK_PERIOD = 9523,
INPUT_DATA_RATE = 840,
INCLOCK_DATA_ALIGNMENT = "EDGE_ALIGNED",
REGISTERED_OUTPUT = "ON",
REGISTERED_DATA_ALIGN_INPUT = "ON"
);
BEGIN
rx_locked = altlvds_rx_component.rx_locked;
rx_out[3..0] = altlvds_rx_component.rx_out[3..0];
rx_outclock = altlvds_rx_component.rx_outclock;
altlvds_rx_component.pll_areset = pll_areset;
altlvds_rx_component.rx_inclock = rx_inclock;
altlvds_rx_component.rx_in[0..0] = rx_in[0..0];
altlvds_rx_component.rx_data_align = rx_data_align;
altlvds_rx_component.rx_pll_enable = rx_pll_enable;
END;
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You can use the project hierarchy to find megafunction instantiations in the Floorplan
Editor. Right-click on the megafunction you want to view, and choose the Quartus II
editor in which you want to view it (Figure 28).
Figure 28. Compilation Hierarchy Navigation Option
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You can also locate your megafunctions in the Node Finder when making
assignments in the assignment editor. Figure 29 shows an example of how the
megafunction logic is shown in the Node Finder.
Figure 29. Node Finder View of ALTLVDS Transmitter Megafunction
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Design Files
The design files are available with this user guide in the Quartus II Project section and
in the User Guides section of the Altera website (www.altera.com).
In this example, you create two files using the MegaWizard Plug-In Manager: one for
an ALTLVDS receiver and one for an ALTLVDS transmitter. Both files are created in
Verilog HDL (.vhd) and are included in your project directory when completed.
Example
In this example, you will complete the following tasks:
Implement the receiver and transmitter functions in the device by adding your
custom megafunctions to the project and compiling the project
Simulate the high-speed differential interface design using the ModelSim -Altera
software
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(Part 1 of 2)
Value
Megafunction
Device family
Stratix II
Verilog HDL
stratixii_rx
Selected
Stratix II
Match project/default
Selected
LVDS receiver
Not selected
Selected
Not selected
Clock frequency
Clock frequency
500 MHz
Selected
Selected
Not selected
Auto selection
Selected
Selected
Selected
Selected
Selected
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(Part 2 of 2)
Value
Register outputs
Selected
Selected
Selected
Selected
Generate netlist
Not selected
Selected
Selected
Selected
Selected
Selected
Selected
Selected
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(Part 1 of 2)
Value
Megafunction
Device family
Stratix II
Verilog HDL
stratixii_tx
Not selected
Stratix II
Match project/default
Selected
LVDS transmitter
Not selected
Not selected
226
(Part 2 of 2)
Value
Clock frequency
Clock frequency
500 MHz
Selected
Selected
(The PLL must be reset in order for the
output clock phase relationships to be
set correctly when the PLL loses lock or
if the PLL input reference clock is not
stable when the device completes the
configuration process.)
Selected
tx_coreclock
Selected
Selected
Selected
Auto selection
Generate netlist
Not selected
Selected
Selected
Selected
Selected
Selected
Selected
Selected
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16. Choose stratixii_rx from the Project library list and click OK (Figure 210). You
may have to expand the Project folder to see the megafunctions it contains.
Figure 210. Design Example 1 Symbol View of stratixii_rx
17. Place the stratixii_rx symbol in the altlvds_stratixII block editor design file under
the text INSERT STRATIXII_RX HERE and align the input and output ports with
the signals already present in the design file.
The block diagram file should look similar to Figure 210.
Figure 211. Design Example 1 Top-Level Block Design File
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This waveform file contains only the input and output pins that are shown. You can
add internal post-compilation nodes with the Node Finder to view all of the data
paths in the design. You can verify that tx_outclock has a 4-ns period, which
corresponds to a 250-MHz clock rate, as specified in the design.
The input serial data rx_in is edge-aligned to the reference clock clk_in_500MHz,
and the output serial data tx_out is edge-aligned to tx_outclock as specified in
the transmitter megafunction.
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This simulation output verifies that 1-Gbps data can be successfully received by and
transmitted from the Stratix II device.
You can change the input vectors in the waveform editor to experiment with the other
features, such as data alignment, to view the functionality and help you understand
the ALTLVDS megafunction.
For PLL-specific information and for examples of PLL clock relationships, refer to the
ALTPLL Megafunction Users Guide.
You can use the external PLL option in ALTLVDS to give you direct access to all of the
PLL clocks that are not accessible when you allow ALTLVDS to infer the PLL for you.
This option gives you the ability to use the PLL output clocks throughout your design
for other functions besides the serialization and deserialization of data.
Design Files
The design files are available with this user guide in the Quartus II Project section and
in the User Guides section of the Altera website (www.altera.com).
In this example, you create two files using the MegaWizard Plug-In Manager: one for
an ALTLVDS receiver and one for an ALTLVDS transmitter. Both files are created in
VHDL (.vhd) and are included in your project directory when completed. The PLL
block is already customized in the design.
Example
This example shows how to design a 600 Mbps receiver with a deserialization factor
of 8 and a 600 Mbps transmitter with the same deserialization factor of 8. The input
reference clock frequency is 75 MHz.
In this example, you will perform the following activities:
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View description of the external PLL settings used to clock the transmitter and
receiver blocks.
Implement the receiver, transmitter, and PLL in the device by adding your custom
megafunctions to the project and compiling the project.
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230
Value
Megafunction
Device family
Cyclone II
VHDL
rx_block
Selected
Cyclone II
Selected
LVDS receiver
Selected
Selected
(The PLL must be reset in order for the
output clock phase relationships to be
set correctly when the PLL loses lock
or if the PLL input reference clock is
not stable when the device completes
the configuration process)
Not selected
Generate netlist
Not selected
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Table 211. Configuration Settings for Design Example 2 (LVDS Receiver) (Part 2 of 2)
MegaWizard Plug-In Manager
Page
6
Value
Selected
Selected
Selected
Selected
Selected
Selected
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(Part 1 of 2)
Value
Megafunction
Device family
Cyclone II
VHDL
tx_block
Not selected
Cyclone II
Match project/default
Selected
LVDS transmitter
Selected
Number of channels
Deserialization factor
Selected
(The PLL must be reset in order for the
output clock phase relationships to be set
correctly when the PLL loses lock or if the
PLL input reference clock is not stable
when the device completes the
configuration process.)
Generate netlist
Not selected
232
(Part 2 of 2)
Value
Selected
Selected
Selected
Selected
Selected
Selected
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5. Place the rx_block symbol in the block editor design file under the text Place
rx_block here and align the input and output ports with the signals already
present in the design file.
The rest of the components for this design are already in the top-level file. They
include two instantiations of DFF and one instantiation of ALTPLL named lvds_pll
in this example. After you place the rx_block and tx_block, the top level should
look like Figure 214.
Figure 214. Design Example 2 Top-Level Block Design File
If you do not want to create the rx_block and tx_block, they are located in the
backup folder within the project directory. You can move them to the top-level
directory and insert them directly into the top-level design.
For details about PLL compensation modes, refer to the PLL chapter of the relevant
device handbook.
The LVDS receiver and transmitter in this design example operate at a 600 Mbps data
rate with deserialization and serialization factors of 8. The reference clock frequency is
equal to the data rate divided by the deserialization factor, which is 75 MHz.
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234
Cyclone and Cyclone II devices use DDIO registers as part of the SERDES interface.
Because the data is clocked on both the rising and falling edge, the clock frequency
must be half the data rate; therefore, the fast clock from the PLL runs at half the data
rate. The core clock frequency (also referred to as the slow clock) is the data rate
divided by the serialization factor (J). In this example, the slow clock is the same
frequency as the reference clock, but is phase-aligned to the fast clock from the PLL.
The PLL in this design example is in the Source-Synchronous Compensation mode,
using the following selections for the megafunction.
Turn on ports for the asynchronous reset function and locked output.
C0 is the high speed clock. The data rate for this design example is 600 Mbps. The C0
signal must have a frequency of one half the data rate, so the output frequency must
be set to 300 MHz. The phase you select depends on the reference clock to data
relationship at the pins of the device. The Source-Synchronous Compensation mode
maintains the clock to data relationship to the I/O element capture registers on the
receiver.
In this design example, the reference clock and data are rising edge aligned (the bit
boundary is synchronous to the rising edge of the reference clock, and 8 bits are
received in every clock period). The C0 must be phase-shifted to properly capture the
data internally at the registers.
For edge-aligned interfaces, you would normally phase-shift your high speed clock
by 180 to center-align the clock and data relationship at the capture register.
However, because Cyclone and Cyclone II devices use a half-rate high-speed clock,
due to the DDIO implementation, a 180 phase-shift would simply switch the rising
edge with the falling edge. To move the capture clock with respect to the DDIO data, a
90 phase shift is required.
C1 is the low speed clock. For even SERDES factors, it must be the data rate divided
by the SERDES factor (J). In this example, the C1 is 75 MHz (600 Mbps / 8). The
phase-shift on the C1 must correspond to the phase-shift on the C0. The data is
edge-aligned with respect to the reference clock at the input pins, so the clocks have to
phase-shift to center-align the rising edge in the core. The high speed to low speed
data transfer does not use the DDIO circuitry, so you can calculate 180 / J to
determine the correct phase shift for this clock to achieve the desired data alignment.
In this example, the result is 22.5, which you use for the C1 phase-shift.
The receiver and transmitter use the same PLL in this example. The phase shifts are
optimized to capture data at the receiver, but they also determine a fixed relationship
of clock and data at the transmitter. If the slow clock is forwarded with the transmit
data, it is center-aligned. If a different clock frequency and phase are desired, you can
enable the C2 output port of the PLL (in Cyclone devices, the third port of the PLL is
E0). The frequency and phase are restricted to the possibilities available for the
ALTPLL megafunction parameters.
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The receiver channels bring the serial data in to the device, edge-aligned with the
reference clock (ref_clock). The rx_in0 receives a data value of 1, the rx_in1
receives a data value of 2, rx_in2 receives a data value of 3, and the rx_in3 receives
a data value of 4. You can expand the parallel receiver channels (rx_parallel_out)
in the waveform editor to see the word alignment position. The parallel data is shifted
two bits toward the MSB in each channel.
The transmitter channel sends data from the device center aligned with the
slow_clock output pin. The tx_out0 transmits a data value of 1, the tx_out1
transmits a data value of 2, the tx_out2 transmits a data value of 3, and the tx_out3
transmits a data value of 4. Depending on your system requirements, you can add the
remaining output clock port of the PLL and forward a clock that is aligned differently
with respect to the data. The timing simulation shows the transmitted data is three bit
positions shifted toward the MSB with respect to the slow_clock.
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238
Select the folder in which you unzipped the files. Click OK.
On the Tools menu, point to TCL and click Execute Macro. The Execute Do File
dialog box appears.
Select the altlvds_ex2_msim.do file and click Open. This is a script file for the
ModelSim software that automates all the necessary settings for the simulation.
You can rearrange signals, remove signals, add signals, and change the radix by
modifying the script in altlvds_ex2_msim.do. Figure 217 shows the expected
simulation results in the ModelSim simulator.
Figure 217. Design Example 2 ModelSim Simulation Results
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Design Files
The design files are available with this user guide in the Quartus II Project section and
in the User Guides section of the Altera website (www.altera.com).
In this example, you create two files using the MegaWizard Plug-In Manager: one for
an ALTLVDS receiver and one for an ALTLVDS transmitter. Both files are created in
Verilog HDL (.v) and are included in your project directory when completed.
Example
In this example, you will complete the following tasks:
Implement the receiver and transmitter functions in the device by adding your
custom megafunctions to the project and compiling the project.
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(Part 1 of 2)
Value
Megafunction
Device family
Stratix III
Verilog HDL
rx_block
Selected
240
(Part 2 of 2)
Value
Stratix III
Match project/default
Selected
LVDS receiver
Not selected
Selected
10
Not selected
Clock frequency
Clock frequency
50 MHz
7
8
9
Not selected
Not available
Selected
Auto selection
Selected
0 PPM
Not available
Not selected
Not available
Not selected
Not selected
Not selected
Not selected
Register outputs
Selected
Not selected
Generate netlist
Not selected
Selected
Selected
Selected
Selected
Selected
Selected
Selected
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Value
Megafunction
Device family
Stratix III
Verilog HDL
tx_block
Not selected
Stratix III
Match project/default
Selected
LVDS transmitter
Not selected
Not available
10
Not selected
Clock frequency
Clock frequency
50 MHz
Not available
Not selected
Selected
Not selected
tx_coreclock
Not selected
Selected
Not selected
Generate netlist
Not selected
242
Table 214. Configuration Settings for Design Example 3 (LVDS Transmitter) (Part 2 of 2)
MegaWizard Plug-In Manager
Configuration Setting
Value
Selected
Selected
Selected
Selected
Selected
Selected
Selected
16. On the Processing menu, click Compilation Report to view the resource usage of
this design.
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4. Select the folder in which you unzipped the files. Click OK.
5. On the Tools menu, point to TCL and click Execute Macro. The Execute Do File
dialog box appears.
6. Select the altlvds_ex3_msim.do file and click Open. This is a script file for the
ModelSim software that automates all the necessary settings for the simulation.
7. Verify the results shown in the Waveform Viewer window.
You can rearrange signals, remove signals, add signals, and change the radix by
modifying the script in altlvds_ex1_msim.do. Figure 219 shows the expected
simulation results in the ModelSim simulator.
Figure 219. Design Example 3 ModelSim Simulation Results
This waveform file contains only the input and output pins that are shown. You can
add internal post-compilation nodes with the Node Finder to view all of the data
paths in the design, including the soft-CDR data path.
This simulation output confirms that 1-Gbps data can be successfully received using
the recovered clock from the soft CDR and then transmitted from the Stratix III
device. You can observe this by comparing the values on text_rx_in and
text_tx_out ports.
Conclusion
The Quartus II software provides parameterizable megafunctions ranging from
simple arithmetic units, such as adders and counters, to advanced PLL blocks,
multipliers, and memory structures. These megafunctions are performance-optimized
for Altera devices and therefore provide more efficient logic synthesis and device
implementation, because they automate the coding process and save valuable design
time. Altera recommends using these functions during design implementation so you
can consistently meet your design goals.
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3. Specifications
For the most current information on the ports and parameters for this megafunction,
refer to the latest version of the Quartus II Help.
Table 31 shows the transmitter input ports, Table 32 shows the transmitter output
ports, and Table 33 shows the transmitter parameters. Table 34 shows the receiver
input ports, Table 35 shows the receiver output ports, and Table 36 shows the
receiver parameters.
Optional clock for the input registers. This port is available for
APEX 20KE, APEX 20KC, Mercury , and APEX II devices only.
tx_in[]
Yes
Input port
[DESERIALIZATION_FACTOR NUMBER_OF_CHANN
ELS 1..0] wide. This is parallel data that is serially
transmitted by the megafunction.
Port Name
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Cyclone
Stratix GX
No
Stratix
sync_inclock
Required
Description
32
Chapter 3: Specifications
Ports and Parameters
Port Name
Cyclone
Stratix GX
Stratix
Required
Description
tx_inclock
Yes
tx_pll_enable
No
Enable control for the LVDS PLL. Not available in Cyclone III
device.
pll_areset
No
tx_enable
No
tx_syncclock
No
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Chapter 3: Specifications
Ports and Parameters
33
Port Name
Cyclone
Stratix GX
Stratix
Required
Description
tx_out[]
Yes
tx_outclock
No
tx_coreclock
No
1. When outclock_divide_by = 1 or
2. when outclock_divide_by =
DESERIALIZATION_FACTOR (for odd factors only)
and outclock_duty_cycle is 50.
tx_locked
No
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Altera Corporation
Gives the status of the LVDS PLL. When the PLL is locked, this
signal is VCC. When the PLL fails to lock, this signal is GND.
34
Chapter 3: Specifications
Ports and Parameters
Parameter Name
Cyclone
Stratix GX
Stratix
Required
Description
INTENDED_DEVICE_FAMILY
Yes
NUMBER_OF_CHANNELS
Yes
DESERIALIZATION_FACTOR
Yes
Values
1, 2,3,4, 5, 6, 7, 8,
Stratix IV, Stratix III,
Stratix II, Stratix II GX, 9, 10
Cyclone III,
Cyclone II, Cyclone,
HardCopy II, and
APEX II
Stratix and Stratix GX
1, 2,3,4, 7, 8, 10
1,3, 4, 7, 8
Mercury
1, 2, 3,4, 7, 8, 9,
10, 11, 12, 14, 16,
18, 20
Yes
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Chapter 3: Specifications
Ports and Parameters
35
Parameter Name
USE_EXTERNAL_PLL
No
Cyclone
Stratix GX
Stratix
Required
Description
v
OUTCLOCK_DIVIDE_BY
No
CORECLOCK_DIVIDE_BY
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No
36
Chapter 3: Specifications
Ports and Parameters
Parameter Name
OUTCLOCK_ALIGNMENT
Yes
Cyclone
Stratix GX
Stratix
Required
Description
v
INCLOCK_PERIOD
Yes
OUTPUT_DATA_RATE
Yes
INCLOCK_DATA_ALIGNMENT
Yes
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Chapter 3: Specifications
Ports and Parameters
37
Parameter Name
REGISTERED_INPUT
No
Cyclone
Stratix GX
Stratix
Required
Description
v
COMMON_RX_TX_PLL
No
OUTCLOCK_RESOURCE
No
IMPLEMENT_IN_LES
No
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Chapter 3: Specifications
Ports and Parameters
Parameter Name
Cyclone
Stratix GX
Stratix
Required
Description
MULTI_CLOCK
No
INCLOCK_BOOST
No
CENTER_ALIGN_MSB
No
OUTCLOCK_DUTY_CYCLE
No
DESERIALIZATION_FACTOR value is 5,
7, or 9
OUTCLOCK_MULTIPLY_BY value is 2
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Chapter 3: Specifications
Ports and Parameters
39
Port Name
Cyclone
Stratix GX
Stratix
Required
Description
rx_in[]
Yes
Input port
[NUMBER_OF_CHANNELS 1..0]
wide. After deserialization, rx_out[n-1] is
the first bit received and rx_out[0] is the
last bit received for channel one; for channel
two, rx_out[2n-1] is the first bit received
and rx_out[n] is the last bit received.
rx_inclock
Yes
rx_pll_enable
No
rx_data_align
No
rx_channel_data_align[]
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Altera Corporation
No
Input port
[NUMBER_OF_CHANNELS 1..0]
wide. Controls byte alignment circuitry. A
pulse to this input causes the data alignment
circuitry to remove one bit of latency from the
serial data stream in Stratix GX devices, or
add one bit of latency into the serial data
stream for Stratix IV, Stratix III, Stratix II, and
Stratix II GX devices. You can register this
port using the rx_outclock port. For
Stratix GX devices, this port is available in
DPA mode.
310
Chapter 3: Specifications
Ports and Parameters
Port Name
Cyclone
Stratix GX
Stratix
Required
Description
rx_dpll_enable[] (1)
No
Input port
[NUMBER_OF_CHANNELS 1..0]
wide. Enables the path through DPA circuitry.
rx_dpll_hold[] (1)
No
Input port
[NUMBER_OF_CHANNELS 1..0]
wide. Prevents the DPA from switching to a
new phase.
rx_reset[] (1)
No
Input port
[NUMBER_OF_CHANNELS 1..0]
wide. Synchronizes all channels and resets
the DPA circuitry. This port must be
connected if the ENABLE_DPA_MODE
parameter is turned on in Stratix GX.
rx_dpll_reset[] (1)
No
Input port
[NUMBER_OF_CHANNELS - 1..0]
wide. Asynchronous reset for all channels.
rx_fifo_reset[] (1)
No
Input port
[NUMBER_OF_CHANNELS - 1..0]
wide. Resets the FIFO between DPA and data
alignment circuits.
rx_cda_reset[]
No
Input port
[NUMBER_OF_CHANNELS - 1..0]
wide. Resets the data alignment circuitry.
rx_coreclk[] (1)
No
Input port
[NUMBER_OF_CHANNELS - 1..0]
wide. LVDS reference input clock used to
synchronize the output of the receiver to a
clock used in the core. One clock is used for
each channel.
pll_areset
No
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Chapter 3: Specifications
Ports and Parameters
311
Port Name
Cyclone
Stratix GX
Stratix
Required
Description
rx_enable
No
rx_deskew
No
rx_data_align_reset
No
rx_syncclock
No
Port Name
Cyclone
Stratix GX
Stratix
Required
Description
rx_out[]
Yes
Output port
[DESERIALIZATION_FACTOR NUMBER_OF_CH
ANNELS - 1..0] wide. Deserialized data signal.
rx_outclock
No
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Chapter 3: Specifications
Ports and Parameters
Port Name
Cyclone
Stratix GX
Stratix
Required
Description
rx_locked
No
rx_dpa_locked[]
No
rx_cda_max[]
No
rx_divfwdclk[]
No
Recovered clock output from the DPA block and sent to the
core via the PCLK network. The DPA output clock selected
by the DPA block is divided by the deserialization factor.
This divided clock is the recovered clock.
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Chapter 3: Specifications
Ports and Parameters
313
Parameter Name
Cyclone
Stratix GX
Stratix
Required
Description
INTENDED_DEVICE_FAMILY
Yes
NUMBER_OF_CHANNELS
Yes
DESERIALIZATION_FACTOR
Yes
ENABLE_DPA_MODE
No
USE_EXTERNAL_PLL
No
COMMON_RX_TX_PLL
No
OUTCLOCK_RESOURCE
No
INCLOCK_PERIOD
Yes
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Chapter 3: Specifications
Ports and Parameters
Parameter Name
Cyclone
Stratix GX
Stratix
Required
Description
INPUT_DATA_RATE
Yes
INCLOCK_DATA_ALIGNMENT
Yes
(1)
ENABLE_DPA_FIFO
No
v
(2)
USE_CORECLOCK_INPUT
No
v
(2)
RESET_FIFO_AT_FIRST_LOCK
No
LOSE_LOCK_ON_ONE_CHANGE
No
REGISTERED_OUTPUT
No
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Chapter 3: Specifications
Ports and Parameters
315
REGISTERED_DATA_ALIGN_
INPUT
No
DATA_ALIGN_ROLLOVER
No
Cyclone
Parameter Name
Stratix GX
Stratix
Required
Description
(1)
No
CDS_MODE
No
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Chapter 3: Specifications
Ports and Parameters
BUFFER_IMPLEMENTATION
No
Parameter Name
Cyclone
Stratix GX
No
Stratix
IMPLEMENT_IN_LES
Required
Description
BUFFER_IMPLEMENTATION applies
only to Cyclone III, Cyclone II, and Cyclone,
and Stratix IV, Stratix III, Stratix II, and
Stratix (LE implementations only for Stratix
series) for Odd deserialization factors.
To use the BUFFER_IMPLEMENTATION
parameter, the IMPLEMENT_IN_LES
parameter must be turned on. Also, the
BUFFER_IMPLEMENTATION parameter can
be used with deserialization factors of 5, 7,
or 9 only.
Values are:
Parameter Value: MUX
Description: Uses mux implementation
instead of buffer implementation.
Parameter Value: RAM
Description: Buffer is implemented in RAM
blocks.
Parameter Value: LES
Description: Buffer is implemented in logic
elements.
If omitted, the default value is RAM.
ENABLE_SOFT_CDR
No
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Chapter 3: Specifications
Ports and Parameters
317
Parameter Name
Cyclone
Stratix GX
Stratix
Required
Description
IS_NEGATIVE_PPM_DRIFT
No
NET_PPM_VARIATION
No
ENABLE_DPA_INITIAL_PHASE
_SELECTION
No
DPA_INITIAL_PHASE_
VALUE
No
ENABLE_DPA_ALIGN_TO_
RISING_EDGE_ONLY
No
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Chapter 3: Specifications
Ports and Parameters
Parameter Name
PLL_OPERATION_MODE
No
Cyclone
Stratix GX
Stratix
Required
Description
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Chapter 3: Specifications
Ports and Parameters
319
Parameter Name
USE_NO_PHASE_SHIFT
No
Cyclone
Stratix GX
Stratix
Required
Description
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Chapter 3: Specifications
Ports and Parameters
180
Reference Edge
tx_inclock
tx_outclock
tx_outclock
tx_outclock
180
Input Clock
Edge Aligned
45 Phase
180o Phase
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Altera Corporation
Additional Information
UG-MF9504-4.0
Revision History
The following table shows the revision history for this user guide.
Date
Version
December 2008
v4.0
Changes Made
Updated for the Quartus II software 8.1:
Removed figures.
Updated Table 21, Table 22, Table 23, Table 24, Table 25, Table 27, Table 29,
Table 211, Table 212, Table 31, Table 32, Table 33,Table 34, and Table 36.
Added Enable bitslip control, Enable independent bitslip controls for each channel, and
Register the bitslip control input using 'rx_outclock' parameters and descriptions to
Table 28
May 2008
v3.4
November 2007
v3.3
March 2007
v3.2
December 2006
v3.1
November 2006
v3.0
June 2006
v2.0
August 2005
v1.1
December 2004
v1.0
Initial release.
December 2008
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About2
Referenced Documents
Referenced Documents
This user guide references the following documents:
AN 409: Design Example Using the ALTLVDS Megafunction & the External PLL Option
in Stratix II Devices
Clock Networks and PLLs in Stratix III Devices chapter in volume 1 of the Stratix III
Device Handbook
Contact
Method
Address
Technical support
Website
www.altera.com/support
Technical training
Website
www.altera.com/training
custrain@altera.com
literature@altera.com
nacomp@altera.com
(Software Licensing)
authorization@altera.com
Note:
(1) You can also contact your local Altera sales office or sales representative.
Typographic Conventions
The following table shows the typographic conventions that this document uses.
Visual Cue
Meaning
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names, file
names, file name extensions, and software utility names are shown in bold type.
Examples: fMAX , \qdesigns directory, d: drive, chiptrip.gdf file.
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
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About3
Typographic Conventions
Visual Cue
Italic type
Meaning
Internal timing parameters and variables are shown in italic type.
Examples: tPIA , n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
Subheading Title
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: Typographic Conventions.
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1 , tdi ,
input. Active-low signals are denoted by suffix n , e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file,
such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN ), as well as logic function names (e.g., TRI ) are shown in Courier.
Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.
Bullets are used in a list of items when the sequence of the items is not important.
A warning calls attention to a condition or possible situation that can cause injury to
the user.
The angled arrow indicates you should press the Enter key.
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