ASSIGNMENT 2:EE 705- VLSI DESIGN LAB

DESIGN OF 8-bit ALU

INDRANIL CHAKRABORTY

ROLL - 143070072

ELECTRICAL ENGINEERING
MICROELECTRONICS

DATE 30th January, 2015

IIT BOMBAY

DESIGN OF A 8-BIT ALU

FUNCTION: The ALU decodes a 2-bit op-code to decide the function to be performed on its two
inputs X and Y to produce Z.
BLOCK DIAGRAM:

x0-x7
8-bit ALU

y0-y7

z0-z7

Op_code0-Op_code7

DESCRIPTION:

The Alu8 computes Z as a function of X and Y. The following functions are to be supported:
Op_code
00
01
10
11

Operation
Z=(X+Y)
Z=(X-Y)
Z=(X>>Y)
Z=(X<<Y)

Remark
Addition
Subtraction
Logical Right Shift
Logical Left Shift

DATA FILE GENERATION:

We have written a C++ implementation of the ALU to generate a test file for our testbench. The
organization of the test data file is as follows:
Opcode

And for each opcode there are 65536 entries of X and Y because X and Y are 8-bit vectors.
There are 4 combinations for opcode. So, total number of entries in the data file is
65536*4=262144.
Note: Logical shifts more than 16-bit are not allowed in C++. So, a function has been defined to
implement more than 16-bit shift.

SAMPLE C++ PROGRAM:

#include<iostream>
#include<string>
#include<bitset>
#include<fstream>
using namespace std;
int lsr(int ar,int n) //Logical Right Shift function
{
for(int i=0;i<n;i++)
{
ar=ar>>1;
}
return ar;
}
int lsl(int ar,int n) //Logical Left Shift function
{
for(int i=0;i<n;i++)
{
ar=ar<<1;
}
return ar;
}

int main()
{
int x,y,z,op;
string xs,ys,zs,ops;
ofstream outputFile;
outputFile.open("data.txt"); //Open File Command

for(op=0;op<4;op++)
{
for (x=0;x<256;x++)
{
for(y=0;y<256;y++)
{
xs = std::bitset<8>(x).to_string(); //function converts an integer to a
binary string
ys = std::bitset< 8 >(y).to_string();
ops = std::bitset<2>(op).to_string();

if(ops=="00")
{
z=x+y;
zs=std::bitset<8>(z).to_string();
}
else if(ops=="01")
{
z=x-y;
zs=std::bitset<8>(z).to_string();
}
else if(ops=="10")
{
z=lsr(x,y);
zs=std::bitset<8>(z).to_string();
}
else if(ops=="11")
{
z=lsl(x,y);
zs=std::bitset<8>(z).to_string();
}
outputFile<<ops<<" "<<xs<<" "<<ys<<" "<<zs<<endl; //Output
}
}
}
outputFile.close();
}

VHDL ORGANIZATION OF DUT

Entity: An entity is defined specifying the input and output ports.
entity Alu8 is
port (X,Y: in bit_vector(7 downto 0); Z: out bit_vector(7 downto
0); op_code: in bit_vector(1 downto 0));
end entity;
Architecture and Process: The Architecture is designed using a Process statement which has a
sensitivity list consisting of vectors X and Y. That is the process statement is processed
whenever there is an event on X or Y.
For arithmetic operations, we convert bit_vector type X and Y into
unsigned using:
xu := unsigned(X);
yu := unsigned(Y);
The opcode decides which operation should be performed on X For example, when opcode is
'00', addition is performed:

if(op_code = "00") then

zu := xu+yu;

After arithmetic operations, unsigned 'zu' is converted to bit_vector and assigned to output signal
'Z'.
Z <= bit_vector(zu);
VHDL CODE:
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;
use std.textio.all;
entity Alu8 is
port (X,Y: in bit_vector(7 downto 0); Z: out bit_vector(7 downto 0);
op_code: in bit_vector(1 downto 0)); --Entity definition
end entity;
Architecture AluBehave of Alu8 is
begin
Process(X,Y)
variable xu,yu,zu:unsigned(7 downto 0); --Unsigned variables definition
variable yn:natural;
begin
xu := unsigned(X);
yu := unsigned(Y);
if(op_code = "00") then
--Addition
zu := xu+yu;
elsif(op_code = "01") then --Subtraction
zu := xu-yu;
elsif(op_code = "10") then Logical Right Shift
yn:=to_integer(yu);
zu:=SHIFT_RIGHT(xu,yn);
elsif(op_code = "11") then --Logical Left Shift
yn:=to_integer(yu);
zu:=SHIFT_LEFT(xu,yn);
end if;
Z <= bit_vector(zu);
--Unsigned to Bit Vector assignment
end process;
end AluBehave;

VHDL ORGANIZATION OF TESTBENCH

Entity and Architecture: An entity for the testbench is defined. The Architecture specifies the
signals of the testbench and defines the DUT component.
entity TestALU is
end entity;
architecture Behave of TestALU is
signal x,y,z: bit_vector(7 downto 0):="00000000";
signal op_code: bit_vector(1 downto 0) := "00";
component ALU8
port (X,Y: in bit_vector(7 downto 0); Z: out bit_vector(7 downto
0); op_code: in bit_vector(1 downto 0));
end component;

Process:We define the required variables in order to read from the data file and to display
output. We used the text.stdio library to read from the data file:
file_open(file_pointer,"data.txt",READ_MODE);
while not endfile(file_pointer) loop

readline (file_pointer,line_num);
READ (line_num,op_code_file);
READ (line_num,x_file);
READ (line_num,y_file);
READ (line_num,z_file);
Thus x_file,y_file,z_file and op_code_file now stores the values of x, y, z and op_code
according to the data file generated earlier.
We assert the original output z against the z_file obtained from test data file:
assert(z=z_file)
report "Error in output" severity error;
We also set counters to count the number of errors in each operation, and our testbench displays
the number of success and failure for each operation, and also the total errors.

VHDL CODE FOR TESTBENCH:

library IEEE;
use IEEE.numeric_bit.all;
use std.textio.all;
entity TestALU is
end entity;
architecture Behave of TestALU is
signal x,y,z: bit_vector(7 downto 0):="00000000"; --Signal definition
signal op_code: bit_vector(1 downto 0) := "00";

--OpCode definition

component ALU8
port (X,Y: in bit_vector(7 downto 0); Z: out bit_vector(7 downto 0);
op_code: in bit_vector(1 downto 0)); --Component definition
end component;
begin
process
file file_pointer : text; --File Pointer
variable l_num:line;

--Line number

variable countadd,countsub,countsr,countsl:integer:=0; --Error Counter

definition
variable x_file,y_file,z_file:bit_vector(7 downto 0);
store input from file

--Variables to

variable xs,ys,zs:string(1 to 8);

Strings to display output

--

variable op_code_file:bit_vector(1 downto 0);

variable ops:string(1 to 2);
function Image(In_Image: Bit_vector) return String is
convert bit_vector to string

--funtion to

variable S:line;
variable Y: string(1 to In_image'length) := (others=> ' ');
begin
std.TextIO.WRITE(S, in_image);
Y(S.all'range) := S.all;
Deallocate(S);

return Y;
end Image;
begin
file_open(file_pointer,"data.txt",READ_MODE);
while not endfile(file_pointer) loop
end of file is reached

readline (file_pointer,line_num);
READ (line_num,op_code_file);
stored into variables

--Open file command

--Loop running until

--Reading line by line

--Input from file is

READ (line_num,x_file);
READ (line_num,y_file);
READ (line_num,z_file);
ops := Image(op_code_file);
from bit_vectors
xs

--Strings are created

:= Image(x_file);

ys := Image(y_file);
zs := Image(z_file);
op_code<=op_code_file;

--Inputs are assigned

X<=x_file;
Y<=y_file;

wait for 10 ns;

assert(z=z_file)
condition

--Waiting for output

--Assertion of output

report "Error in output" severity error;

if(not(z=z_file)) then
mismatches

--Check if output

if(op_code_file="00") then
specific error output

--Check opcode for

report "Operation: Addition. Input: X: " & xs & " Y: " & ys & "
Expected: " & zs & " Produced: " & Image(z);
--Error output
countadd:=countadd+1;

--Increment Counter

end if;
elsif(op_code_file="01") then

report "Operation: Subtraction. Input: X: " & xs & " Y: " & ys &
" Expected: " & zs & " Produced: " & Image(z);
countsub:=countsub+1;

end if;
elsif(op_code_file="10") then

report "Operation: Shift right. Input: X: " & xs & " Y: " & ys &
" Expected: " & zs & " Produced: " & Image(z);
countsr:=countsr+1;

end if;
elsif(op_code_file="11") then

report "Operation: Shift Left. Input: X: " & xs & " Y: " & ys & "
Expected: " & zs & " Produced: " & Image(z);
countsl:=countsl+1;

end if;
end if;
end loop;
file_close(file_pointer);

--File close command

if(countadd>0 or countsub>0 or countsr>0 or countsl>0) then --Total errors

display
report "Number of errors: " &
integer'image(countadd+countsub+countsr+countsl);
report "Addition: Success: " & integer'image(65536-countadd) & " Failure:
" & integer'image(countadd);

report "Subtraction Success: " & integer'image(65536-countsub) & "

Failure: " & integer'image(countsub);
report "Shift Right Success: 65536 " & integer'image(65536-countsr) & "
Failure: " & integer'image(countsr);
report "Shift Left Success: 65536 " & integer'image(65536-countsl) & "
Failure: " &integer'image(countsl);
else
report "Test passed successfully for all " & integer'image(65536*4) & "
combinations.";
end if;
wait;
end process;
dut: ALU8
port map(x => X,
y => Y,
op_code => op_code,
z => Z);

end Behave;

--Port Mapping

OUTPUT

Addition:

Subtraction:

Logical Right Shift

Logical Left Shift

Successful test output sample:

Unsuccessful test output sample:

a) Manual change in data file:

b) Z6 stuck at 1:

c) Z4 stuck at 0:

d) Addition and Subtraction opcodes interchanged: