Documente Academic
Documente Profesional
Documente Cultură
Yervant Zorian
Virage Logic
46501 Landing Parkway, Fremont, CA 94538, USA
zorian@viragelogic.com
Abstract:
Todays System-on-Chip typically embeds memory IP
cores with very large aggregate bit count per SoC. This
trend requires using dedicated resources to increase
memory yield, while containing test & repair cost and
minimizing time-to-volume. This paper summarizes the
evolution of such yield optimization resources, compares
their trade-offs, and concentrates on on-chip
Infrastructure IP. To maximize the repair efficiency, this
Infrastructure IP need to leverage the memory design
knowledge and the process failure data. The ideal solution
is to integrate the memory IP and its Infrastructure IP into
a single composite IP that yields itself effectively.
1. Introduction:
The growth in demand for System-on-Chips (SoCs) has
spurred a flood of better, faster, smaller chips. The
creation of such SoCs necessitates finer fabrication
processes and new material. One of the greatest obstacles
to the widespread adoption of SoCs based on such
processes is achieving adequate manufacturing yields.
Todays semiconductor fabrication processes are reaching
defect susceptibility levels that result in lowering SOC
yield and reliability, consequently lengthening production
ramp -up period, and therefore time-to-volume (TTV).
In order to optimize yield and reach acceptable TTV
levels, the semiconductor industry started adopting
advanced yield optimization solutions. These are solutions
that are implemented at the design stage and utilized at
different phases of the chip realization flow [17]. These
advanced yield optimization solutions necessitate
embedding a special type of IP blocks in a chip. Such IP
blocks are called Infrastructure-IP (I-IP) [18]. Unlike the
Functional-IP (F-IP) cores used in SoCs, such as
embedded processors, embedded memories, or embedded
FPGAs, the I-IP cores do not add to the main functionality
of the chip. Rather, they are intended to ensure the
manufacturability of the SoC and to achieve lifetime
reliability [19]. The industry in the recent past has
introduced a wide range of I-IP blocks. Examples of such
I-IP blocks are process monitoring IP [3], test & repair IP,
diagnosis IP [9], timing measurement IP [13], and fault
tolerance IP [4]. Embedding such blocks into the SoC
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20 %
80 %
52 %
71 %
83 %
90 %
94 %
16 %
100
64 %
60 %
24 Mb 32 Mb
90
32 %
20 %
13 %
9%
16 %
99
02
05*
Year
8%
08*
6%
4%
11*
4%
2%
14*
% Area Memory
80
16 %
40 %
70
60
Width of die in mm
12.00
Height of die in mm
12.00
0.4
0.8
50
40
30
20
10
0
11
22
43
% Memory on die
65
86
Process technology
0.13um
Memory
Tester
Embedded
Memory
Laser Fuses
Laser Repair
Embedded
Memory
Memory
Tester
Laser Fuses
Embedded
Memory
SoC
Logic
Tester
Packaging
Characterization
SoC Design
D Failure
Analysis
In-Field
Test
Assembling
Packaging
Production
Ramp Up
Volume
Fabrication
Detection
Analysis
Correction
Paper 12.1
343
STAR
Memory
STAR
Processor
Laser Fuses
STAR
Memory
Logic
Tester
Laser Repair
STAR
Processor
SoC
STAR
Memory
STAR
Processor
Logic
Tester
STAR
Memory
Laser Fuses
ASAP
Memory
STAR
Memory
Logic
Tester
NV Fuses
SoC
Packaging
Packaging
Fig. (5) I-IP for Single-Time Repair
In this method, the manufacturing cost is reduced, because
the need for external test & repair equipment and
resources of are less, compared to Fig. (3). On the other
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charge pump and its control, are considered a part of the IIP function.
The STAR Processor performs all the appropriate test &
repair coordination of a STAR memory. This Processor is
programmed by a set of instructions to control the
operation of the internal modules, as shown in Fig. (8).
The BIST module performs the tests using memory
specific test algorithms. The test algorithms may be preconfigured in the BIST module or made re-configurable
via microcode residing outside the processor, such as in a
non-volatile memory, named the NV Test Box. The BuiltIn Self-Diagnosis (BISD) module determines the location
of the memory defects (if any) and provides error logging
by scanning out failure data if required for failure analysis
during loop 2.
STAR Processor
Re-configurable Test
NV Test Box
BIST
BISD
BIRA
Built-in Redundancy
Allocation
Reconfig. Data
Generation
Reconfiguration Data
Repair
Signature
Fuse
Box
STAR
Mem.
STAR
Mem.
STAR
Mem.
IW
IW
IW
IW
STAR
Processor 1
Fuse Box
1149.1
P1500
P1500
STAR
Processor 2
STAR
Mem.
IW
Row
Decoder
Memory
Array
Control
Logic
Redundant Rows
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346
Redundancy
Logic
Test Modes
Failure Data
= defects
Repair &
Redundancy
Allocation
Memory
Address
Mapping
Repair
Signature
Knowledge Base
- Logical to physical
Hard Repair
Unrepaired
Available
Redundancy
Process Failure
History
Soft Repair
Powered up
Unrepaired
Repaired
Powered down
Reliability failures
Repaired
Combinational
Repair
Powered up
Hard failures
Repaired
Unrepaired
Powered down
Repaired
Cumulative
Repair Unrepaired
Progressively
Repaired
Progressively
Repaired
USER I/O
RSA
RSA
Redundancy MUXs
I/O
USER I/O
7. Conclusion
Producing SoCs requires embedded memory IPs
supported by I-IP to perform embedded test & repair and
diagnosis . This Infrastructure IP, as described in this
paper, can only reach adequate yield and reliability levels,
if it leverages the memory design information and the
process failure data. Thus the solution needed is a
composite IP that includes the memory F-IP and its test &
repair I-IP. Integrating this composite IP into the SoC
design requires adequate interoperability with the rest of
the functional and test infrastructure on-chip. The STAR
Processor solves the test in teroperability problem by
adopting the standard core test interface IEEE P1500
[5][16], similar to the adoption of IEEE P1500 by other
types of embedded cores [8].
References
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Improvement, Proc. Design Automation Conference (DAC
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