Single-Chip

3D Ultrasound Beamforming
1

Pascal Alexander Hager , Andrea Bartolini

1,2

, Luca Benini

1,2

Integrated Systems Laboratory (IIS), ETH Zrich

2
Electrical, Electronic, and Information Engineering (DEI), Universit di Bologna

1. Introduction

3. Our Solution

Project Goal: Development of a high-performance, low-power

signal processing platform for ultrasound imaging targeting future
3D portable ultrasound systems.

A. Highly-scaleable beamforming architecture [1,2]

Imaging
Volume

Transducer
Matrix

Analog Frontend

Beamformer Channel (BFC)

this work

Local Delay Index Calculation

ASIC
BF ASIC

Interpolation
Polyphase Filter

BFC
BFC

Modulation
LUT

Buer
1024x32bit

BFC

3D ultrasound systems can achieve ...

- volumetric measurements
- fast motion capture (e.g., of heat valves)
- separation of acquisition and interpretation
... but currently still use massive analog preprocessing, making
low-power, highly integrated portable devices impossible.
A fully-digital architecture promises more flexibility and higher
integration but needs to...
- employ massively parallel hardware (10'000 channels)
- require sophisticated signal processing (238 MFP/s)
... at a the power budget of a portable device.

BFC
BFC

BFC
BFC

Analog
Signals

Beamforming

Final Image

Post Processing

B. Bandpass Processing:
Exploit bandpass properties to process data at the information rate.
AFE
(incl. ADC)

RF input

Transducers

Beamformer

Minimized
Datarate

Processing Chain:

BF input

Pre-BF
Interpolation

Buered
Signal

-fs/2

fs/2

Minimized
Datarate

Delay and Sum

BF output

-fs/2

a) Analog Input Signal b) Critically Sampled

Baseband Signal

Post Processing
demodulate and
interpolate
B

fs/2

c) Interpolated
Analytic Signal

-fs/2

Image

-fs/2

fs/2

Envelop
Extraction

2B

fs/2

-fs/2

d) Beamformed
e) Beamformed
Undersampled Signal Baseband Signal

fs/2

f) Envelop Signal

- reduction of focal point and delay computation rate by at least 12x.

Ultrasound imaging:

C. Direct on-chip delay computation

Compute delays from the underlying geometry, which can be
parametrized with very few constants (36.6kBit).

Scanline

Focal Point

System Control

Transducer Element

uC Engine
instr

RF

64x16bit

const

256x22bit

Virtual Source

Fast Control
double
buering

ALU
mult prod

mem
mem

2x64x48bit

Shared Computations
1x
1x
100x

prog. LUT

shot index

Geometry

Computed
Focal Points

- fully scaleable with the number of channels and target throughput

- no external memories for buffering and delays required

fc

Scatterer

BFC

digital IQ
samples

Signal Aquisition and Pre-Processing

Spectrum:

2. The Problem

Multicore
Processor
System

BFC

Transmission

Reception

Global Control

100x

const

512x64bit
register

const

100x

Local Delay Index Computaion:

Computations per channel
(2 Additions, 1 Square-Root)

200x9bit

Shared Computations (with uC Engine)

The beamforming operation:

- sharing computations in combination with a programmable unit

enables area and power efficient on-chip delay computation.
Delay

The challenges are to...

- compute focal points at a high rate (238MFP/s)
- process massive amount of input data (160GB/s)
- provide the required delays (2.38TD/s)
Biggest Challenge
... on a single chip without external memory.

4. Results
Synthesis results (28nm SOI) for 4-100 channels:

In conventional 2D ultrasound systems, the delays are precomputed

and provided from an external memory. This is unfeasible since...
- there are 159G delays, which would require 198GB of storage
- and an access data-rate of 23.8 Tbit/s for 3D imaging.
Our approach:
Architectural Level:
Algorithmic Level:
System Level:

We attack on all design levels

Highly-scaleable beamforming architecture

Bandpass processing
Direct on-chip delay computation

5. Conclusions
- A fully-digital single-chip beamformer for 3D imaging is feasible
- The effort for delay computation can be minimized by sharing
computations and using a programmable uC Engine.

Area
Power
0%
Interp.

25%
Modula.

50%
Buer

75%
LDIC

100%
Apod

Area/Power Distribution
with BFC

- 100 channels: 1.68mm2, 3.4M GE, 303.4mW

- linear scaling with the number of channels
- shared computations and uC Engine grow irrelevant rapidly
- Estimation for 10'000 channels: 1.68cm2, 30.3W

- The beamformer can be retrofitted for efficient high-performance

2D beamforming, by reducing channel count and software update.
- Integration of the beamformer in the transducer head will enable
portable 2D and 3D ultrasound imaging devices.

[1] P. Vogel et al., Efficient Parallel Beamforming for 3D Ultrasound Imaging, GLSVLSI 2014, May 2014.
[2] P. A. Hager et al., Assessing the area/power/performance tradeoffs for an integrated fully-digital, large-scale 3d-ultrasound beamformer,
in Biomedical Circuits and Systems Conference (BioCAS), 2014 IEEE, Oct 2014, pp. 228231.