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DD+DIS161.98E
Section 6 - 4
List of contents
06.11.98
5361
Section 6.4 / I
DD+DIS161.98E
1.1
1.1.1
SCN2
J4
for DTE:
J4
J1
for DCE:
J1
J3
J3
J2
J2
Figure 1
J5
J4
J3
J2
J1
J1
J2
J3
J4
J5
J6
Thin Ethernet:
J6
UTP Ethernet:
(Twisted Pair)
J7
J7
1.1.2 MAU
Figure 2
1.1.3 COS1
Reset switch see Figure 3.
The reset switch resets all on board devices.
1.1.4 Gemini
Reset and abort switch see Figure 4
The reset switch resets all on board devices, including the CPU. The abort switch is enabled just
before the first monitor prompt appears on the debug terminal. Some situation exist in which the
09.01.00
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Section 6.4 / 1
DD+DIS161.98E
1.2
Fuses
Destination
PMC1
PMC1
PMC1
SCN2
SCN2
Power supply
Power supply
Fuse
F1
F2
F3
F1
F2
-
Value
500 mA, F, Microfuse
500 mA, F, Microfuse
500 mA, F, Microfuse
250 mA, Microfuse
250 mA, Microfuse
8AFF
8AFF
Protected voltage
8,5 V, external keypad 1
8,5 V, external keypad 3
8,5 V, external keypad 2
+ 12 V, power supply RS232/422
- 12 V, power supply RS232/422
+ 60 V, Quartz lamp decurl unit
+ 60 V, Quartz lamp decurl unit
Remark
The +/-12 V power supply for the RS232/422 on SCN2 is normally (90%) taken from the
host machine.
Section 6.4 / 2
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1.3
LED's
Destination
PMC1
LED
L1
PMC1
L2
PMC1
L3
PMC1
L4
PMC1
L5
off
on
PMC1
L6
PMC1
L7
PMC1
Heater
flashing
on/off
on
off
on
off
PMC1
+5V
PMC1
+8V
PMC1
+12V
PMC1
-12V
PMC1
+24V
09.01.00
Status
off
on
flashing
off
on
flashing
off
on
off
on
on
off
on
off
on
off
on
off
on
off
Function
selftest failed
selftest OK
selftest busy
decurl temp off
decurl temp on, temperature is not within window
decurl temp off, temperature is within window
rocan bus idle
rocan bus busy, object received
gear ratio adjustment sensor S8 not home
gear ratio adjustment sensor S8 home, will be
activated for at least 5 sec.
DSP<->592 communication idle
DSP<->592 communication busy, must flash at least
5 times/sec.
optical encoder running, channel B
optical encoder not running, channel B
PWMsignal drum motor. Led intensity is modulated
PWMsignal drum motor is 0%
PWMsignal heater decurl unit. Led intensity is
modulated
PWMsignal heater decurl unit is 0%
+5V supply voltage present
+5V failure
+8V supply voltage present
+8V failure
+12V supply voltage present
+12V failure
-12V supply voltage present
-12V failure
+24V supply voltage present
+24V failure
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Section 6.4 / 3
DD+DIS161.98E
Destination
AIC1
LED
Led1
AIC1
Led2
AIC1
Led3
AIC1
VCC
AIC1
-Vs
AIC1
+Vs
AIC1
Vth
AIC1
PWM
MDM1
PIC
(D12)
MDMST
AT (D1)
MDM1
MDM1
MDMST
AT (D5)
MDM1
MDMST
AT (D9)
MDM1
LMP
(D2)
CAN
(D10)
SAM
(D6)
PHA
(D11)
-8V
(D8)
+8V
(D7)
+24V
(D3)
+5V
(D4)
MDM1
MDM1
MDM1
MDM1
MDM1
MDM1
MDM1
Section 6.4 / 4
Status
off
on
off
on
off
on
off
on
off
on
off
on
off
on
off
on
off
on
off
on
flashing
off
on
flashing
off
on
flashing
off
on
off
on
off
on
off
on
off
on
off
on
off
on
off
on
Function
rocan bus idle
rocan bus busy,object received
TH resistance measurement idle
TH resistance measurement busy
selftest failed
selftest OK
+5V supply voltage failure
+5V supply voltage present
-12V supply voltage failure
-12V supply voltage present
+12V supply voltage failure
+12V supply voltage present
TH voltage failure
TH voltage present
TH voltage control passive
TH voltage control active
<Not used>
selftest error DSH
selftest OK
selftest busy
selftest error STM
selftest OK
selftest busy
selftest error MDM
selftest OK
selftest busy
lamp off
lamp on
rocan bus idle
rocan bus busy, object received
MDM standby
MDM sampling
STM standby
STM sampling
failure
-8V supply voltage present
failure
+8V supply voltage present
failure
+24V supply voltage present
failure
+5V supply voltage present
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Destination
COS
COS
COS
COS
LED
D4
(yellow)
Status
off
on
D5
(red)
off
on
D6
(red)
off
on
D7
(yellow)
off
on
Function
configuration busy, if it stays continuously on ->
configuration failure
configuration busy, if it stays continuously on ->
configuration failure
configuration busy, if it stays continuously on ->
configuration failure
configuration busy, if it stays continuously on ->
configuration failure
BCD coding
2
2
1
2
0
2
G Y R
G Y R
G Y R
SW
RESET
Figure 3
The green (G) LED's are hardware controlled, the yellow (Y) and red (R) are software controlled.
Green LED
Upper
Middle
Lower
Status
on
on
on
Function
Strobe active
Line sync active
data transfer from VME to COS DRAM
The yellow and red LED'S are BCD coded (7 all on, 1 only lower on)
Yellow LED's
1
2
3
4
5
6
7
09.01.00
During power up
idle (selftest OK)
checksum test
not implemented
black counter test
memory test
FIFO test
checksum test
Normal functioning
idle
filling pixelmemory
command interface active
not implemented
not implemented
reading of image data from data FIFO
not implemented
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Section 6.4 / 5
DD+DIS161.98E
During power up
idle (selftest OK)
checksum test
SRAM test
extended DRAM test
short DRAM test
FIFO test
checksum test
Normal functioning
idle
compensation calculation busy
VME command interface active
data FIFO filling with image data
TSL command interface active
not implemented
not implemented
RESET
SW
ABORT
SW
1
2
G Y R
G Y R
3
4
G Y R
G Y R
Figure 4
Blocks 1 and 3 are driven by the Slave CPU in socket 19 and blockd 2 and 4 by the Main CPU in
socket U20.
LED
1
(Software
controlled)
Status
Green
Yellow
Red
2
(Software
controlled)
3
(Hardware
controlled)
Green
Yellow
Red
Green
Yellow
Red
4
(Hardware
controlled)
Green
Section 6.4 / 6
Yellow
Red
Function
Slave CPU Idle
Slave CPU Busy
Slave CPU FLWR, 12V supply to flash EPROM during
programming cycles
Main CPU Idle
Main CPU Busy
Main CPU Fail
Slave CPU Run (CPU accesses external device: DRAM or Local
Bus)
Slave CPU Configfail, if contin. on FPGA configuration failed
Slave CPU Halted
Main CPU Run (CPU accesses external device: DRAM or Local
Bus)
Main CPU slave of external master (Local Bus or VME)
Main CPU Halted
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During power up
idle (selftest OK)
checksum test
not implemented
black counter test
memory test
FIFO test
checksum test
Normal functioning
idle
filling pixelmemory
command interface active
not implemented
not implemented
reading of image data from data FIFO
not implemented
The yellow and red LED's are BCD coded (7 all on, 1 only lower on)
Red LED's
1
2
3
4
5
6
7
09.01.00
During power up
idle (selftest OK)
checksum test
SRAM test
extended DRAM test
short DRAM test
FIFO test
checksum test
Normal functioning
idle
compensation calculation busy
VME command interface active
data FIFO filling with image data
TSL command interface active
not implemented
not implemented
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Section 6.4 / 7