Documente Academic
Documente Profesional
Documente Cultură
INTRODUCTION
Intelligent control is a control theory tehnique that uses artificial intelligence in
process of controlling dynamical systems. Some types of intelligent control are
neural networks, fuzzy logic, machine learning, ant colony and genetic algorithm. In
this research, it will be discuss about use of genetic algorithm for tuning cascade PID
controller.
Since PID controllers perform in real-time, external disturbances are always present.
Cascade connection of PID controllers will be used to avoid those disturbances and
to keep controlling process optimal.
Genetic algorithm is a simulation of a process of genetic inheritance in nature. It is
effective way for transferring the best properties from generation to the next one. The
best fitting genes from both parents are selected and incorporated into new
generation.
Control theory is an interdisciplinary branch of engineering. and its essential part.
There is a controlling process as a part of every dynamical system. Effective control
makes the difference between feasible system and unfeasible one. PID control has
been used in many applications and its tuning process can be a major challenge. The
best fitting PID coefficients are needed for a system to have an optimal performance.
This analogy can be used for development of genetic algorithm, which as a result,
will have coefficients of PID controller. For these purposes, MATLAB tools will be
used.
After PID coefficient calculation, results will be analyzed and statistically processed,
pattern in result changes according to system requirement changes will be found, so
process of control will be kept optimal in situation of different input values.
At the end, practical implementation of cascade PID controlling process will be
performed using FPGA integrated circuit. FPGA will be programmed using Verilog
Hardware Description Language. System will be ready for practical application in
industrial control processes (motor drive cascade PID controller).
CHAPTER 2
CASCADE PID CONTROL
2.1 PID Controller
PID controller is feedback loop controller used in industrial control systems. It was
first introduced in 1939 and has remained the most widely used controller in process
control until today. An investigation performed in 1989 in Japan indicated that more
than 90 % of the controllers used in industries are PID controllers and its advanced
versions (Araki, 2005).
A PID controller calculates an error value as the difference between a measured
process variable and a set point. The controller minimizes the error by adjusting the
process variable.
I =Ki e ( t ) dt
0
D=
Kdde (t)
dt
Two basic requirements are regulation (reaching given set point, disturbance
rejection) and command tracking (implementing set point changes). Specific criteria
for command tracking include settling time and rise time. An overshoot of the
process variable beyond the set point must not be allowed if it would be unsafe.
Otherwise, it must have an optimal value. Other processes must reduce the energy
consumption in reaching a new set point.
PID controller tuning is the adjustment of its parameters, P, I and D, to the optimum
values for the desired control response. Stability is a basic requirement, but various
4
CHAPTER 3
GENETIC ALGORITHM
Genetic algorithm is part of the class of evolutionary algorithms used in field of
artificial intelligence. Evolutionary algorithms are search and optimization methods,
based on the principle of natural selection in genetics. In general, any iterative,
population based approach that uses selection and random variation to generate new
solutions can be regarded as an EA. Genetic algorithms became known through the
work of John Holland in the early 1970s and was popularized by Goldberg in 1989
and, as a result, the majority of control applications in the literature adopt this
approach (Muhammet nal, 2013). Their applications include several types of
problems such as designing the communication networks, optimizing the database
query and controlling the physical systems. Thus, GA has become a robust
optimization tool for solving the problems related to different field of the technical
and social sciences (Muhammet nal, 2013).
3.1 Theoretical Foundations
GA scans the most suitable of the chromosomes that built the population in the
potential solutions space. It tries to balance two opposite objectives: searching the
best solutions and expanding the search space. During execution of GA, evolution of
the population.
evaluate results, if conditions are satisfied, then GA stops and outputs the best
with a crossover probability cross over the parents to form a new offspring, if
chromosome).
place new offspring in the old population to create a new population and use a
new generated population for a further run of the algorithm (Tze_Fun Chan,
2011).
10
CHAPTER 4
FPGA
4.1 General Notions
A field-programmable gate array is an integrated circuit designed to be fieldprogrammable by a designer. The FPGA configuration is generally specified using a
hardware description language. FPGA has large resources of logic gates and RAM
blocks to implement complex digital computations. FPGA contains programmable
logic components called logic blocks and a hierarchy of reconfigurable
interconnections that allow the blocks to be wired together. Logic blocks can be
configured to perform complex combinational, or simple logic functions like AND
and XOR.
Some FPGAs have analog features in addition to digital functions. A few FPGA have
integrated peripheral analog-to-digital converter and digital-to-analog converter.
Application of FPGA includes digital signal processing, software-defined radio,
medical imaging, computer vision, speech recognition, cryptography, bioinformatics,
computer hardware emulation, radio astronomy, metal detection and other areas.
4.2 DE2-115 Development and Education Board
11
and
sensitivity.Verilog's concept of wire consists of both signal values and strengths. This
system allows abstract modeling of shared signal lines, where multiple sources drive
a common net. When a wire has multiple drivers, the wire's value is resolved by a
function of the source drivers and their strengths.
A subset of statements in the Verilog language is synthesizable. Verilog modules that
conform to a synthesizable coding style can be physically realized by synthesis
software. Synthesis software algorithmically transforms the abstract Verilog source
into a net list, a logically equivalent description consisting only of elementary logic
primitives (AND, OR, NOT, flip-flops, etc.) that are available in a specific FPGA or
technology. Further manipulations to the net list ultimately lead to a circuit
fabrication blueprint (such as a bit stream file for an FPGA).
13
CHAPTER 5
EXPERIMENTAL RESULTS (GA FOR CASCADE PID)
5.1 The Model
Next demonstration shows a PID controller optimized by MATLAB GA function ga
when the control system is a Simulink model. To call Simulink model from
MATLAB, the model must be built, and then a MATLAB programming function is
used to call the Simulink model.
A Simulink model of a cascade PID control system is built, as shown in Figure 5.1.
Cascade PID control system will be optimized by GA. It has been simulated by a
Transfer function blocks. A Step block has been used to create a control reference.
An Out1 block has been used to export calculation results of the Simulink model.
The model has been saved with the filename PID_controller.mdl.
Parameters of cascade PID controller consist of three variables, P1, I1, D1=0 for
inner PID and P2, I2; D2=0 for outer PID. Parameters D1 and D2 are set to 0 to
avoid noise disturbances.
14
Figure 5.1 Cascade PID Simulink Model (modified) (Tze_Fun Chan, 2011)
5.2. Methodology
In order to call the Simulink model from MATLAB platform, a MATLAB function
Call_PID.m has been programmed (Appendix 1.).
In MATLAB/Simulink, there are two workspaces, one is named caller which stores
variable values of MATLAB function and other workspace is named as base which
stores variable values of Simulink model input and output. Because the ga function is
a MATLAB function, an assignin function is employed to transfer data between two
workspaces. In this way, the variable values may be exchanged between function
Call_PID.m and model PID_controller.mdl.
Overshoot variable is changeable, in range from 1 to 1.5 of an output signal
amplitude with 0.05 difference.
For loop calculates mean square error of the plant output and command reference R,
then error function has been evaluated.
15
The GA simulation has been performed in PID.m file (Appendix 2.). After GA
options and PID parameters boundaries have been set, value of fitness function has
been calculated and the plot has been drawn, as shown in Figure 5.2.
4.5
x 10
15
4
3.5
Fitness value
3
2.5
2
1.5
1
0.5
0
20
40
60
Generation
80
100
120
140
16
17
0.65
P1 vs. ovsh
untitled fit 1
0.6
P1
0.55
0.5
0.45
1.05
1.1
1.15
1.2
1.25
ovsh
1.3
1.35
1
xb 2
(
( xb
)
c1 )
+a 2e c 2
P1=a 1e
Coefficients:
a1 =0.6402
b1 =1.204
c1 =0.3399
a2 =0.128
b2 =1.474
c2 =0.08749
18
1.4
1.45
1.5
3.5
I1 vs. ovsh
untitled fit 1
3.45
3.4
3.35
I1
3.3
3.25
3.2
3.15
3.1
3.05
3
1
1.05
1.1
1.15
1.2
1.25
ovsh
1.3
1.35
1.4
1.45
1.5
( xbc 1 1 )
I 1=a1e
((xb 2)/ c 2)
+ a2e
Coefficients:
a1 =3.494
b1 =1.204
c1 =0.5045
a2 =0.5261
b2 =1.497
c2 =0.1026
4.6
P2 vs. ovsh
untitled fit 1
4.4
4.2
4
P2
3.8
3.6
3.4
3.2
3
2.8
2.6
1
1.05
1.1
1.15
1.2
1.25
ovsh
1.3
1.35
1.4
1.45
1.5
19
Coefficients:
a1 =3.514
b1 =2.531
c1 =4.549
a2 =0.5879
b2 =23.36
c2 =-11.1
a3 =0.3774
b3 =36.43
c3 =3.348
0.18
I2 vs. ovsh
untitled fit 1
0.16
I2
0.14
0.12
0.1
0.08
1.05
1.1
1.15
1.2
1.25
ovsh
1.3
1.35
1.4
1.45
1.5
Coefficients:
a1 =0.1462
b1 =3.622
c1 =3.015
a2 =0.01066
b2 =15.48
c2 =-3.88
a3 =0.02843
b3 =36.9
c3 =1.825
20
CHAPTER 6
PRACTICAL IMPLEMENTATION (FPGA & PID)
6.1. The Model
Digital computers are necessary part of a control system. It is essential to convert
real-world analog signals and its numerical representation to digital ones, so they
could be properly processed.
FPGA integrated circuit uses 16-bit digital representation of an analog signal
received after process of cascade PID tuning GA was performed. Digital display
shows 4-digit number, with each digit representing 4-bits. The number symbolizes
amplitude of an analog signal received from system response after PID controlling
process.
After starting value, representing overshoot amplitude of the signal, each switching
will change that value and it will represent oscillation process and decreasing will
represent settling process(Appendix 3).
21
22
CONCLUSION
Intelligent control advance in last few decades has improved industrial process and
products in various branches. Many techniques have been used. As shown in this
research, GA can be used in process of cascade PID controller tuning with
satisfactory results in accordance with system requirements After GA simulation has
been performed, cascade PID controller coefficients have been calculate and the
controller have been tuned. Statistical processing of results has showed that pattern
exists and controlling process can be predicted for different input values and
requirements. Since system is feasible, it can be practically implemented using
FPGA controlled by a computer system. Cascade PID controller can be used in
process of induction motor drive control.
The research has shown that GA is advanced intelligent control technique that
improves process of design and development of cascade PID controller and its
tuning. As a consequence, process being controlled will be more accurate and
reliable.
23
REFERENCES
Altera. (2014). http://www.altera.com/.
Araki. (2005). Control System, Robotics and Automation - vol II - PID Control.
Kyoto: Kyoto University.
Bck, T. (1993). Optimal Mutation Rates in Genetic Search, Proceeding of the Fifth
International Conference on Genetic Algorithms. CL, USA.
Control Solutions, I. M. (n.d.). http://www.csimn.com/.
Mathworks, I. (2014). http://www.mathworks.com/.
Michalewicz. ( 1996). Genetic algorithms and data structures. Springer, USA.
Mitchell, M. (1996). An Introduction to Genetic Algorithms. Cambridge, MA: MIT
Press.
Muhammet nal, A. A. (2013). Optimization of PID Controllers Using Ant Colony
and Genetic Algorithms. Springer-Verlag Berlin Heidelberg.
Syswerda, G. (1989). Uniform Crossover in Genetic Algorithms. In: Proceeding of
theThird International Conference on Genetic Algorithms . NJ, USA.
24
25
APPENDIX 1
Call_PID.m MATLAB CODE
function s= Call_PID(x)
assignin('base','P1',x(1));
assignin('base','P2',x(2));
assignin('base','I1',x(3));
assignin('base','I2',x(4));
[tout,xout,yout]=sim('PID_controller',200);
z=yout;
overshoot=0.1;
%Overshoot is expressed as a percentage of amplitude
s=0;
[m,n]=size(z);
%Evaluating the error function
if max(z)>1+overshoot
s=1/eps;
else
V=0;
R=1;
for i=1:m
V=V+(R-z(i))^2;
end
s=V/m;
end
end
26
APPENDIX 2
PID.m MATLAB CODE
clc;
%clear;
options=gaoptimset(@ga);
%Setting Genetic Algorithm options
options=gaoptimset(options,'PlotFcns',
{@gaplotbestf},'Display','iter');
options=gaoptimset(options,'PopulationSize',40);
options=gaoptimset(options,'EliteCount',10);
options=gaoptimset(options,'CrossoverFraction',0.6);
options=gaoptimset(options,'Generations',140);
options=gaoptimset(options,'MutationFcn',@mutationadaptfe
asible);
%Setting bounds for P and I components
lb=[0 0 0 0];
ub=[60 10 60 10];
%calling the function
[x,fval]=ga(@Call_PID,4,[],[],[],[],lb,ub,[],options);
27
APPENDIX 3
QUARTUS CODE FOR FPGA
module Edvin(SW, HEX0, HEX1, HEX2, HEX3);
input [2:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3;
wire [15:0] x, e1, e2, y1, y2, r1, r2;
SI pravimoUlaz(SW[0], x);
//Write PI
PI vanjskiRegulator(r2, e2, SW[1],SW[2]);
defparam vanjskiRegulator.k1=6;
defparam vanjskiRegulator.k2=5;
PI unutrasnjiRegulator(r1, e1, SW[1],SW[2]);
defparam unutrasnjiRegulator.k1=6;
defparam unutrasnjiRegulator.k2=5;
PI prvaPolovina(y1, r1, SW[1],SW[2]);
defparam prvaPolovina.k1=1;
defparam prvaPolovina.k2=0;
PI drugaPolovina(y2, y1, SW[1],SW[2]);
defparam drugaPolovina.k1=1;
defparam drugaPolovina.k2=0;
assign e2=x-y2;
28
assign e1=r2-y1;
Disp7 Ispis(e2, HEX0, HEX1, HEX2, HEX3);
endmodule
module SI(prekidac, kabl);
input prekidac;
output [15:0] kabl;
assign kabl=150*prekidac;
endmodule
module PI
(output reg [15:0] u_out,
input signed [15:0] e_in,
input clk,
input reset);
parameter k1;
parameter k2;
reg signed [15:0] u_prev;
reg signed [15:0] e_prev[1:2];
//assign u_out = u_prev + k1*e_in-k2*e_prev[1];
always @ (posedge clk)
if (reset == 1) begin
u_prev <= 0;
e_prev[1] <= 0;
e_prev[2] <= 0;
end
else begin
//e_prev[2] <= e_prev[1];
//e_prev[1] <= e_in;
//u_prev <= u_out;
u_out = u_prev + k1*e_in-k2*e_prev[1];
u_prev = u_prev + k1*e_in-k2*e_prev[1];
29
e_prev[2] = e_prev[1];
e_prev[1] = e_in;
end
endmodule
module
Disp7(broj,
displej1,
displej2,
displej3,
displej4);
input [15:0] broj;
output [6:0] displej1, displej2, displej3, displej4;
Seg7 prvi(broj[3:0],displej1);
Seg7 drugi(broj[7:4],displej2);
Seg7 treci(broj[11:8],displej3);
Seg7 cetvrti(broj[15:12],displej4);
endmodule
module Seg7(sel,HEX);
input [3:0]sel;
output reg [6:0]HEX;
always@(sel)
begin
if (sel==0)
HEX=7'b1000000;
else if (sel==1)
HEX=7'b1111001;
else if (sel==2)
HEX=7'b0100100;
else if (sel==3)
HEX=7'b0110000;
else if (sel==4)
HEX=7'b0011001;
else if (sel==5)
HEX=7'b0010010;
30
else if (sel==6)
HEX=7'b0000010;
else if (sel==7)
HEX=7'b1111000;
else if (sel==8)
HEX=7'b0000000;
else if (sel==9)
HEX=7'b0010000;
else if (sel==10)
HEX=7'b0001000;
else if (sel==11)
HEX=7'b0000011;
else if (sel==12)
HEX=7'b1000110;
else if (sel==13)
HEX=7'b0100001;
else if (sel==14)
HEX=7'b0000110;
else if (sel==15)
HEX=7'b0001110;
else
HEX=7'b1010101;
end
endmodule
31