Sunteți pe pagina 1din 4

ESSCIRC 2002

A 0.5V, 1µW Successive Approximation ADC

Jens Sauerbrey Doris Schmitt-Landsiedel Roland Thewes


Infineon Technologies AG Technical University of Munich Infineon Technologies AG
Corporate Research Institute for Technical Electronics Corporate Research
D-81730 Munich, Germany D-80333 Munich, Germany D-81730 Munich, Germany
jens.sauerbrey@infineon.com dsl@ei.tum.de roland.thewes@infineon.com

Abstract converters is presented. Only standard “digital” CMOS


transistors are used, bootstrapping techniques are avoided.
A successive approximation analog-to-digital converter Similar as in switched opamp circuits [2, 3], this ADC
is designed in a way that only reference voltages are
(ADC) is presented operating at ultra low supply voltages.
switched. Use of a capacitor-based DAC and of a passive
The circuit is realized in a 0.18µm CMOS technology. sample-and-hold stage enables the circuit to be operated at
Neither low-VT devices nor voltage boosting techniques very high values of VT/VDDmax.
are used. All voltage levels are between supply voltage
(VDD) and ground (VSS). A passive sample-and-hold
2. Converter principle
stage and an capacitor-based digital-to-analog converter
(DAC) are used to avoid application of opamps, since 2.1. Basic principle of successive approximation
opamp operation requires higher values for the lowest converters
possible supply voltage. The ADC has a signal-to-noise-
and-distortion ratio (SNDR) of 51.2dB and 43.3dB for Successive Approximation A/D Converters consist of
supply voltages of 1V and 0.5V, at sampling rates of a sample-and-hold stage (S&H), a comparator, a
150kS/s and 4.1kS/s and power consumptions of 30µW successive approximation register (SAR), and a DAC
(Fig. 1). Using a binary search algorithm, the DAC
and 0.85µW, respectively. Proper operation is achieved
output voltage VA successively approximates the
down to a supply voltage of 0.4V. sampled input voltage VH. In each clock cycle one bit of
digital output signal D is obtained.
1. Introduction
In modern CMOS processes, the maximally allowed VH D1
supply voltage VDDmax is continuously decreasing but the Vin S&H D2
threshold voltage of the devices, VT, is not scaled in
SAR
DN
proportion to VDDmax due to off-state currents and the VA
related static power consumption in logic circuits [1]. In
DAC
the digital world, the increasing ratio of VT/VDDmax is
usually acceptable, however, for analog circuits decreased
signal swings and crucial design restrictions result. In Fig.1. Successive approximation converter
particular for VDD values below the sum of the threshold architecture
voltages of n- and p-MOSFETs (VTn+VTp), only a very
limited number of circuit topologies is still usable. 2.2. Successive approximation converter based
Specific process options as provision of low-VT devices on a charge redistribution principle
help the analog circuit designer to overcome these
constraints but lead to increased process complexity and to In Fig. 2, a converter based on a charge redistribution
increased costs. Adapted analog design approaches principle is depicted. Binary weighted capacitors are
avoiding such options but providing same performance used for the DAC. The sample-and-hold function is
thus represent an attractive alternative. realized by the DAC itself. The switching point of the
Switched opamp circuits [2, 3] and circuits using comparator is independent of the value of the input
bootstrapping techniques [4] have been shown to be signal. During conversion at the comparator input
particularly suited under low VDD conditions without positive and negative voltages VC referred to analog
specific process options. In case of the latter design ground occur, whose magnitude is continuously
technique, however, gate-to-bulk voltages are applied to decreasing with the number of conversion steps
part of the devices which exceed VDDmax so that enhanced performed within a complete conversion cycle.
device stress occurs. Consequently, at the end of the conversion cycle, i.e.
In this paper, a successive approximation ADC when highest precision is demanded, both comparator
technique suitable for medium-speed/medium-resolution inputs are operated near analog ground.

247
To avoid leakage currents at switch S1 on the one 3. Circuit implementation
hand, analog ground should be adjusted in the middle
between VDD and VSS. On the other hand switch 3.1. Capacitor array
operation at ultra low supply voltages (e.g. under VDD-
VSS<VTn+VTp-conditions) is only possible if the DC level The capacitors C0...CN in Fig. 3 are realized as
of the signal to be switched is close to VDD or VSS. multiples of a unit capacitor of 20fF. Since small
Since theses requirements cannot be fulfilled differences of the value of CS referred to the value of
simultaneously the approach shown in Fig. 2 is not capacitances provided by the C-array only result in a
suitable for ultra low voltage applications. small gain error but do not affect the linearity, CS is
realized as a non-subdivided large area device for 9-bit
mode operation. In the 8-bit case, CS is obtained by
Ci+1=2Ci i=1,..,N-1 connecting C9 and CS from the 9-bit version in parallel
VC D1
SAR D2 (cf. Table 1).
S1
DN
Vin CN C2 C1 C0 Table 1. Capacitor values
C1=C0
bit-mode 8-bit mode 9-bit mode
V R S2 CS 10.24pF 15.36pF
C9 5.12pF
C8 2.56pF 2.56pF
Fig.2. Successive approximation architecture based C7 1.28pF 1.28pF
. . .
on a charge redistribution principle .
.
.
.
.
.
. . .

C2 40fF 40fF
2.3. Modified successive approximation C1= C0 20fF 20fF
converter
9-bit mode is used when the supply voltage is large
A modified architecture using a capacitor-based DAC is enough for proper sample-and-hold and comparator
shown in Fig. 3. The DAC simply tracks the sampled ADC function for a maximum input voltage of VDD/2. For
input signal VH. VSS and VDD are used as reference smaller values of VDD 8-bit mode is used.
levels. A shunt capacitor CS is operated as capacitive
divider to adjust the signals according to the low supply 3.2. Comparator
voltage operating conditions of the circuit. Corresponding
to 9- or 8-bit operation, 0.5×VDD or 0.25×VDD is chosen The comparator is designed as a simple regenerative
as input voltage range here. Minimum input voltage equals resetable circuit (Fig. 4). It is designed for an input
VSS in all cases. This adjustment guarantees proper common mode voltage range between 0V and VDD/2 or
comparator as well as sample-and-hold operation within VDD/4, respectively (cf. chapter 2.3.). Although the input
the whole input voltage range. transistors are operated in weak inversion under ultra low
In this architecture the S&H function is no more VDD conditions, reasonable sampling rates are obtained
realized by the capacitor array itself as in Fig. 2. A passive (cf. Fig. 11) since only small capacitive loads have to be
sample-and-hold stage is used here. This is sufficient as the driven by this sub-circuit.
load of the sample-and-hold stage only consists of the
MOS-gate of the input transistor of the comparator. An vbias
VDD
advantage of this approach is that the input capacitance of
the whole converter is not determined by the DAC inp inm out
capacitor array.

clk
Vin S&H VSS
VH D1
Ci+1=2Ci i=1,..,N-1
SAR D2 Fig.4. Comparator circuit
VA DN
CS CN C2 C1 C0 C1=C0 3.3. Successive approximation register
S1 CS=2CN for Vin_max=VDD/2
VSS CS=6CN for Vin_max=VDD/4 The successive approximation register (SAR) is
VDD realized in static CMOS logic. The circuit also generates
the clock signals for the comparator and the sample-and-
hold circuit. All clock signals are derived from an
Fig.3. Modified architecture externally provided master clock.

248
3.4. Sample-and-hold circuit 4.1. Static measurements
The sample-and-hold circuit is shown in Fig. 5. Figure 7 shows measured data of the integral
Capacitors CH1 and CH2 are alternately operated in sample nonlinearity (INL) and of the differential nonlinearity
and in hold operation. The sampling clock “fS” provided (DNL) in 9-bit mode at VDD = 1V. To evaluate these
by the SAR is divided by two. A non-overlapping two- parameters in 8-bit mode it is sufficient to consider only
phase clock is generated. Both signals are provided in the codes from 1 up to 256 in these diagrams.
complementary form to control the n-MOS switches and
the related n-MOS dummy switch devices. 1
The operating point of the switch transistors determines

INL [LSB]
the minimum settling time. At ultra low supply voltage
0
these transistors are operated in weak inversion when
switched “on”. However, a relaxation of the impact of this
operating condition is obtained due to the fact that the -1
100 200 300 400 500
sampling frequency is an order of magnitude lower than Output code
the operating frequency of the comparator. Moreover, the 1

DNL [LSB]
switching frequency is two times lower compared to the
sampling frequency since two time-interleaved sampling 0
paths are used.
The sampling capacitors are not integrated on-chip. We
use relatively large values of 47pF here in order to -1
100 200 300 400 500
suppress parasitic coupling effects caused by packaging Output code
and bondwire capacities. Integration of these capacitors Fig.7. Measured INL and DNL in 9-bit mode at
on-chip allows to significantly decrease their value. VDD = 1V

4.2. Dynamic measurements


compensated CH1 VSS
n-MOS switches Fig. 8 shows a full scale 200Hz sine wave spectrum
measured at VDD=0.5V at a sampling rate of 4.1kS/s.

fS 2:1 clock
0
Vin VH
-10
CH2
VSS -20
Amplitude [dB]

-30
Fig.5. Sample-and-hold circuit
-40

4. Experimental results -50


-60
The ADC is fabricated in a 0.18 µm n-well CMOS
process with single poly, four metal layers and a -70
MIMCAP (Metal-Insulator-Metal) capacitor option. The -80
threshold voltages are 0.43V for the n-MOS and -0.38V
0 0.5 1 1.5 2
for the p-MOS device. A chip photograph is shown in Frequency [kHz]
Fig. 6. Chip area is 0.11 mm2.
Fig.8. Measured FFT spectrum at VDD=0.5V,
9-bit mode 100um 200Hz input signal frequency, 0.125V input signal
2
0
swing, and 4.1kS/s sampling rate
1
4
3 0
C6 2 1
C5 SNDR vs. sinusoidal input frequency at input levels
C
CS C9 C8 4
C
3
between 0dB and –40dB at VDD=0.5V and 1V are shown
in Figs. 9 and 10, respectively.
C7 Fig. 11 shows the maximum sampling rate and the
related power dissipation as a function of supply voltage.
switches The sampling rate decreases with a moderate slope from
SAR clock comp
S&H
150kS/s to 34kS/s for supply voltages from 1V down to
0.6V. For smaller supply voltages the drop of the sampling
Fig.6. Chip photograph rate is more pronounced.

249
There, an SNDR of 38.9dB at 0.6kS/s is achieved.
50
Measured results are summarized in Table 2.
0dB
40 -3dB
-6dB 60
-10dB
SNDR [dB]

30 50

40

SNDR [dB]
-20dB
20
30
-30dB
10 20 9-bit mode
10 8-bit-mode
-40dB
0
10 100 1000 0
Frequency [Hz]
1 0.9 0.8 0.7 0.6 0.5 0.4
Fig.9. SNDR vs. input frequency at VDD=0.5V, Supply voltage [V]
sampling rate =4.1kS/s, VIN=0dB (0.125V), Fig.12. SNDR vs. supply voltage
-3dB, -6dB, -10dB, -20dB, -30dB, -40dB

60
Table 2. Measured ADC performance
Supply voltage 1V 0.6V 0.5V 0.4V
50 0dB Sampling rate 150kS/s 34kS/s 4.1kS/s 0.6kS/s
-3dB
-6dB Input signal swing 0.5V* 0.3V* 0.125V** 0.1V**
-10dB
40 SNR 51.6dB* 47.4dB* 43.6dB** 39.2dB**
SNDR [dB]

-20dB SNDR 51.2dB* 46.5dB* 43.3dB** 38.9dB**


30
Power diss. 30µW 3.12µW 0.85µW 0.28µW
-30dB Technology 0.18µm CMOS, 1P/4M/MIMCAP used
20
VTn = 0.43V, VTp = - 0.38V
-40dB Die area converter 0.45mm×0.24mm=0.11mm2
10
Die area S&H 0.085mm×0.02mm=0.002mm2 (w/o CH1,CH2)
0 *9-bit mode **8-bit mode
1 10 100
Frequency [kHz]

Fig.10. SNDR vs. input frequency at VDD=1V,


5. Conclusion
sampling rate =150kS/s, VIN=0dB (0.5V),
-3dB, -6dB, -10dB, -20dB, -30dB, -40dB A successive approximation converter suitable for
operation at ultra low supply voltage is realized in a
0.18µm CMOS technology using standard threshold
1.E+03
CMOS devices and avoiding bootstrapping techniques.
Max. sampling rate [kS/s]

Test results indicate that the circuit is well suited for


Power dissipation [uW]

1.E+02
operation far below 1V. Proper operation is shown down
1.E+01
to a supply voltage of 0.4V, which is approximately
equal to the threshold voltages of the devices used.
1.E+00
Max. sampling rate 6. References
1.E-01
Power dissipation
[1] International Technology Roadmap for Semiconductors,
1.E-02 http://public.itrs.net/.
1 0.9 0.8 0.7 0.6 0.5 0.4 [2] V. Peluso, P. Vancorenland, A. Marques, M. Steyaert, and
Supply voltage [V] W. Sansen, "A 900mV 40µW Switched Opamp ∆Σ
Modulator with 77dB Dynamic Range", ISSCC Digest of
Fig.11. Maximum sampling rate and power Technical Papers, pp. 68-69, p. 414, 1998.
dissipation vs. supply voltage [3] J. Sauerbrey, T. Tille, D. Schmitt-Landsiedel, and R.
Thewes, “A 0.7V MOSFET-Only Switched-Opamp Σ∆
Measured SNDR as a function of VDD is shown in Modulator ”, ISSCC Digest of Technical Papers, pp.310-
Figure 12. A reasonable SNDR value under 9-bit mode 311, p. 469, 2002.
operation is obtained down to a supply voltage of [4] M. Dessouky and A. Kaiser, "A 1V 1mW Digital-Audio
approximately 0.6V. In 8-bit mode the circuit shows ∆Σ Modulator with 88dB Dynamic Range using Local
proper operation down to a supply voltage of 0.4V. Switch Bootstrapping", Proc. CICC, pp. 13-16, 2000.

250

S-ar putea să vă placă și