Ansi Ieee STD 991 (1986)

ANSI/IEEE Std 991-1986
An American National Standard IEEE

Standard for Logic Circuit Diagrams
Sponsor
IEEE Standards Coordinating Committee 11, Graphic Symbols and Designations

Approved March 21, 1985
IEEE Standards Board

Approved April 25, 1985
American National Standards Institute
Copyright 1986 by
The Institute of Electrical and Electronics Engineers, Inc
345 East 47th Street, New York, NY 10017, USA
No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the
prior written permission of the publisher.
Acceptance Notice
This non-Government document was adopted on 5 June, 1986, and is approved for use by the DoD. The indicated
industry group has furnished the clearances required by existing regulations. Copies of the document are stocked by
DoD Single Stock Points, US Naval Publications and Forms Center, Philadelphia, PA 19120, for issue to DoD
activities only. Contractors and industry groups must obtain copies directly from IEEE, 345 East 47th Street, New
York, NY 10017.
Title of Document:
IEEE Standard for

Logic Circuit Diagrams
Document No:
Date of Specific Issue Adopted:
27 June, 1986
Releasing Industry Group:
The Institute of Electrical and Electronics Engineers, Inc.
Custodians:
Army -- AR
Navy -- SH
Military Coordination Activity:

Amry -- AR
Project DRPR-0260
Air Force -- 13
Review Activities:
Army -- AV, MI, AM, CR, ER
Navy -- OS, AS
Air Force -- 11, 15, 17
User Activities:
Army -- AT
Navy -- MC
NOTICE: When reafrmation, amendment, revision, or cancellation of this standards is initially proposed, the industry
group responsible for this standard shall inform the military coordinating activity of the proposed change and request
participation.
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iii
Foreword
(This Foreword is not a part of ANSI/IEEE Std 991-1986, IEEE Standard for Logic Circuit Diagrams.)
The contributors to this standard represent a broad range of institutions, technologies, and documentation needs. They
include industrial, governmental, and educational organizations, producers and consumers of devices and equipment,
users and nonusers of computer-aided design and drafting, and a range of aesthetic preferences. That a consensus of
such diverse interests could be achieved in producing this standard is indicative of a need for a common practice in this
eld.
Work on this standard started in 1972, in an ad-hoc working group on Logic Diagrams, under the preparing group for
Y14.15, Electrical Diagrams. Work was suspended for several years while the International Electrotechnical
Commission, Technical Committee 3 developed Publication 117, Part 7. to which the United States contributed. In
1982 a new subcommittee was formed, operating as part of the IEEE Standards Coordinating Committee for Graphic
Symbols and Designations, SCC 11. It decided to prepare a new draft incorporating:
1)
2)
3)
The 1975 draft of the original working group,

IEC Publication 113, Part 7. insofar as practical (in the present standard, some parts and illustrations are very
similar to the IEC document; differences and additions result from new developments in symbols for logic
functions and new perceptions of current needs), and
Such parts of ANSI Y14.15-1968 (R 1973) as applied to logic circuit diagrams, but with updating to remove
duplication of requirements found in referenced standards and to apply the material explicitly to logic circuit
diagrams.
After ten drafts the present document was completed and submitted to the IEEE Standards Board for approval.
The following persons were on the balloting committee that approved this document for submission to the IEEE
Standards Board:
Standards Coordinating Committee on Graphic Symbols and Designations, SCC 11
R. B. Angus, Jr
J. C. Brown
G. A. Knapp
C. R. Muller
John Peatman
J. W. Seifert
T. R. Smith
S. V. Soanes
R. M. Stern
L. H. Warren
S. A. Wasserman
Subcommittee on Logic Circuit Diagrams, SCC 11.10

T. R. Smith, Chair
C. R. Muller, Acting Secretary
R. W. Andrews
R. B. Angus, Jr
John Balog
R. R. Barta
L. Burns
L. A. Ciskowski
L. Davis *
P. H. Enslow
C. D. Fisher
E. R. Fleming
A. C. Gannett
J. J. George
* Liaison AFLC / MM APD
Liaison Y14
Resigned
Liaison DoD
iv
A. Hendry
W. R. Holbrook
G. A. Knapp
J. A. Kohlmeier
J. M. Kreher
F. A. Mann
D. Martinec
J. Massaro
R. P. Mayer
J. F. Morrongiello
E. L. Nesbitt
V. T. Rhyne
M. R. Richter
R. R. Ritter
J. P. Russell
R. Sandige
L. E. Schulz
R. M. Stern
R. D. Stuart
M. E. Taylor
R. Tobias
J. Vargo
L. H. Warren
J. Williams
R. J. Yuhas
At the time this standard was approved on March 21, 1985, the IEEE Standards Board had the following membership:
John E. May, Chair
John P. Riganati, Vice Chair
Sava I. Sherr, Secretary
James H. Beall
Fletcher J. Buckley
Rene Castenschiold
Edward Chelotti
Edward J. Cohen
Paul G. Cummings
Donald C. Fleckenstein
Jay Forster
Daniel L. Goldberg
Kenneth D. Hendrix
Irvin N. Howell, Jr
Jack Kinn
Joseph L. Koepfinger*
Irving Kolodny
Donald T. Michael*
R. F. Lawrence
Lawrence V. McCall
Frank L. Rose
Clifford O. Swanson
J. Richard Weger
W. B. Wilkens
Charles J. Wylie
*Member emeritus
CLAUSE
1.
PAGE
Introduction .........................................................................................................................................................1
1.1 Purpose....................................................................................................................................................... 1
1.2 Scope .......................................................................................................................................................... 1
2.
Applicable Documents ........................................................................................................................................1

2.1 Industry Standards...................................................................................................................................... 1
2.2 Military Standards...................................................................................................................................... 2
2.3 International Standards .............................................................................................................................. 2
3.
Definitions...........................................................................................................................................................3
4.
General Requirements.........................................................................................................................................4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.
Content ....................................................................................................................................................... 4
Drawing Size and Format .......................................................................................................................... 4
Diagram Titles............................................................................................................................................ 5
Diagram Revisions ..................................................................................................................................... 5
Lettering ..................................................................................................................................................... 5
Lines........................................................................................................................................................... 5
Abbreviations ............................................................................................................................................. 6
Letter Symbols ........................................................................................................................................... 6
Layout and Presentation............................................................................................................................. 6
Logic Conventions and Polarity Indication ........................................................................................................7

5.1 Relationship Between Logic States and Logic Levels............................................................................... 7
5.2 Single Logic Convention ........................................................................................................................... 8
5.3 Direct Polarity Indication........................................................................................................................... 8
6.
Symbols for Devices and Functions....................................................................................................................9

6.1 Standard Symbols ...................................................................................................................................... 9
6.2 Size........................................................................................................................................................... 14
6.3 Orientation ............................................................................................................................................... 14
6.4 Application and Identification Information ............................................................................................. 17
6.5 Inputs and Outputs with Multiple Functions............................................................................................ 19
6.6 Abbreviated Representation of Symbols.................................................................................................. 21
6.7 Abutment of Symbols .............................................................................................................................. 23
6.8 Detached Representation of Symbols ...................................................................................................... 23
6.9 Unused Terminals and Elements.............................................................................................................. 24
6.10 Devices Having a Large Number of Terminals ....................................................................................... 24
7.
Interconnection of Symbols ..............................................................................................................................25

7.1
7.2
7.3
7.4
7.5
7.6
7.7
vi
General Requirements.............................................................................................................................. 25
Line Spacing ............................................................................................................................................ 26
Junctions and Crossovers ......................................................................................................................... 26
Interrupted Lines ...................................................................................................................................... 27
Grouping of Lines .................................................................................................................................... 28
Polarity and Negation Matching .............................................................................................................. 28
Power Connections .................................................................................................................................. 29
CLAUSE
8.
Labeling of Connecting Lines...........................................................................................................................29

8.1
8.2
8.3
8.4
8.5
9.
General ..................................................................................................................................................... 29
Names for Logic and Analog Signals ...................................................................................................... 29
Names for Power and Other Constant-Level Connections ...................................................................... 37
Locator Information ................................................................................................................................. 37
Additional Properties and Characterization ............................................................................................. 38
Supplementary Information ..............................................................................................................................38

9.1
9.2
9.3
9.4
9.5
10.
PAGE
Reference-Designation Accounting ......................................................................................................... 38

Diagram Notes ......................................................................................................................................... 38
Tabular Information ................................................................................................................................. 40
Waveforms ............................................................................................................................................... 40
Diagram Simplification and Abbreviation Techniques............................................................................ 42
Examples of Logic Diagrams............................................................................................................................49
Annex A Mnemonics for Use in Signal Names (Informative) .....................................................................................60

Annex B Lines and Lettering Size and Spacing (Informative) ................................................................................72
Annex C Single Orientation of Lettering (Informative) ...............................................................................................82
vii
An American National Standard

IEEE Standard for Logic Circuit Diagrams
1. Introduction
1.1 Purpose
The purpose of this standard is to provide standard practices and information for use in the preparation of diagrams
depicting logic functions.
1.2 Scope
This standard provides guidelines for preparation of diagrams depicting logic functions. It includes denitions,
requirements for assignment of logic levels, application of logic symbols, presentation techniques, and labeling
requirements with typical examples. The techniques are presented in the context of electrical/electronic systems, but
also may be applied to nonelectrical systems (for example, pneumatic, hydraulic, or mechanical).
2. Applicable Documents
2.1 Industry Standards
The latest editions of the following industry documents form a part of this standard to the extent specied herein:
American National Standards
ANSI X3.4-1977, American National Standard Code for Information Interchange.1
ANSI X3/TR-1-1983, American National Standard Dictionary for Information Processing.
ANSI Y1.1-1972 (R 1984), American National Standard Abbreviations for Use on Drawings and In Text.
1
ANSI publications are available from the Sales Department, American National Standards Institute, 1430 Broadway, New York, NY 10018.
Copyright 1986 IEEE All Rights Reserved
IEEE STANDARD FOR
ANSI Y14.1-1980, American National Standard Drawing Sheet Size and Format.
ANSI Y14.2M-1979, American National Standard Line Conventions and Lettering.
ANSI Y14.15-1966 (R 1973), American National Standard Electrical and Electronics Diagrams (includes
Supplements ANSI Y14.15a-1971 and ANSI Y14.15b-1973 ).
ANSI/IEEE Std 91-1984, IEEE Standard Graphic Symbols for Logic Functions.2
ANSI/IEEE Std 100-1984, IEEE Standard Dictionary of Electrical and Electronics Terms.
ANSI/IEEE Std 194-1977, IEEE Standard Pulse Terms and Denitions.
ANSI/IEEE Std 200-1975, IEEE Standard Reference Designations for Electrical and Electronics Parts and Equipment.
ANSI/IEEE Std 260-1978 (R 1985), IEEE Standard Letter Symbols for Units of Measurement (SI Units, Customary
Inch-Pound Units, and Certain Other Units).
ANSI/IEEE Std 280-1985, IEEE Standard Letter Symbols for Quantities Used in Electrical Science and Electrical
Engineering.
ANSI/IEEE Std 315-1975, Graphic Symbols for Electrical and Electronics Diagrams (Including Reference
Designation Class Designation Letters).
2.2 Military Standards

The latest edition of the following Department of Defense document forms a part of this standard to the extent
specied herein and shall be used for DoD contracts in place of the equivalent Industry Standards listed above:
MIL-STD-12, Military Standard Abbreviations for Use on Drawings, Specications, Standards, and in Technical
Documents.3
2.3 International Standards

This standard is compatible (except as noted) with the following publications:
IEC Publication 113 (1971 - 1983), Diagrams, Charts, Tables.4
ISO 31/1-1978, Quantities and Units of Space and Time.5
ISO 646-1983, 7-bit Coded Character Set for Information Processing Interchange.
2 IEEE publications are available from IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854.
3 MIL publications are available from Superintendent of Documents, US Government Printing Office, Washington, DC 20402.
4IEC publications are available in the United States from the Sales Department, American National Standards Institute, 1430 Broadway, New York,
NY 10018, USA. The IEC publications are also available from International Electrotechnical Commission, 3, rue de Varemb, Case postale 131,
1211Genve 20, Switzerland/Suisse.
5 ISO publications are available in the United States from the Sales Department, American National Standards Institute, 1430 Broadway, New York,
NY 10018, USA. ISO publications are also available from the ISO Office, 1, rue de Varemb, Case postale 56, CH-1211, Genve 20, Switzerland/
Suisse.
LOGIC CIRCUIT DIAGRAMS
3. Definitions
The following denitions are for use with this standard. For other use and for denitions not contained herein, see
ANSI/IEEE Std 100-1984 .6
graphic symbol: A gure, mark, or character conventionally used on a diagram, document, or other display to
represent an item or a concept.
logic symbol: A graphic symbol that represents a logic function.
qualifying symbol: A graphic symbol added to another to provide additional information. For a logic element, a
graphic symbol added to the basic outline to designate the overall logic characteristics of the element or the physical
or logic characteristics of an input or output of the element.
negation bar: A line over a signal label that indicates logic inversion of that signal.
element: As used within this standard, a representation of all or part of a function within a single outline, which may,
in turn, be subdivided into smaller elements representing subfunctions of the overall function. Alternatively, the
function so represented.
logic circuit diagram: A circuit diagram that predominantly uses symbols for logic functions to depict the overall
function of a circuit.
basic logic diagram: A logic circuit diagram that depicts, in simple form, the intended function of a circuit. It does
not necessarily contain constructional or engineering information, nor does it represent exactly the nal physical
form.
detailed logic diagram: A logic circuit diagram that depicts, in detail, a circuit as actually implemented. It contains
information that can be used for manufacturing or maintenance purposes, but it does not necessarily include
engineering information that is not concerned with logic functions.
logic state: One of two possible abstract states that may be taken on by a logic (binary) variable.
0-state: The logic state represented by the binary number 0 and usually standing for an inactive or false logic
condition.
1-state: The logic state represented by the binary number 1 and usually standing for an active or true logic condition.
logic level: Any level within one of two nonoverlapping ranges of values of a physical quantity used to represent the
logic states.
NOTE A logic variable may be equated to any physical quantity for which two distinct ranges of values can be dened. In this
standard, these distinct ranges of values are referred to as logic levels and are denoted H and L.
H is used to denote the logic level with the more positive algebraic value, and L is used to denote the logic level with
the less positive algebraic value.
In the case of systems in which logic states are equated with other physical properties (for example, positive or
negative pulses, presence or absence of a pulse), H and L may be used to represent these properties or may be
replaced by more suitable designations.
high (H) level: A level within the more positive (less negative) of the two ranges of the logic levels chosen to
represent the logic states.
low (L) level: A level within the more negative (less positive) of the two ranges of logic levels chosen to represent
the logic states.
signal state: The logic state corresponding to the truth-value of the statement or expression represented by a signal
name.
6When reference is made to any publication throughout this standard the user should refer to Section 2. for the full title and location of availability.
IEEE STANDARD FOR
logic conventions and polarity indication

positive logic convention: The representation of the external 1-state and the external 0-state by the high (H) and low
(L) levels, respectively.
negative logic convention: The representation of the external 1-state and the external 0-state by the low (L) and high
(H) levels, respectively.
direct polarity indication: The indication of the relationship between the internal logic state and the external logic
level at each input and output of the every logic element directly by means of the presence or absence of the polarity
symbol (
).
4. General Requirements
4.1 Content
4.1.1 Basic Logic Diagram
This diagram shall show the conceptual principles of a circuit. It shall include as a minimum the required logic
symbols and other necessary functional symbols, together with their signal and major control path connections. Other
information such as waveforms, formulas, and algorithms may be included. Physical location, pin connection, and
assembly level information are usually omitted.
4.1.2 Detailed Logic Diagram
This diagram shall show the information necessary for manufacture, installation, maintenance, and training for a logic
circuit or system. It shall include as a minimum:
1)
2)
3)
4)
5)
6)
Graphic symbols for logic functions and other devices (see Section 6.)
Connections among symbols (signal, control, and power) (see Section 7.)
Reference designations (see 6.4.1.1)
Terminal identication (see 6.4.1.5)
Signal-level conventions applicable to the diagram: positive or negative logic, logic states or levels (for
example, H and L) (see Section 5.)
Information necessary to trace paths and circuits among sheets of the diagram (see 7.4)
4.1.3 Combined Forms of Circuit Diagrams

Provided that approved standards are followed, diagrams combining logic circuit information with conventional
schematic (mechanical, or electrical) diagram information may be prepared.
4.2 Drawing Size and Format

Drawing sizes and formats used with diagrams shall conform to ANSI Y14.1-1980 . In general, the smallest standard
format compatible with the nature of the diagram should be selected. See also Appendix 11..
4.2.1 Drawing Zones
On logic diagrams with many logic elements, it is often helpful to have a coordinate system to permit referencing
particular areas or zones on the sheet (see ANSI Y14.1-1980). This is especially helpful when many sheets are
required and cross references between sheets are numerous. Signal tracing is expedited if reference can be made from
one point in a diagram to both sheet and zone of another point.
4.2.2 Supplemental Drawing Number Location

If a diagram is reproduced for an instruction book or similar purposes and the title block is not retained, it may be
desirable to include the original drawing number within the reproduced area. This drawing number (if included)
should be shown close to the lower right edge of the reproduced area in a lettering size comparable to that used for
notes and other detailed reference material.
4.3 Diagram Titles

The title of the diagram should include the name of the circuit or equipment followed by the diagram type. For
example: MEMORY CONTROLLER, MODEL 1134 CIRCUIT DIAGRAM.
4.4 Diagram Revisions

Provision shall be made on all logic circuit diagrams for recording revisions. The record of changes made in each
revision shall be identied7 by either a number, letter or character, and the date of the revision. When it is possible to
make a brief detailed explanation of the revision, this is desirable. When a detailed explanation is not practicable, a
note covering the general nature of the revision should be included. A reference to a change order document may be
shown in lieu of an explanation.
4.5 Lettering
Lettering style, size, spacing, and legibility shall conform to ANSI Y14.2M-1979 .
NOTE Lettering height and spacing affect symbol size and overall layout of diagrams. See Appendix B for guidelines including
those applying to diagrams that are used both as a part of the engineering drawing set and in technical manuals.
4.5.1 Orientation
All lettering within a diagram shall be readable from no more than two orientations of the diagram, 90 apart.8
4.6 Lines
Line width and quality shall be such that, after reproduction of the diagram at the required size, all lines shall be legible
and without breaks. For detailed recommendations concerning line width, see Appendix B.
Thick lines may be used for general use (including symbols and connecting lines) and for lettering. Thin lines should
be approximately half the width of the thick lines.
If emphasis of special features, such as main or transmission paths, is essential, an extra-thick line, approximately
twice the width of thick lines, may be used to provide the desired contrast.
Line conventions for use on logic circuit diagrams are shown in Fig 1.
7For US Department of Defense applications, the identification shall be an uppercase letter, used in alphabetical sequence, omitting the letters I, O,
Q, S, X, and Z.
8For special IEC requirements, see Appendix 11..
IEEE STANDARD FOR
Figure 1Line Conventions for Diagrams
4.7 Abbreviations
For rules applying to connecting-line labels, see Section 8. Other abbreviations used on diagrams shall conform to
ANSI Y1.1-1972 (R 1984).9 If the term is not included in ANSI Y1.1-1972 (R 1984), an abbreviation given in other
standards recognized as National Standards may be used. If no suitable abbreviation exists, a special abbreviation may
be used, but shall be explained by a note on the diagram.
4.8 Letter Symbols

Letter symbols for units of measurement shall conform to ANSI/IEEE Std 260-1978 (R 1985).
Letter symbols for quantities used in electrical science and electrical engineering shall conform to ANSI/IEEE Std
280-1985.
4.9 Layout and Presentation

4.9.1 Coverage
A logic diagram, which may consist of several sheets, should be prepared for each distinct unit, or assembly of units,
intended to fulll a dened purpose. It may thus relate to a single unit or to several units that together form a functional
entity. In cases where the logic diagram cannot be shown on a single sheet, the division into separate sheets should be
based on the purpose of the diagram.
4.9.2 Planning
Basic logic diagrams are prepared primarily for design engineers. It is possible, in many cases, for the basic diagram
to be converted to a detailed diagram simply by adding the required labeling. If this can be foreseen, the basic diagram
should initially be laid out with sufcient space left both inside and outside of the symbols to accommodate future
labeling.
9See
also 2.2.
4.9.3 Signal Flow

The principal direction of signal ow should be from left to right or, alternatively, from top to bottom. Flow direction
may be indicated by the orientation of symbols, logic polarity symbols, or ow arrowheads, or by a convention of
unidirectional ow suitably noted. Regardless of the convention used, the signal ow shall be clearly indicated. The
ow arrowhead is a small arrowhead superimposed upon data lines or control lines. The ow arrowhead shall not touch
any part of the symbol.
4.9.4 Layout
The layout shall be such that the main features are prominently shown. The parts should be spaced to provide an even
balance between blank spaces and lines. Sufcient blank area should be provided in the vicinity of symbols to avoid
crowding of information. Functionally related symbols should be grouped (see 4.9.5) and placed as close to one
another as the requirements of annotation and the avoidance of overcrowding will allow. Large spaces should be
avoided, except that space provision may be made for anticipated circuit additions.
The logic diagram shall use a layout that follows the circuit, signal, or transmission path either from input to output,
source to load, or in the order of functional sequence. Long interconnecting lines between parts of the circuit should
he avoided. Similar basic circuits should be drawn in a similar form (this does not prevent the use of simplied
representation to depict repeated circuits).
Where practical, signal ow lines should begin and terminate at the outer edge of the sheet. If this is not practical,
references to the terminations may be made by the use of drawing zones.
4.9.5 Grouping of Symbols
If a circuit contains symbols that need to be shown grouped, the grouping may be indicated by means of a boundary
(phantom) line enclosure (see Fig 1). The phantom line enclosure may be omitted if sufcient space is provided
between groups. Typical groupings are by function or by physical location (for example, unit assemblies,
subassemblies, printed circuits, integrated circuits, sealed units). Labeled brackets may be used in place of a boundary
line to identify functional groups of symbols if there is sufcient space between groups, so that confusion is unlikely
as to which group any symbol belongs. The dashed line used to indicate shielding also implies that the symbols
enclosed by the dashed line are grouped (see Figs 31 and 32).
5. Logic Conventions and Polarity Indication

5.1 Relationship Between Logic States and Logic Levels
When logic symbols are used to represent physical devices, it is necessary to establish the relationship between logic
states and the nominal values (logic levels) of the physical quantities used to represent these states. There are two
methods by which this may be done:
1)
2)
The use of the symbol for logic negation and requires the adoption of a single logic convention, either
positive or negative, for the whole diagram (see 5.2)
The use of direct polarity indication in which the presence or absence of the logic polarity symbol
indicates the required relationship between logic level and internal logic state at each input and output of
every logic symbol on the diagram (for direct polarity indication, see 5.3).
IEEE STANDARD FOR
5.2 Single Logic Convention

With this method the correspondence between a given external logic state and logic level is the same at all inputs and
outputs on the diagram.
The symbol for logic negation shall be used as required to dene the relationship between the external logic state and
the internal logic state. Specically the presence of the logic negation symbol at an input or output signies that the
internal and external states are the complements of one another for that terminal. The absence of the logic negation
symbol signies that the internal and external states are the same for that terminal. The symbol for logic polarity shall
not be used with this method.
The convention in use, either positive logic or negative logic (see 5.2.1 and 5.2.2), shall be clearly stated on the
diagram or in referenced documentation. This statement can include a useful, small waveform diagram with
indications of the logic states and, if necessary, of the nominal value of corresponding physical quantities.
NOTE Different logic conventions may be used for different parts of the same diagram; for example, on either side of an
interface between contrasting technologies the convention applying to each part should be clearly shown and the
areas of the diagram to which each applies should be clearly delineated.
5.2.1 Positive Logic Convention

For every logic connection, the more positive value of the physical quantity H-level corresponds to the external 1-state.
The less positive value L-level corresponds to the external 0-state. This may be stated on a diagram thus:
See Fig 31 for an example of a diagram using positive logic.

5.2.2 Negative Logic Convention
For every logic connection, the less positive value of the physical quantity L-level corresponds to the external 1-state.
The more positive value H-level corresponds to the external 0-state. This may be stated on a diagram thus:
5.3 Direct Polarity Indication

With this method the relationship between the internal logic state and the external logic level of each input and output
of every logic element is indicated directly by means of the presence or absence of the logic polarity symbol
.
Specically, the presence of the polarity symbol at an input or output indicates that the external low level corresponds
to the internal 1-state for that terminal. The absence of the polarity symbol signies that the external high level
corresponds to the internal 1-state for that terminal. No relationship between an external logic state and either an
internal logic state or an external logic level is dened by the symbol. A relationship between the external logic level
and a signal state is dened only by the signal name (see 8.2.2.1). In this system the symbol for logic negation shall not
be used, except within a symbol outline as permitted by ANSI/IEEE Std 91-1984 .
Direct polarity indication has been called mixed logic implying that both positive and negative logic are present on a
diagram using that method. This is misleading since the xed relationship between logic levels and external logic
states inherent in a single logic convention does not exist with direct polarity indication. Therefore, the term mixed
logic is deprecated.
For diagrams prepared with direct polarity indication but showing no logic polarity symbols, a statement indicating
that direct polarity is employed shall be placed on the diagram or in referenced documentation.
6. Symbols for Devices and Functions

6.1 Standard Symbols
Graphic symbols shall conform to the following applicable standards: ANSI/IEEE Std 91-1984 and ANSI/IEEE Std
315-1975 .
If no suitable standard symbol exists, any special symbol used shall be explained by a note on the diagram.
The use of a symbol in the illustrations of this standard does not preclude the use of alternatives permitted by the
graphic symbol standards.
6.1.1 Symbols for Logic Elements
Each logic element should be shown by the symbol that best depicts actually the logic function performed by the
element in the system. Thus, in Fig 31, the same type of hardware element is represented once by the symbol for an OR
element with negated inputs (designated U4D) and elsewhere by the symbol for AND element with negated output
(NAND) (designated U4B and U4C).
6.1.2 Distributed Connections (Dot-AND, Dot-OR)
The connection of certain logic elements to achieve the effect of an AND or an OR operation without the use of
additional logic elements shall be depicted using the symbols shown in ANSI/IEEE Std 91-1984 .
There are two basic methods for showing the distributed-AND function and two basic methods for showing the
distributed-OR function. In each case, the rst method uses one of the usual methods of showing a junction with the
addition of either a qualifying symbol or a surrounding distinctive-shape symbol to denote the logic performed.
Method 2 replaces the junction with a rectangle containing the & or 1 qualifying symbol appropriate to the AND
or OR function, respectively. This qualifying symbol is followed by the qualifying symbol
indicating that the logic
is performed by a distributed connection instead of by a separate element.
IEEE STANDARD FOR
Method 2 permits the use of qualifying symbols for negated inputs and negated outputs with positive and negative
logic, and for the polarity indicator with direct polarity indication. These are used with the rectangular symbol in the
same manner that they are used if the logic were performed by discrete logic gates with one exception: all the inputs
and the outputs shall show the same qualifying symbol since a distributed connection cannot be inverting.
Method 1 does not lend itself to the use of the input and output qualifying symbols. Therefore, to understand the logic
performed by the distributed connection, it is necessary to consider the types of outputs that are connected together.
L-type open-circuit outputs (for example, n-p-n open collectors) connected together perform either active-high
ANDing or active-low ORing. H-type open-circuit outputs (for example, n-p-n open emitters) connected together
perform either active-high ORing or active-low ANDing. See Fig 2. For denitions of open-circuit outputs, see ANSI/
IEEE Std 91-1984 .
10
Figure 2Distributed Connections
11
IEEE STANDARD FOR
Figure 2Distributed Connections (continued)
12
Figure 2 assumes that the same negation symbols or polarity symbols can be appropriately used at the driving outputs
and the driven inputs. This is the recommended practice; however, sometimes it is not possible to follow this practice
at all points in a diagram. The presence or absence of negated output or active-low output qualifying symbols does not
inuence which type of logic, AND or OR, applies. In Fig 3 the AND and the OR representations are equivalent.
Figure 3Distributed Connections with a Mix of Negated and Unnegated Outputs (Positive Logic
Shown)
The same principle applies for direct polarity indication. In Fig 4 the AND and the OR representations are equivalent.
Figure 4Distributed Connections with a Mix of Active-High and Active-Low Outputs
13
IEEE STANDARD FOR
6.2 Size
In most cases, the meaning of a symbol is dened by its form and contents. The size and the line thickness do not, as
a rule, affect the meaning of the symbol.
In some cases, it may be desirable to use different sizes of symbols to
1)
2)
Emphasize certain aspects, or

Facilitate the inclusion of additional information
Logic symbol size should be governed by the space necessary for internal annotations and the length of the side needed
to accommodate input and output lines at an acceptable spacing. In Fig 5 a binary logic AND element symbol is shown
at the left as specied in ANSI/IEEE Std 91-1984 . The symbol at the right has been increased in size to facilitate the
addition of pin numbers, designations, and other application information.
Figure 5Enlargement of Symbol Outline to Accommodate Application Information

Graphic symbols may be drawn to any proportional size that suits a particular diagram, provided the selection of size
takes into account the anticipated reduction or enlargement. On any printed document, nonlogic symbols should be no
smaller than 0.6 times the size shown in ANSI/IEEE Std 315-1975 . If those symbols are drawn approximately 1.5
times the size shown, the resulting drawings may be reduced as much as 2.5 to 1. Detailed recommendations regarding
the size and proportions of logic symbols may be found in ANSI/IEEE Std 91-1984 .
6.3 Orientation
Symbols or parts of symbols that lend themselves to being rotated or mirror imaged may also be manipulated for
simplication of circuit layout, provided
1)
2)
3)
Proper orientation of lettering is maintained (see 4.5.1),

Signal ow on the resultant diagram is generally from left to right or top to bottom, and
The requirements of ANSI/IEEE Std 91-1984 and ANSI/IEEE Std 315-1975 are met.
The logic symbols contained in ANSI/IEEE Std 91-1984 have been designed for the usual case of inputs on the left
and outputs on the right, and this orientation is preferred.
6.3.1 Orientation of Logic Symbol Lettering
In diagrams where two orientations of the lettering are permitted, all lettering inside a logic symbol including alphanumeric qualifying symbols should be oriented parallel to the predominant direction of the input and output lines on
the symbol. See Fig 6.10
10For
14
special IEC requirements, see Appendix 11..
Figure 6Logic Symbol Orientation Examples for Diagrams that Permit Two Orientations of Text
15
IEEE STANDARD FOR
Figure 6Logic Symbol Orientation Examples for Diagrams that Permit Two Orientations of Text
(continued)
16
6.3.2 Orientation of Qualifying Symbols Derived from Characteristic Curves

If part of a symbol is derived from the characteristic curve of a device, this part of the symbol shall not be rotated.
However, in logic symbols, orientation shall be maintained with respect to the lettering within the symbol. See Fig 7.
Figure 7Orientation of Qualifying Symbols Derived from Characteristic Curves

(See NOTE to Fig 6)
6.4 Application and Identification Information

Identication or detailed references within or adjacent to symbols, other than qualifying symbols, indicator symbols,
and control symbols, are referred to as application information (tagging lines). See Fig 8.
6.4.1 Types of Application Information
Depending upon the kind of logic diagram and its hardware implementation: all, none, or any combination of the types
of application information that follow may be needed.
6.4.1.1 Reference Designation
Reference designations uniquely identify symbols on a diagram and shall be in accordance with ANSI/IEEE Std 2001975 and the applicable portion of ANSI/IEEE Std 315-1975. All letters and digits that make up a reference
designation shall be of the same size and on the same line, with no spaces or hyphens between them. Reference
designations are required on detailed logic circuit diagrams.
All symbols representing elements contained within the same physical package (device) shall carry the same basic
reference designation. If a device is represented by several detached symbols (see 6.8), then each symbol should carry
a different alphabetic sufx to the reference designation.
The examples in this standard conform to the Unit Numbering Method of ANSI/IEEE Std 200-1975 .
17
IEEE STANDARD FOR
6.4.1.2 Element Physical Identification (Type Designation, Reference Number, Part Number, Circuit
Diagram Number, etc)
In the case of highly complex function elements, the logic element physical identication (type designation, type
number) may be provided as part of the symbol function information.
6.4.1.3 Physical Location of Device (In the Assembly)
6.4.1.4 Functional Use (Function of Element in the Particular Circuit)
6.4.1.5 Terminal Identification (Required on Detailed Logic Diagrams)
Terminal identication or pin numbers shall be shown outside of and adjacent to the symbol. They may be placed
adjacent to the connection line or in a break in the connection line. See Figs 9, 10, and 11 for typical examples. If a
single terminal on the symbol represents a multiplicity of physical device terminals, reference shall be made to
supporting information that provides individual terminal identication.
6.4.1.6 Other Information (Such as Values, Stylized Waveforms, and Pulse and Timing
Characteristics)
6.4.2 Application Information Placement
Care shall be exercised to separate application information from qualifying symbols,indicating symbols, and control
designation symbols. Arrangement and meaning of application information should be consistent on a set of drawings,
and should be explained on the diagram or in supporting documentation.
The sequence of application information and identication information should remain the same even if all types of
information are not provided; the lines of application information should be compressed, leaving no blank lines.
6.4.2.1 Logic Symbols
The preferred placement of application and identication information for logic symbols is internal to the symbol. A
suggested arrangement of information is shown in Fig 8 (a), (b), and (c). If the information is shown external to the
logic symbol it shall be placed adjacent to the symbol, and should be in the same sequence as if it were internal to the
symbol.
6.4.2.2 Nonlogic Symbols
Application and identication information for nonlogic symbols shall be placed adjacent to the symbol with the
reference designation on the rst line and the remaining information provided on succeeding lines in the same order as
for logic symbols on the diagram. See Fig 8 (d) for an example.
18
Figure 8Application Information: Typical Examples
6.5 Inputs and Outputs with Multiple Functions

Some logic devices have inputs or outputs that serve more than one function. For example, a terminal may be an input
and an output at different times, or an input may be a clock input and a level-operated control input. Multiple-function
terminals may be depicted in the following ways:
1)
The individual functions may be shown as separate inputs or outputs tied together outside the symbol outline.
19
IEEE STANDARD FOR
Figure 9Multiple-Function Terminal (Terminal 1) Shown as Separate Lines

This method requires that the terminal identication (pin number) be positioned on or adjacent to the
combined circuit path. This location of the terminal identication indicates that the connection is internal to
the device.
2)
If all functions require identical polarity and dynamic symbols and if no ambiguity is likely regarding which
labels apply to the input and output functions, then a single terminal may be shown and a solidus (/) used to
separate the labels associated with the separate functions.
Figure 10Multiple-Function Terminal (Terminal 1) Shown as a Single Line

3)
To simplify a diagram, a multiple-function terminal may be depicted more than once at the symbol outline
with the terminal identication repeated, provided the requirements of 7.4 are met.
Figure 11Multiple-Function Terminal (Terminal 1) Repeated on Symbol Outline

If necessary to identify repetitive information, this may be done by placing the repeated terminal identication in
parentheses or by a special identier explained on the diagram.
20
6.6 Abbreviated Representation of Symbols

6.6.1 Identical Inputs and Outputs
A set of identical inputs to or outputs from an element (inputs or outputs having identical functions and labels) may be
nfor multiple conductors and a single input or output line at the
shown in abbreviated form by using the symbol
element. This technique cannot be used if terminal identiers are required at the symbol.
Figure 12Abbreviated Representation of Identical Inputs and Outputs

6.6.2 Arrays of Identical Elements (See Fig 13.)
n for multiple
An array of identical elements may be indicated in abbreviated form by using the symbol
conductors and the notation mX where m is to be replaced by a number indicating the number of elements in the
array. In the case of logic symbols, this notation shall be placed in the position used for the normal general qualifying
symbol. If this position is already occupied by a general qualifying symbol, then mX shall be placed in front of the
general qualifying symbol.
NOTE Because the elements are identical, the multiple conductors are distributed equally among the elements.
21
IEEE STANDARD FOR
Figure 13Abbreviated Representations of Arrays of Identical Elements

22
6.7 Abutment of Symbols

Logic symbols, whether representing elements in the same or different packages may be abutted according to the rules
of ANSI/IEEE Std 91-1984 provided that
1)
2)
3)
All required application information is shown

All connections external to the devices are shown
Nonexistent internal connections are not implied. See Fig 14.
Figure 14Abutment of Symbols
6.8 Detached Representation of Symbols

Logic symbols may be shown in detached (disassembled) form provided that connections internal to a device are
clearly indicated. See also 6.4.1.1.
Internal connections, if necessary to depict the logical relationships, shall be shown as solid connecting lines. An
internal connection is implied by
1)
2)
3)
The omission of terminal identications at the outline of the separated symbol portion,
Stating IC at the usual terminal identication location, or
Special identiers explained on the diagram or in a reference document
Connecting lines depicting internal connections may be interrupted provided the requirements of 7.4 are met.
23
IEEE STANDARD FOR
Figure 15Detached Representations of Devices
6.9 Unused Terminals and Elements

Terminals or circuit elements that are not used (for example, inputs, outputs, or complete elements in a multipleelement package) may be shown. If shown, terminal identication shall be included. If reserved for a specic future
use, the intended use should be indicated.
Any terminal that, if connected, could adversely affect the circuit shall be shown and labeled11 to warn against use.
6.10 Devices Having a Large Number of Terminals

The depiction of complex devices having very large numbers of terminals (for example, hundreds of pins) may be
impractical using techniques applicable to less complex devices. The following possibilities should be considered:
1)
2)
3)
Break the main complex device outline into parts. Put each part on a separate sheet of the diagram.
Break the main complex device into functional groups and detail each group separately.
Show the main complex device as a reentrant (open-jaw) shape. Place external devices connected between the
terminals of the main device in the reentrant space. Other external connections may be shown around the
outside periphery of the main device.
11Presently
published conventions are:

ANSI Y1.1-1972 (R 1984) None.
IEC Publication 147-OF NU = not usable.
MIL-STD-12 DNU = do not use.
24
4)
5)
Group leads and use the Bus or Data Path symbols where practical.
Tabulate the full details of multilead paths in a separate table.
7. Interconnection of Symbols
7.1 General Requirements
Lines should be drawn horizontally or vertically except in those isolated cases where oblique lines improve the clarity
of the diagram. After arranging the symbols on the diagram for functional clarity and symmetry, connecting lines
should be drawn with as few bends and crossovers as possible.
If a signal feeds a multiplicity of elements, the use of a single straight line with appropriate indications of T-junctions
aids comprehension of the diagram. See Fig 16.
25
IEEE STANDARD FOR
Figure 16Diagram Layout
7.2 Line Spacing

Minimum spacing (center-to-center) between parallel connecting lines, shall be approximately twice the lettering
height if there is lettering between the lines. If there is no lettering between the lines the minimum spacing shall be
equal to the general lettering height used on the diagram. See 4.6 and Appendix 11.. The longer parallel lines shall be
arranged in groups, with approximately double spacing between groups. In determining the grouping, the functional
relationship of the lines should be considered.
7.3 Junctions and Crossovers

All junctions of connecting lines should be shown as T-junctions, as shown in Fig 17(a), or Fig 17(b). When layout
considerations prevent the exclusive use of the T-junction methods of Fig 17(a) or (b), multiple junctions may be
shown as in Fig 17(c). Figure 17(d) illustrates the use of both the no-dot T-junction and multiple-junction methods in
an array of lines if spacing or clarity of presentation precludes the exclusive use of the no-dot T-junction method of
Fig 17(a).
26
Figure 17Junctions and Crossovers
7.4 Interrupted Lines

Complex diagrams with many crossovers or with many elements in series (see Fig 18) may be simplied by breaking
ow lines and providing a cross-reference between the interrupted connections. The cross-reference may be by signal
names, common connection symbols, connection tables, or other unambiguous means. If necessary for clarity,
reference to the locations (on the diagram) of the related common connections shall be provided.
Figure 18Layout Techniques (a) Complex Presentation (b) Alternative Presentation

The same techniques shall be used for common connections between sheets of multiple sheet drawings.
27
IEEE STANDARD FOR
7.5 Grouping of Lines

The recommendations for grouping and omission of lines given in ANSI Y14.15-1966 (R 1973) apply also to lines
representing information ow and connection lines in logic diagrams. The techniques of highway or cable diagrams,
ANSI Y14.15-1966 (R 1973) , can be used to simplify logic diagrams where groups of similar signals are encountered.
For example, binary coded decimal (BCD) lines 1, 2, 4, 8, 10, 20, 40, and 80 could be combined (see Fig 19), provided
that the individual lines are properly identied at both ends.
Figure 19Grouping of Lines
7.6 Polarity and Negation Matching

The symbols used in an application usually are chosen so that the polarity or negation indication at an input is the same
as that at the source of a signal feeding that input. If this is done, a reader of the diagram can directly apply the internal
logic state of an output as the internal logic states of the inputs fed by that output. In the case of direct polarity
indication, if the form of the signal name is chosen as described in 8.2.2.2 the signal name, excluding the level
indication, directly expresses the meaning of that internal logic state.
However, it is not always possible to choose symbols so that all the inputs and outputs connected by a signal carry the
same polarity or negation indication. If there is a mismatch between the indication at the source of a signal and the
indication at the destination, a reader of the diagram must invert the internal logic state of the source before using it as
the internal logic state of the next input. Because these mismatches are a common source of errors in logic circuit
design, it can be helpful to clearly indicate where such mismatches (and inversions) intentionally exist. If it is desired
to highlight these mismatches, it should be done using a short perpendicular line (the mismatched symbol) across the
connecting line.
28
This symbol divides the connection into two segments each of which contains consistent polarity or negation
indicators. If the connecting line is branched, one or more symbols should be used to divide the connection tree into
consistent subtrees.
7.7 Power Connections

Power connections (voltage requirements) to logic devices shall be specied on detailed logic diagrams. Normally
connections to logic device power terminals (for example, VCC, VBB, GND) are not shown graphically but are
specied in a table or a note.
8. Labeling of Connecting Lines

8.1 General
Labeling of connecting lines can greatly promote the understanding of a diagram and facilitate the maintenance of a
logic system, provided that the lines are labeled intelligently and that names are chosen carefully, based on system
functions. Each label should be shown adjacent to the line to which it applies or within a break in that line.
8.2 Names for Logic and Analog Signals

Signal names are used to uniquely identify sets of points that are electrically interconnected without intervening
devices.
8.2.1 General Requirements
Signal names should be concise, informative, and unambiguous.
29
IEEE STANDARD FOR
8.2.1.1 Descriptive Requirements

Signal names should indicate the function performed by the signal or the particular information carried. Every effort
should be made to use mnemonic names (see Appendix A) and standard abbreviations (see ANSI Y1.1-1972 (R 1984)
. The mnemonics and abbreviations used should be explained on the diagram or in supporting documentation. If space
permits, easy-to-understand mnemonics should be used instead of overly short abbreviations. For example, SELDEV1
better conveys the meaning SELECT DEVICE 1 than does SD1. For other examples see Figs 20, 31, and 32.
Signals should be named based on the function they perform rather than on the signals that are used to generate them.
If a signal PRUN is gated with a second signal TP6 to produce a signal that sets a bistable element called RUN, then
its function is obvious if the output signal is named SETRUN. However, if the output signal is named PRUNTP6, then
its function is open to speculation. See Fig 20, Example (a).
NOTE Mnemonics and abbreviations based on typical usage in the English language cannot all be translated without risk of
confusion.
8.2.1.2 Recommended Characters

Signal names should be composed from standard character sets, excluding lowercase letters. Single embedded spaces
may be used where necessary. To maintain compatibility with computer processing, it is recommended that character
sets be restricted to12
(1) Capital letters
A to Z
(2) Digits
0 to 9
(3) Negation characters
-~
(4) Special characters
! " % & ' () * + , - . / : ; < = >

? ^
8.2.1.3 Length
Practical considerations and design automation systems usually place limits on the allowable length of signal names.
Therefore, it is recommended that a maximum length of 24 characters be mutually supported by designers and designautomation systems.
8.2.1.4 Similar and Equivalent Signals
Identical names shall not be applied to different signals, no matter how similar the functions. A signal name shall be
altered whenever the signal is amplied, inverted, gated with another signal, delayed, chopped, stored, or changed in
any way. This change may take the form of an addition of a suitable sufx to the signal name so as to construct a new
signal name. For example see Fig 20, Examples (d) and (f).
If the same signal is generated more than once, is amplied, or is level shifted, then each occurrence or variation of the
basic signal should have the same basic name modied by the addition of a different serial number or letter sufx. The
serial number or letter may be concatenated with the basic name or separated from it by a space. For example, if the
signal STOP drives two ampliers, the outputs of those ampliers may be labeled STOP1 and STOP2. For example,
see Fig 20, Example (f).
12ISO
646-1983 , 7-bit Character Set (International Reference Version (except for ).

ANSI X3.4-1977, 7-bit Character Set (except for - ).
30
Figure 20Examples of Signal Name Allocation

31
IEEE STANDARD FOR
If a binary logic signal is simply inverted, then the inverted signal should have the same basic name as the uninverted
signal, modied by the addition (or deletion) of negation bars (or other negation indication). On diagrams using direct
polarity indication, the indicated signal level (see 8.2.2.2) may be changed instead. If a signal is inverted more than
once, serial numbers or letters should be used to distinguish different inverted or uninverted versions of a signal.
8.2.2 Binary Logic Signals
Binary logic signals are signals having only two states, represented by two nonoverlapping ranges of physical values
for the signal. These two ranges are called levels.
8.2.2.1 Signal State
For binary logic signals, the signal name should include an abbreviation of a statement or expression that is either true
or false. For example, the name ALARM is an abbreviation of the statement ALARM IS ACTIVE. A signal name shall
not contain an inherent contradiction. The name ON/OFF consists of two parts, and when one part is true the other is
false. Such a signal name is ambiguous and might seem to imply a statement that is always true.
The truth value obtained from evaluating the statement or expression represented by the signal name is called the
signal state.
The true value of a statement represented by the signal name corresponds to the 1-state of the signal. The false value
of a statement represented by the signal name corresponds to the 0-state of the signal. For example, the signal name
ALARM means that ALARM IS ACTIVE is true when the signal is in its 1-state and false when the signal is in its 0state. See Table 1, rows 1 and 2.
Table 1Relationships Among States and Signal Names (Single Logic Convention)
Relationship Defined by
Presence or Absence of
Negation Symbol
Row
1
Input (or Output)
Signal State
(TruthValue)
External
Logic State
Internal Logic
State
alarm
no alarm
true=1
false=0
1
0
1
0
alarm
no alarm
true=1
false=0
1
0
0
1
alarm
no alarm
false=0
true=1
0
1
0
1
alarm
no alarm
false=0
true=1
0
1
1
0
System
Condition
NOTES:
1The signal state being true always corresponds to the external logic state being 1.
2The signal state being false always corresponds to the external logic state being 0.
32
8.2.2.1.1 Negated Signals

Signal names that embody an inherent negative, such as NORUN, are difcult to understand. It requires some mental
somersaults to say whether the corresponding statement NORUN IS ACTIVE is true or false. If possible, such signal
names should be made inherently true. For example, STOP or HALT could be substituted for NORUN.
However, sometimes an action should take place when a certain statement, or expression, is not true. The preferred
method of indicating negation of a signal name is to place a negation bar over the portion of the name representing the
expression to be negated. For example, RUN corresponds to the statement RUN IS NOT ACTIVE. Note that the signal
name includes the negation bar. The signal name RUN means that RUN IS NOT ACTIVE is true when the signal is in
its 1-state and false when the signal is in its 0-state. This further implies that RUN IS ACTIVE is true when the signal
RUN is in its 0-state and false when the signal RUN is in its 1-state. See Table 1, rows 3 and 4.
If an in-line notation for negation is required, then the negation bar may be replaced by a preceding mathematical
13 or a different notation explained on the diagram or in supporting documentation, for
symbol for logic negation
example
RUN. If confusion is likely regarding which portion of the signal name is negated, that portion of the
signal name to be negated shall be enclosed in parentheses with the negation symbol placed immediately following the
opening parenthesis, subject to the following rule:
The in-line negation symbol applies to the string to the right of the symbol up to the rst occurrence of
1)
2)
3)
An unmatched closing parenthesis,

A solidus that is itself not enclosed within a matching set of parentheses to the right of the negation symbol,
or
The end of the string.
For example
The tilde (~) may be substituted for the symbol for logic negation on computer systems not having the logic negation
symbol
as part of their character sets.
8.2.2.1.2 Arithmetic and Logical Expressions

The plus sign (+) denotes algebraic addition and the minus sign (-) denotes algebraic subtraction; for example, AR+1
may be the mnemonic for ADDRESS REGISTER PLUS 1.
In signal names the plus sign (+) should be used to denote the OR function only if no confusion with algebraic addition
is likely. If the content does not clarify the distinction, an often used solution is to substitute the words OR or PLUS as
appropriate in one or both of the cases.
13ISO
31/1-1978 , Symbol 11-2.3.
33
IEEE STANDARD FOR
A logic AND function may be denoted by a dot (), an asterisk (*), or, if no confusion is likely, by normal juxtaposition.
For example, ENABLE may be the mnemonic for ENABLE A ANDed with BLOCK E; PQ may mean P ANDed with
Q. See also 8.2.1.1.
Parentheses may be used to clarify expressions. For example, (ENA)BLE is another way to indicate the mnemonic for
ENABLE A ANDed with BLOCK E.
8.2.2.1.3 Bus Signals and Other Grouped Signals
Bit and byte labeling within a bus or other set of grouped signals should include a numeric sufx to the bus or group
name. For buses or groups with an inherent weighting of the signals within, the numeric sufxes should represent the
actual weights of the signals, all of which are consistently expressed either as decimal numbers or as exponents of the
powers of 2. The numeric sufx may be enclosed in angle brackets.14 For example, the 32 lines of an intermediate
register may be labeled IRBUS<1> to IRBUS<2147483648>, or IRBUS<00> to IRBUS<31>. A seven line BCD
intermediate register should be labeled IRBUS<1>, IRBUS<2>, IRBUS<4>, IRBUS<8>, IRBUS<10>, IRBUS<20>,
IRBUS<40>.
Connecting lines representing entire buses, rather than individual signals within them may be labeled as follows:
IRBUS<0:31> IRBUS<0>, IRBUS<1>, ..., IRBUS<31>
IRBUS<1,2,4,8,10,20,40> IRBUS<1>, IRBUS<2>, IRBUS<4>, ..., IRBUS<40>
If any other convention is used, and the meaning is not obvious, it shall be explained on the diagram or in supporting
documentation.
For clarity, weighting of individual bits of a bus shall be indicated either in the symbol elements or with the connecting
lines. IEC Publication 113-7 (1971-1983) states that connecting lines for buses should be ordered proceeding from
least signicant to most signicant, from top to bottom, or from left to right. This is the normal result of using logic
symbols for weighted arrays having a common control block on the top or left of the symbol.
8.2.2.1.4 Clock Signals
In signal names for clocks, it is often helpful to include important characteristics such as period (or frequency) and
phase. For example, if the basic clock period is 25 ns, the mnemonic might be CP25N. Clocks derived from the basic
clock might then be termed CP50N, CP100N, and so on.
The timing pulses from CP50N might be designated as indicated in Fig 21.
8.2.2.2 Signal Level
In detailed logic diagrams employing a single logic convention (positive or negative logic), the relationship between
the external logic states of the signals and the corresponding logic levels is xed. For example, if the positive logic
convention is in force, the 1-state of a signal (the true state of the signal name) always corresponds to the H-level. For
the negative logic convention, the 1-state always corresponds to the L-level.
14
Angle brackets can be formed from the less than (<) and greater than (>) characters.
34
Figure 21Clock and Timing Pulses

In detailed logic diagrams employing direct polarity indication, the logic symbols do not imply any external logic
state, only logic levels. Therefore, each logic signal name should include an indication of which logic level
corresponds to the 1-state (true state) of the signal. The preferred method for doing this is to place an indication of that
logic level (for example, H or L) within parentheses at the end of the signal name.
EXAMPLES:
ALARM(H) means ALARM IS ACTIVE is true when the logic level of the signal is high and is false when the logic
level is low.
ALARM (H) means ALARM IS NOT ACTIVE is true when the logic level is high and is false when the logic level is
low. This further implies that ALARM IS ACTIVE is true when the logic level of the signal is low and false when the
logic level is high. See Table 2 for all combinations.
STOP(L) means STOP IS ACTIVE is true when the logic level of the signal is low and is false when the logic level is
high.
A signal whose true state corresponds with a high level may be referred to as a true-when-high signal.
A signal whose true state corresponds with a low level may be referred to as a true-when-low signal.
If all signal names on a diagram are true when high, the logic level indications may be omitted from the names.
35
IEEE STANDARD FOR
Table 2Relationships Among States, Levels, and Signal Names (Direct Polarity Indication)
Relationship Defined by
Presence or Absence of
Negation Symbol
Row
Input (or Output)
Signal State
(TruthValue)
External
Logic State
Internal Logic
State
alarm
no alarm
true=1
false=0
H
L
1
0
alarm
no alarm
true=1
false=0
L
H
1
0
alarm
no alarm
true=1
false=0
L
H
0
1
alarm
no alarm
true=1
false=0
H
L
0
1
alarm
no alarm
false=0
true=1
L
H
0
1
alarm
no alarm
false=0
true=1
H
L
0
1
alarm
no alarm
false=0
true=1
H
L
1
0
alarm
no alarm
false=0
true=1
L
H
1
0
System
Condition
NOTES:
1 The signal state being true corresponds to the external logic level being that level specied in the signal
name.
2 The signal state being false corresponds to the logic level being the opposite of the level specied in the
signal name.
A signal name that can be derived by applying both logic negation and level inversion to an existing signal name is
equivalent to the existing signal name and therefore shall not be used to identify a different signal. For example:
STOP(L) = STOP(H)
ALARM(H) = ALARM(L)
RD/WR(H) = RD/WR(L)
36
To reduce the amount of mental translation necessary in interpreting a logic diagram, usually the signal name is
constructed so that its level indication agrees with the polarity indication at the source of the signal.
Signal names on connections with mismatched polarity indications (see 7.6) should be consistent with the polarity
indications on the portion of the connecting line where the signal name is shown.
8.2.3 Analog Signals

Analog signals have a continuous range of possible physical values. Names for analog signals should convey the
variable or function represented by the signal.
8.3 Names for Power and Other Constant-Level Connections

Constant-level connections, such as power supply connections, should be named according to the value of the physical
quantity they carry. This can be either a numerical value with a unit of measure or a commonly understood
abbreviation that implies a nominal numerical value and may also imply a tolerance to other additional properties. For
example, a ground connection may be named 0.0 V or GND. A TTL supply voltage connection may be named +5.2 V
or VCC. All of the rules of 8.2 through 8.2.1.5 also apply to constant-level connections.
8.4 Locator Information

Locator information is information in addition to the connection names that aids in locating the connections, or other
information about the connections in the documentation or on the device itself. This may include documentation crossreferences and physical-access information. Conventions used for locator information should be explained on the
diagram or in supporting documentation.
37
IEEE STANDARD FOR
8.4.1 Cross-Reference Information

Labels may include additional information that assists in locating other places on the diagram where a signal or
connection is represented, including sources, destinations, and drawing coordinates. They may also include
information used to identify a signal or connection in other documents, including computer-processed or computergenerated documents.
8.4.2 Physical Access Information
Labels and symbols may be associated with a signal or connection for the purpose of explaining how and where the
signal or connection may be accessed on the nished device (for example, test points).
8.5 Additional Properties and Characterization

Additional information that claries the operation, appearance, maintenance, or adjustment of a signal or constantlevel connection may also be included (see also Section 9.).
9. Supplementary Information
9.1 Reference-Designation Accounting
If the class-code, sequential-numbering, reference designation system is used and items are eliminated as a result of a
revision, remaining items need not be renumbered. For circuits showing many items, a table may be used to show
which numbers are not used and the highest numerical reference designations, as shown in Fig 22. This table may
include any or all types of items and shall be located conveniently near notes or other tabular information.
Figure 22Typical Table Indicating Omitted and Highest Numerical Reference Designations
9.2 Diagram Notes

Notes may be used on diagrams to
1)
2)
3)
4)
5)
38
Consolidate repetitious information

Explain abbreviations
Specify standards and conventions upon which the diagram is based
Specify supporting documentation
Otherwise augment the circuit diagram
These notes may be consolidated in one location or placed near their point of application.
9.2.1 General Notes
General notes usually apply to the entire drawing and are grouped together. They often include or may be preceded by
the words, UNLESS OTHERWISE SPECIFIED.
9.2.2 Local Notes
A local note is one that is placed near to and is clearly associated with a specic diagram detail.
9.2.3 Referenced (Indexed) Notes
Referenced notes are usually grouped together with the general notes. However, referenced notes apply to one or more
of the diagram details and are referred to by local notes that state, for example, SEE NOTE 15. Referenced notes
should be used if
1)
2)
3)
The note invokes or references another document,

The identical note applies at several locations on the diagram, or
The note is lengthy and placing it at the point of application reduces clarity or tends to crowd other
information.
9.2.4 Examples
The following examples are typical of the kinds of information that should be considered when preparing NOTES.
a)
b)
c)
d)
FOR ASSEMBLY, SEE (drawing number).

FOR WIRING INFORMATION, SEE (document number).
FOR TEST SPECIFICATION, SEE (document number).
UNLESS OTHERWISE SPECIFIED, RESISTANCE VALUES ARE IN OHMS (W), PLUS OR MINUS
(tolerance) %, (power rating) W.
e) UNLESS OTHERWISE SPECIFIED, CAPACITANCE VALUES ARE IN MICROFARADS (mF), PLUS OR
MINUS (tolerance) %, (voltage rating) V.
f) UNLESS OTHERWISE SPECIFIED, INDUCTORS ARE (value) MICRO-HENRIES (mH), PLUS OR
MINUS (tolerance) %.
g) UNLESS OTHERWISE SPECIFIED, TRANSISTORS ARE (type disignation).
h) UNLESS OTHERWISE SPECIFIED, DIODES ARE (type designation).
i) TERMINAL NUMBERS ARE NOT NECESSARILY MARKED ON PARTS. SEE ASSEMBLY
DRAWING FOR TERMINAL LOCATIONS.
j) ROTARY DEVICES ARE VIEWED FROM THE FRONT WITH KNOB IN EXTREME CCW POSITION.
k) (State convention) DENOTES LOWERCASE LETTERS.
l) PARTIAL REFERENCE DESIGNATIONS ARE SHOWN. FOR COMPLETE DESIGNATION, PREFIX
WITH (show all of the reference designations that apply to the subassemblies or assemblies within which the
item is located including the highest level required to designate the item uniquely).
m) NOMENCLATURE ENCLOSED IN A RECTANGLE IS A FRONT-PANEL MARKING.
n) ALL WAVEFORMS ARE IDEALIZED.
o) ABBREVIATIONS CONFORM TO (state document).
p) (Insert TERMINALS or CONTACTS) SHOWN WITHOUT CONNECTION ARE SPARES.
q) DNU INDICATES (insert TERMINALS or CONTACTS) TO WHICH CONNECTION SHALL NOT BE
MADE.
r) (Starting reference designation) THROUGH (last reference designation in the series) ARE IDENTICAL
COMPONENTS CONNECTED IN PARALLEL.
s) PREPARED IN ACCORDANCE WITH ANSl/IEEE Std 991-1985 .
t) LOGIC SYMBOLS CONFORM TO ANSI/IEEE Std 91-1984 .
39
u)
v)
IEEE STANDARD FOR
(Specify POSITIVE or NEGATIVE) LOGIC CONVENTIONS APPLY.

DIRECT POLARITY INDICATION APPLIES.
9.3 Tabular Information

A logic diagram may be supplemented by other information such as:
1)
2)
3)
Truth tables or function tables

Tables containing information on components and packaged elements used to implement functions
Tables providing information on signal source, destination, etc
9.4 Waveforms
9.4.1 Use
Waveforms shall be shown where required for testing, adjustment of the circuit, or clarication of the circuit function.
Waveforms may be required to show the waveshape or the timing relation of the wavetrain.
Waveforms or their stylized representation should be oriented as they appear on an oscilloscope or other device
normally used to view a waveform.
9.4.2 Stylized Waveforms
Unless otherwise required for the application, waveforms may be shown in a stylized manner; for example, an
approximation of the actual waveshape, with sharp corners and omitting signicant trailing edges or spikes (see
Fig 23).
Narrow pulses may be represented by a single line if representation of the pulse duration is not essential.
40
Figure 23Stylized Waveforms

Waveforms may be shown adjacent to a line or, if not confusing, may use the signal line as the x-axis, as shown in
Fig 24.
Figure 24Typical Waveforms for Signal Lines

9.4.3 Simplified Waveform Notations
The time of occurrence of a pulse, or the beginning and ending times of a pulse train, or of a level may be indicated in
a simplied manner as shown in Fig 25.
41
IEEE STANDARD FOR
Figure 25Simplified Waveform Notations
9.5 Diagram Simplification and Abbreviation Techniques

Diagram simplication and abbreviation techniques may be used, for example, to reduce preparation effort, increase
amount of information shown per diagram sheet, or reduce clutter by eliminating repetitive details. In general, any
abbreviation method may be used that does not impair understanding of the diagram and that maintains the continuity
of signals within the diagram. If simplication or abbreviation techniques are employed, they should be explained on
the diagram or in supporting documentation unless they are self-explanatory.
The following paragraphs provide typical examples of some simplication and abbreviation techniques.
9.5.1 Repeated Symbol Simplification
If a logic symbol for a specic device is shown two or more times on a diagram, the fully delineated symbol need be
shown only once. The repeated appearances may be represented by a simplied symbol.
42
The simplied symbol shall be a rectangle and contain all relevant application and identication information. It shall
also include an appropriate reference to the fully delineated symbol. A rectangular box shall be added outside, at the
upper-left corner of the fully delineated symbol, to contain a unique reference identication. The same reference
identication shall be shown in a rectangular box located at the inside, at the upper-left corner of each corresponding
simplied symbol. If on a single sheet only one fully delineated symbol is used for a specic device, the device type
is sufcient reference for repeated appearances of that device on that sheet. If more than one sheet of a multisheet
diagram is involved, a sheet cross-reference to the fully delineated symbol shall be shown in the lower-left corner of
the repeated pattern enclosure.
Individual inputs and outputs of the simplied symbols shall include appropriate references to the corresponding
inputs and outputs on the fully delineated symbol. If there are no terminal identiers (for example, in a basic logic
diagram) or other corresponding internal labels, the arrangement of inputs and outputs in the simplied symbol must
be the same as in the fully delineated symbol (the arrangement provides the cross reference). Otherwise, the individual
inputs and outputs must have appropriate cross-references provided.
If there are identical terminal identiers on both symbols, the terminal identiers, not their arrangement, provide the
cross-reference. However, it is recommended that the terminal arrangement still be the same. See Fig 26.
43
IEEE STANDARD FOR
Figure 26Repeated Symbol Simplification

9.5.2 Repeated Circuit Patterns
If a portion of circuitry is used repeatedly in the same diagram, only one complete delineation is necessary. All
additional applications may be shown in simplied form. Both theoriginal pattern and the repeated-patterns shall be
enclosed in solid single-line boxes. The repeated-pattern enclosures shall be drawn only as large as required since
circuit detail is omitted. If more than one sheet of a multisheet diagram is involved, a sheet cross-reference to the fully
delineated pattern shall be shown in the lower-left corner of the repeated-pattern enclosure. Connections to repeated
circuit patterns shall be arranged in the same order and direction as shown on the fully delineated circuit pattern.
Otherwise, the connections shall include appropriate references to the corresponding connections of the fully
delineated circuit pattern.
A unique identication shall be assigned to each different circuit pattern. The same circuit pattern identication shall
be assigned to all like patterns in a diagram. The identication shall be shown in a rectangle located at the upper-left
corner of both the fully delineated and the repeated patterns.
Any differences within the repeated pattern from the original in designations, values, or wiring shall be clearly
indicated in the succeeding repeated-pattern enclosures. A hierarchy of repeated patterns may be used if needed, for
example, repeated patterns within repeated patterns. See Fig 27 for an example of repeated patterns.
44
Figure 27Typical Diagram Sheet with Repeated Circuit Pattern
45
IEEE STANDARD FOR
Figure 27Typical Diagram Sheet with Repeated Circuit Pattern (continued)
46
9.5.3 Connection Paired with Ground

If signal connections are paired with a ground connection and full delineation of the paired connections may result in
a cluttered diagram, a simplied, single line representation may be used as shown in Fig 28. The letters PG indicate
that the connection or connection segment is paired with ground. The ground connection termination pin number is
shown in brackets [].
NOTES:
1 Terminal numbers shown in square brackets [] are ground pair termination pins.
2 The letters PG indicate connections that are paired with ground.
Figure 28Single Line Representation of Connections that are Paired with Ground
9.5.4 Circuit Layout Condensation
Many different techniques may be used to condense or reduce complex circuit representation. For example, a series of
similar connections may be shown in tabular form. In Fig 29, an example of one method, symbols for printed wiring
board (PWB) assemblies CP FB235, CP FA1110, and CP FA1111 are shown once, but represent ve groups of these
PWB symbols and their interconnections with a single PWB (CP FA1134) symbol. In this gure, the four symbols
supported by the table and notes represent connections among sixteen symbols.
47
IEEE STANDARD FOR
Figure 29Example of Circuit Layout Condensation
48
Figure 29Example of Circuit Layout Condensation (continued)
10. Examples of Logic Diagrams

Figures 30, 31, and 32 illustrate the application of the principles given in this standard. To facilitate comparison
between the different types of logic diagrams, the same part of a circuit, that is, a timing-pulse generator, is shown in
each of the gures. An explanation of the signal names used in these gures would normally appear in supporting
documentation. In the examples, the power-supply connections to the logic elements have been omitted.
In Fig 30, symbols for logic functions are used to show the conditions that start and stop the oscillator. This basic logic
diagram shows the conceptual principles of the circuit rather than the actual implementation. Also, the actual logic
levels available and produced for each signal may be different from those shown. A block symbol is used for the
frequency divider (changer).
49
IEEE STANDARD FOR
Figure 31 is an example of a detailed logic diagram using the positive-logic convention. This convention, which is
stated in a note on the diagram, establishes the relationship between logic levels and external logic states so that the
logic function and the physical function are represented by the diagram. Note that several of the logic symbols of Fig
30 (for example, the single shot) have been replaced by symbols or devices and associated connections that represent
the actual implementation.
Figure 32 is an alternative example of a detailed logic diagram using direct polarity indication. The exact logic levels
are stated in a note on the diagram.
50
Figure 30Basic Logic Diagram for a Timing-Pulse Generator
51
IEEE STANDARD FOR
Figure 31Detailed Logic DiagramUsing the Positive Logic Convention
52
Figure 31Detailed Logic Diagram Using the Positive Logic Convention (continued)
53
IEEE STANDARD FOR
Figure 32Detailed Logic Diagram Using Direct Polarity Indication
54
Figure 32Detailed Logic Diagram Using Direct Polarity Indication (continued)
55
IEEE STANDARD FOR
Figure 33One Sheet of a Typical Circuit Diagram (Direct Polarity Indication)
56
Figure 33One Sheet of a Typical Circuit Diagram (Direct Polarity Indication) (continued)
57
IEEE STANDARD FOR
Figure 34One Sheet of a Typical Circuit Diagram (Positive Logic Convention)
58
Figure 34One Sheet of a Typical Circuit Diagram (Positive Logic Convention) (continued)
59
IEEE STANDARD FOR
Annex A Mnemonics for Use in Signal Names

(Informative)
Table A-1 is an effort to encourage uniformity in signal names. This table necessarily cannot be exhaustive, but
suggests mnemonics for some of the more common terms used to construct signal names. If necessary, other meanings
may be assigned to the mnemonics listed and other mnemonics may be assigned to the descriptions, if no ambiguity
results.
No set of rules can avoid the necessity for the designer to exercise good judgment and for the user to know how to
interpret the signicance of signal names.
The examples given in the following table represent typical usage in the English language. They cannot all be
translated into other languages without risk of confusion.
Table A-1Signal NamesAlphabetically by Mnemonic
Mnemonic
Meaning
A
ACC
Accept
ACC
Accumulator
ACK
Acknowledge
ACT
Activate
ADD
Adder
ADR
Address
ALI
Alarm Inhibit
ALU
Arithmetic Logic Unit
ASYNC
Asynchronous
B
BCD
Binary-Coded Decimal
BCTR
Bit Counter
BG
Borrow Generate
BI
Borrow Input
BIT
Bit
BLK
Block
BO
Borrow Output
BP
Borrow Propagate
BUF
Buffer, Buffered
BUS
Bus
BUSY
Busy
BYT
Byte
C
60
Mnemonic
Meaning
CRY
Carry
CE
Chip Enable
CHK
Check
CI
Carry Input
CK
Clock
CLK
Clock
CLR
Clear
CMD
Command
CNT
Count
CNTL
Control
CO
Carry Output
COL
Column
COMP
Compare
CORR
Corrected
CP
Carry Propagate, Compare
CPU
Central Processing Unit
CRC
Cycle Redundancy Check
CS
Chip Select
CTR
Counter
CYC
Cycle
D
Data
DEC
Decimal
DEV
Device
DIS
Disable
DISK
Disk, Disc
DLY
Delay
DMA
Direct Memory Access
DRAM
Dynamic Ram
DRV
Driver
DWN
Down
E
EN
Enable
END
End
EOF
End of File
61
IEEE STANDARD FOR
Mnemonic
Meaning
EOL
End of Line
EOT
End of Tape, End of

Transmission
ERS
Erase
ERR
Error
EXOR
Exclusive OR
EXT
External
F
FF
Flip-Flop
FIFO
First In - First Out
FLD
Field
FLT
Fault
FNC
Function
G
Gate
GEN
Generate
GND
Ground
H
HEX
Hexadecimal
HLD
Holding
HORZ
Horizontal
I
ID
Identification
IN
In, Input
INH
Inhibit
INT
Internal, Interrupt
INTFC
Interface
INTRPT
Interrupt
I/O
Input/Output
IRQ
Interrupt Request
K
KYBD
Keyboard
L
62
LCH
Latch, Latched
LD
Load
Mnemonic
Meaning
LFT
Left
LOC
Location
LRC
Longitudinal Redundancy
Check
LSB
Least Significant Bit
LSBYT
Least Significant Byte
LT
Light
M
MAR
Memory Address Register
MEM
Memory
MOT
Motor
MPX
Multiplex
MSB
Most Significant Bit
MSBYT
Most Significant Byte
MSK
Mask
STR
Master
MTR
Motor
MULT
Multiply, Multiplier
N
NACK
Negative Acknowledge
NEG
Negative
NC
Normally Closed
NO
Normally Open
O
OCT
Octal
OFF
Off
ON
On
OUT
Out, Output
OVFL
Overflow
P
PAR
Parity
PC
Program Counter
PCI
Program-Controlled
Interrupt
PE
Parity Error
63
IEEE STANDARD FOR
Mnemonic
Meaning
POS
Positive
PROS
Process, Processor
PRGM
Program
PU
Pull-Up
PWR
Power
R
RAM
Random Access Memory
RCVR
Receiver
RD
Read
RDY
Ready
REG
Register
REJ
Reject
REQ
Request
RES
Reset
RFSH
Refresh
ROM
Read Only Memory
ROW
Row
RST
Restart
RT
Right
RTN
Return
RTZ
Return to Zero
S
64
SEL
Select
SET
Set
SFT
Shift
SIM
Simulation
SLV
Slave
SPLY
Supply
SRQ
Service Request
START
Start
STAT
Status
STDBY
Standby
STK
Stack
STOP
Stop
STRB
Strobe
Mnemonic
Meaning
SW
Switch
SYNC
Synchronization
SYS
System
T
TERM
Terminate, Terminal
TG
Toggle
TRIG
Trigger
TST
Test
U
UP
Up
UTIL
Utility
V
VERT
Vertical
VID
Video
VIRT
Virtual
VLD
Valid
W
WR
Write
WRD
Word
X
XCVR
Transceiver
XMIT,
XMT
Transmission, Transmit
XMTR
Transmitter
XOR
Exclusive OR
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IEEE STANDARD FOR
Table A-2Signal NamesAlphabetically by Meaning

Term Meaning
Mnemonic
A
Accept
ACC
Accumulator
ACC
Acknowledge
ACK
Activate
ACT
Adder
ADD
Address
ADR
Alarm Inhibit
ALI
Arithmetic Logic Unit
ALU
Asynchronous
ASYNC
B
Binary
BIN
Binary-Coded Decimal
BCD
Bit
BIT
Bit Counter
BCTR
Block
BLK
Borrow Generate
BG
Borrow Input
BI
Borrow Output
BO
Borrow Propagate
BP
Buffer
BUF
Buffered
BUF
Bus
BUS
Busy
BUSY
Byte
BYT
C
66
Carry
CRY
Carry Generate
CG
Carry Input
CI
Carry Output
CO
Carry Propagate
CP
Central Processing Unit
CPU
Check
CHK
Chip Enable
CE
Term Meaning
Mnemonic
Chip Select
CS
Clear
CLR
Clock
CLK, CK
Column
COL
Command
CMD
Compare
COMP, CP
Control
CNTL
Corrected
CORR
Count
CNT
Counter
CTR
Cycle
CYC
Cycle Redundancy Check
CRC
D
Data
Decimal
DEC
Delay
DLY
Device
DEV
Direct Memory Access
DMA
Disable
DIS
Disc
DISK
Disk
DISK
Down
DWN
Driver
DRV
Dynamic Ram
DRAM
E
Enable
EN
End
END
End of File
EOF
End of Line
EOL
End of Tape
EOT
End of Transmission
EOT
Erase
ERS
Error
ERR
Exclusive OR
EXOR
External
EXT
67
IEEE STANDARD FOR
Term Meaning
Mnemonic
F
Fault
FLT
Field
FLD
First In - First Out
FIFO
Flip-Flop
FF
Function
FNC
G
Gate
Generate
GEN
Ground
GND
H
Hexadecimal
HEX
Holding
HLD
Horizontal
HORZ
I
Identification
ID
In
IN
Inhibit
INH
Input
IN
Input/Output
I/O
Interface
INTFC
Internal
INT
Interrupt
INTRPT
Interrupt Request
IRQ
K
Keyboard
KYBD
L
68
Latch
LCH
Latched
LCH
Least Significant Bit
LSB
Least Significant Byte
LSBYT
Left
LFT
Light
LT
Load
LD
Location
LOC
Term Meaning
Longitudinal Redundancy
Check
Mnemonic
LRC
M
Mask
MSK
Master
STR
Memory
MEM
Memory Address Register
MAR
Most Significant Bit
MSB
Most Significant Byte
MSBYT
Motor
MOT, MTR
Multiplex
MPX
Multiply
MULT
Multiplier
MULT
N
Negative
NEG
Negative Acknowledge
NACK
Normally Closed
NC
Normally Open
NO
O
Octal
OCT
Off
OFF
On
ON
Out
OUT
Output
OUT
Overflow
OVFL
P
Parity
PAR
Parity Error
PE
Positive
POS
Power
PWR
Process
PRCS,
PROC
Processor
PRCS,
PROC
Program
PRGM
Program Counter
PC
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IEEE STANDARD FOR
Term Meaning
Mnemonic
Program-Controlled
Interrupt
PCI
Pull-Up
PU
R
Random Access Memory
RAM
Read
RD
Read Only Memory
ROM
Ready
RDY
Receiver
RCVR
Refresh
RFSH
Register
REG
Reject
REJ
Request
REQ
Reset
RES
Restart
RST
Return
RTN
Return to Zero
RTZ
Right
RT
Row
ROW
S
70
Select
SEL
Service Request
SRQ
Set
SET
Shift
SFT
Simulation
SIM
Slave
SLV
Stack
STK
Standby
STDBY
Start
START
Status
STAT
Stop
STOP
Strobe
STRB
Supply
SPLY
Switch
SW
Synchronization
SYNC
Term Meaning
System
Mnemonic
SYS
T
Terminal
TERM
Terminate
TERM
Test
TST
Toggle
TG
Transceiver
XCVR
Transmission
XMIT
Transmit
XMT
Transmitter
XMTR
Trigger
TRIG
U
Up
UP
Utility
UTIL
V
Valid
VLD
Vertical
VERT
Video
VID
Virtual
VIRT
W
Word
WRD
Write
WR
71
IEEE STANDARD FOR
Annex B Lines and Lettering Size and Spacing

(Informative)
B.1 Introduction
The legibility of a diagram depends heavily on the quality and dimensions of the lines and lettering. Lettering and line
size, and spacing on an original document must take into account the various media to be used throughout the
document generation and distribution process, the processes and equipment employed during reproduction, and the
degree of enlargement or reduction at various stages in the life of the document. ANSI Y14.2M-1979 provides much
guidance on the proper selection of line and lettering dimensions, appropriate for many traditional document
production processes. However, with the continual improvement of reproduction equipment, the increasing use of
nonpaper media such as microlm, and the advent of electronically generated or distributed documents, or a
combination of these traditional methods of specifying acceptable documentation quality may be inappropriate or
difcult to apply. For example, in a CAD system, the dimensional units used may be convertible to any arbitrary real
unit if and when a hardcopy document is produced. For documents normally presented on a video screen, or directly
output to microlm, the appropriate units of measurement might bepixels, rather than inches or millimeters.
Nevertheless, certain fundamental dimensional relationships hold true for judging the potential legibility of a
document regardless of the units of measure or documentation medium.
This Appendix sets forth a set of general guidelines, consistent with traditional practice, that can be used to determine
approximate line and lettering size and spacing requirements appropriate to a wide range of document production and
distribution processes.
72
Table B-1Basic Dimensional Relationships

Final size ratio (Final dimensions as a fraction of
original dimensions)
(Rc)
As required
Minimum line thickness on the final document
(Tlf)
As required*
Minimum separation between line edges on the

final document
(Tsf)
As required
(usually 2 Tlf)
Line thickness
(Tl)
Tlf / Rc
Separation between line edges
(Ts)
Tsf / Rc
Spacing between parallel lines (centerline to

centerline)
(Sl)
Tl + Ts
Lettering height (top centerline to bottom

centerline)
(Hc)
Using uppercase characters only

Using upper and lowercase characters
Lettering thickness (top-edge to bottom-edge
lettering height)
2 Sl
3 Sl
(Tc)
Hc + Tl
Connection line spacing (centerline to centerline)

Without lettering between
With lettering between
With lettering and negation bar between
Sl (usually = Hc)
Hc + (2 Sl)
Hc + (3 Sl)
Vertical letter spacing (bottom of one character to

the bottom of the one above)
Without negation bar
With negation bar
Hc + Sl
Hc + (2 Sl)
*The minimum usable line thickness on any printed document is usually 0.008 in. If other constraints
apply, the corresponding minimum line thickness should be substituted.
Figure B-1Minimum Spacing Between Parallel Lines
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IEEE STANDARD FOR
Figure B-2Lettering Size
Figure B-3Spacing for Lines Surrounding Lettering
B.2 Basic Dimensional Relations

For a given set of drawing production and reproduction processes, the thickness of lines and the space between them
must be large enough to prevent line breakage and ll-in on the nal copy. Because lettering is also composed of lines
and spaces, the minimum lettering size is dictated by these same two requirements. It should be noted that because
lowercase letters are smaller than uppercase letters, but require the same number of lines to resolve, the minimum size
of an uppercase letter is larger on a diagram that includes lowercase letters than on a diagram that includes only
uppercase letters.
The relationships as shown in Table B-1 may be used to derive the recommended minimum dimensions on an original
document that will be subject to reproduction or proportional reduction. Figures B-1 through B-3 show how these
relationships were derived.
74
Values greater than the minimum are usually chosen to produce convenient values on the original document for line
thickness, line spacing, and lettering size. If the drawing technique uses templates or other means that produce letters
with a specied outer dimension, then Tc is chosen to match the available sizes. If the drawing technique requires the
specication of the lettering height when an innitely thin line is used, such as in many CAD systems, then Hc is
chosen to be a convenient value.
Table B-2Minimum Dimensions
(Inches)
Using Uppercase Characters Only
Maximum reduction ratio (1/Rc)
1.000
1.250
2.000
2.500
Line thickness (Tl)
0.008
0.010
0.016
0.020
Lettering height (Hc)

Lettering thickness (Tc)
0.048
0.056
0.060
0.070
0.096
0.112
0.120
0.140
Minimum line spacing (C/L to C/L) (Sl)
0.024
0.030
0.048
0.060
0.024
0.096
0.120
0.030
0.120
0.150
0.048
0.192
0.240
0.060
0.240
0.300
0.072
0.096
0.090
0.120
0.144
0.192
0.180
0.240
Connection line spacing (C/L to C/L)

No lettering between
With lettering and negation bar
between
Vertical lettering spacing
With negation bar
Using Uppercase and Lowercase Characters and Special Symbols

Maximum reduction ratio(1/Rc)
1.000
1.250
2.000
2.500
Line thickness(Tl)
0.008
0.010
0.016
0.020

Lettering thickness(Tc)
0.072
0.080
0.090
0.100
0.144
0.160
0.180
0.200
Minimum Line spacing (C/L to C/L) (Sl)
0.024
0.030
0.048
0.060
0.024
0.120
0.144
0.030
0.150
0.180
0.048
0.240
0.288
0.060
0.300
0.360
0.096
0.120
0.120
0.150
0.192
0.240
0.240
0.300

between
With negation bar
EXAMPLES: The dimensions in Tables B-2, B-3, and B-4, which were derived using the formulae in Table B-1, show
the dimensions to be used on original documents subject to reduction by the given ratios to produce printed documents.
Other sets of dimensions may be derived from the formulae or by multiplying the rst column by the ultimate
reduction ratio desired. The dimensions are given in inches.
75
IEEE STANDARD FOR
Table B-3Dimensions with Convenient Units for Lettering Heights (Hc)*

1.000
1.250
2.000
2.500
Line thickness (Tl)
0.008
0.010
0.016
0.020

0.050
0.058
0.063
0.073
0.100
0.116
0.125
0.145
0.050
0.100
0.125
0.063
0.125
0.156
0.100
0.200
0.250
0.125
0.250
0.313
0.075
0.100
0.094
0.125
0.150
0.200
0.188
0.250

between
With negation bar

1.000
1.250
2.000
2.500
Line thickness (Tl)
0.008
0.010
0.016
0.020

0.075
0.083
0.094
0.104
0.150
0.166
0.188
0.208
0.075
0.150
0.150
0.094
0.188
0.188
0.150
0.300
0.300
0.188
0.375
0.375
0.100
0.150
0.125
0.188
0.200
0.300
0.250
0.375

between
With negation bar
*These requirements were derived, using the formulae in Table B-1 to produce
convenient dimensions for line spacing and center-line lettering height (hc).
76
Table B-4Dimensions with Convenient Units for Lettering Thickness (Tc)*

1.000
1.250
2.000
2.500
Line thickness (Tl)

0.008
0.055
0.010
0.068
0.016
0.109
0.020
0.136
0.063
0.078
0.125
0.156
0.063
0.125
0.125
0.078
0.156
0.156
0.125
0.250
0.250
0.156
0.313
0.313
0.125
0.156
0.250
0.313

with/without negation bar

1.000
1.250
2.000
2.500
Line thickness (Tl)
0.008
0.009
0.015
0.019

0.068
0.075
0.084
0.094
0.135
0.150
0.169
0.188
0.075
0.150
0.150
0.094
0.188
0.188
0.150
0.300
0.300
0.188
0.375
0.375
0.150
0.188
0.300
0.375

between
with/without negation bar
*These requirements were derived, using the formulae in Table B-1 to produce convenient
dimensions for line spacing and lettering thickness (Tc).
B.3 Planning Documents for Multiple Use

Diagrams are often needed for use in the engineering drawing set and in associated technical manuals or handbooks.
For this dual role, it is advantageous to prepare a single diagram that meets the requirements of both disciplines. This
eliminates the need to redraw engineering-prepared diagrams to meet technical manual requirements. Engineeringprepared diagrams may then be reduced or scaled to the size required for the manual.
When this is done, certain parts of the original diagram, such as drawing border and title block, may be excluded or
replaced on the nal document. The area of the original diagram that is to be reproduced and the area it occupies on the
nal document are called the image areas of the respective documents. The potentially usable image areas of the two
documents may be not only of different sizes, but of different shapes or aspect ratios. It is usually necessary to limit the
portion of the usable drawing area actually used on either the original, the nal, or both, depending on the principal
purpose(s) of the diagram.
77
IEEE STANDARD FOR
Table B-5Determining Image Areas and Reduction Ratios

Usable dimensions of the final document
Width (larger dimension)
Height (smaller dimension)
(Fw)
(Fh)
(according to format)
(Ow)
(Oh)
Width ratio
Height ratio
(Rw)
(Rh)
Fw / Ow
Fh / Oh
Final size ratio (final dimension as a fraction of

the corresponding original dimension)
(Rc)
Usable dimensions of the original document

Width (larger dimension)
Height (smaller dimension)
To use the entire final area

To use the entire original area
To make optimum use of both areas
Given a final and original character
thickness
Larger of Rw or Rh
Smaller of Rw or Rh
SQRT[(Fw Fh) / (Ow Oh]
Tcf / Tc
Image area to use on the original document

Width
Height
(Iow)
(Ioh)
Smaller of (Fw / Rc) or Ow

Smaller of (Fh / Rc) or Oh
(Ifw)
(Ifh)
Iow Rc
Ioh Rc
(Tlf)
(Tl)
As required
Tlf / Rc
Image area resulting on the final document

Width
Height
Minimum line thickness
On the final document
On the original document
* This table, which includes some of the most common choices made, may be applied to
determine the appropriate dimensions on an original document intended for dual use.
Other minimum dimensions are derived using the basic relationships described in B2.
B.3.1 Determining Image Areas and Reduction Ratios

Table B-5 which includes some of the most common choices made, may be applied to determine the appropriate
dimensions on an original document intended for dual use.
Other minimum dimensions are derived using the basic relationships described in B2.
78
Figure B-4Image Area On an Original Document
79
IEEE STANDARD FOR
Table B-6Multiple-Use Examples Showing Original Lettering Thickness (Tc) (Inches)

Original
Final
Usable
(Oh)
Area
(Ow)
Image
(Ioh)
Area
(Iow)
Line
Thickness
(Tl)
Line
Space
(Sl)
Letter
Thickness
(Tc)
Final Size
Ratio
(Rc )
Usable
(Fh)
Area
(Ffw)
Image
(Ift)
Area
(Ifw)
Line
Thickness
(Tlf)
Line
Space
(Slf)
Letter
Thickness
(Tcf)
9.25
15.95
9.25
15.95
0.018
0.054
0.125
0.560
7.00
9.00
5.18
8.93
0.010
0.030
0.070
14.50
20.00
14.50
20.00
0.022
0.067
0.156
0.448
7.00
9.00
6.50
8.96
0.010
0.030
0.070
14.50
20.00
0.018
0.054
0.125
0.560
9.00
15.25
8.12
11.20
0.010
0.030
0.070
20.00
28.13
0.031
0.094
0.219
0.320
7.00
9.00
6.40
9.00
0.010
0.030
0.070
20.00
31.00
0.022
0.067
0.156
0.448
9.00
15.25
8.96
13.89
0.010
0.030
0.070
16.07
31.00
0.018
0.054
0.125
0.560
9.00
36.00
9.00
17.36
0.010
0.030
0.070
26.00
36.16
0.040
0.121
0.281
0.249
7.00
9.00
6.47
9.00
0.010
0.030
0.070
24.11
38.00
0.027
0.081
0.188
0.373
9.00
15.25
9.00
14.19
0.010
0.030
0.070
16.07
38.00
0.018
0.054
0.125
0.560
9.00
36.00
9.00
21.28
0.010
0.030
0.070
31.00
40.18
0.045
0.134
0.313
0.224
7.00
9.00
6.94
9.00
0.010
0.030
0.070
28.13
42.00
0.031
0.094
0.219
0.320
9.00
15.25
9.00
13.44
0.010
0.030
0.070
16.07
42.00
0.018
0.054
0.125
0.560
9.00
36.00
9.00
23.52
0.010
0.030
0.070
20.00
31.00
26.00
38.00
31.00
42.00
Table B-7Multiple-Use Examples Showing Original Lettering Thickness (Tc)

(Inches)
Original
Final
Usable
(Oh)
Area
(Ow)
Image
(Ioh)
Area
(Iow)
Line
Thickness
(Tl)
Line
Space
(Sl)
Letter
Thickness
(Tc)
Final
Size Ratio
(Rc )
Usable
(Fh)
Area
(Ffw)
Image
(Ift)
Area
(Ifw)
Line
Thickness
(Tlf)
Line
Space
(Slf)
Letter
Thickness
(Tcf)
9.25
15.95
9.25
14.91
0.016
0.050
0.100
0.603
7.00
9.00
5.58
9.00
0.010
0.030
0.070
14.50
20.00
14.50
20.00
0.025
0.075
0.150
0.400
7.00
9.00
5.80
8.00
0.010
0.030
0.070
14.50
20.00
0.016
0.050
0.100
0.603
9.00
15.25
8.75
12.07
0.010
0.030
0.070
20.00
29.96
0.033
0.100
0.200
0.300
7.00
9.00
6.01
9.00
0.010
0.030
0.070
20.00
31.00
0.025
0.075
0.150
0.400
9.00
15.25
8.00
12.40
0.010
0.030
0.070
14.91
31.00
0.016
0.050
0.100
0.603
9.00
36.00
9.00
18.71
0.010
0.030
0.070
26.00
37.41
0.041
0.125
0.250
0.241
7.00
9.00
6.25
9.00
0.010
0.030
0.070
22.50
38.00
0.025
0.075
0.150
0.400
9.00
15.25
9.00
15.20
0.010
0.030
0.070
14.91
38.00
0.016
0.050
0.100
0.603
9.00
36.00
9.00
22.93
0.010
0.030
0.070
29.10
37.41
0.041
0.125
0.250
0.241
7.00
9.00
7.00
9.00
0.010
0.030
0.070
29.96
42.00
0.033
0.100
0.200
0.300
9.00
15.25
9.00
12.62
0.010
0.030
0.070
14.91
42.00
0.016
0.050
0.100
0.603
9.00
36.00
9.00
25.34
0.010
0.030
0.070
D 20.00
31.00
26.00
38.00
31.00
42.00
80
B.3.2 Examples
The data in Tables B-6 and B-7 demonstrate the application of the methods of this Appendix to derive the sizes and
spacings necessary on various sizes of original diagrams so as to produce technical document pages of various sizes.
In these examples the nal lettering is to be 0.070 inches in total height. In Tables B-6 and B-7 only uppercase lettering
is used, and the image areas have been chosen to permit the best use of the overall usable areas both on the original
diagram and on the nal document. Units have been chosen differently in the two examples so as to make them more
convenient for the method used in the production of the original. In Table B-6, the units were chosen to produce
lettering thickness Tc in conventional inch-fractions, as would be suitable for many hand-drawn diagrams. In Table B7, the units were chosen to produce convenient decimal values for lettering height Hc, as they might be if preparing a
diagram on a CAD system.
81
IEEE STANDARD FOR
Annex C Single Orientation of Lettering

(Informative)
C.1
IEC Publication 113, Part 7. (1981) permits only one orientation of text. Change in this requirement is under
consideration.
C.2
Because the symbology of ANSI/IEEE Std 91-1984 is based on the concept that inputs are predominantly on the left
and outputs are on the right, many problems can occur when trying to use horizontal text with vertical signal ow. The
following requirements address some of these problems (see also Fig B-5).
1)
2)
82
The symbol for an output with special amplication shall not be used. The general qualifying symbol for an
element with special amplication may be used. For example:
The qualifying symbol must not appear adjacent to the output line, where it could be confused with the 3state output symbol.
In arrays with successive groups of elements, it will usually be necessary to show the details within the
outlines at both ends of the groups. For example:
3)
General qualifying symbols shall not appear adjacent to an input or output line. This will usually force the
general qualifying symbol out of the normally preferred top center location. For example:
C.3
Example of Application Information Placement.
83
Figure C-1Logic Symbol Orientation Examples for Diagrams that Permit

Only One Orientation of Text
(See NOTE to Fig 6)
84

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