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UVM based Automated SoC


Interconnect Verification
Methodology
Ganesh Venkatakrishnan
Prajakta Rohom
C O N F I D E N T I A L

7th November 2014

Traditional SoC Interconnect Verification Methodology

Standalone development of Test-Bench and


Test-Cases for Interconnect verification

Test-Cases

Limitations to this approach :

Test-Bench

Traditional approach:

Separately maintain a Test-Bench environment for


Interconnect
Does not take into consideration the final
integrated SoC RTL
Additional efforts are required at the SoC level to
ensure the Connectivity and Integration of the IPs
with the Interconnect

M1
VIP

M2
VIP

M3
VIP

M4
VIP

Interconnect

Toggle coverage closure for Interconnect signals


cannot be achieved at SoC level by only functional
Test-Cases at IP level

S1
VIP

S2
VIP

Traditional SoC Interconnect Test-Bench

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Proposed SoC Interconnect Methodology

Basically enables the verification of the Interconnect


in the Integrated SoC
The Verification Setup generation/automation is
divided into 2 parts:

Instantiating the Bus VIPs (Master/Slave) inside


the top level file of the IP RTL at the Interface
connecting to the Interconnect.
UVM Environment Layer Generation for
controlling the Transactions to/from the Bus VIPs.

Architecture/IP capabilities

Interconnect RTL
generation tool

Custom TEXT
input from Spec to
generate traffic

SoC Integration
Interconnect/IPs
UVM layer for
VIPs / Test-Cases

SoC File-List
DUT config

File-list
management
Modified File-List
New SoC RTL
with VIPs
connected inside
IP top

Configurable
functional SoC TB

Simulator

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Proposed SoC Interconnect Methodology Implementation

The BUS VIP Interfaces are instantiated through an automated process inside the IP RTL top files.

The setup must have the following information to enable the automation of replacement of IP by BUS VIP :

IP block name with block flavor


BUS type (AXI/AHB/APB)
Interface type ( Master or Slave)
Name of clock and reset signals of the BUS Interface
BUS signal naming format used in IP top

For the UVM based Test-Bench generation of Interconnect, the same block of code with different configurations
repeat in the environment for large number of agents.

Automation of the UVM layer using a Perl script to avoid manual errors and save time
In addition, the automation also includes generation of coverage, assertions and necessary Test-Cases too

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UVM layer auto generation

The Perl script takes inputs from a text file which reflects the attributes of the Interconnect Master/Slaves and
generates following UVM files:

UVM Interconnect Environment


Basic sequence library
Basic M-S access and non-access test-cases
System Verilog Functional Coverage
System Verilog Assertions

IP

BUS

SA

EA

M/
S

D
W

W R
I I

ID

REMAPSA

REMAPEA

CPU

AXI3

0000_0000

FFFF_FFFF

128

CPU

0000_0000

FFFF_FFFF

128

CPU

0000_0000

FFFF_FFFF

128

DMA

AXI3

0000_0000

FFFF_FFFF

64

0000_0000

FFFF_FFFF

0000_0000

FFFF_FFFF

BOOTAM

0000_0000

FFFF_FFFF

UART0

0000_0000

FFFF_FFFF

BOOTBM

DMA

0000_0000

FFFF_FFFF

64

0000_0000

FFFF_FFFF

DRAM0

AXI3

0000_4000

3FFF_FFFF

64

15

0000_0000

3FFF_FFFF

UART0

APB3

FFF1_D000

FFF1_DFFF

32

FFF1_D000

FFF1_DFFF

UART1

APB3

FFF1_E000

FFF1_EFFF

32

FFF1_E000

FFF1_EFFF

BOOTAM

AXI3

0000_0000

0000_3FFF

64

0000_0000

0000_0000

BOOTBM

AXI3

FFFF_0000

FFFF_3FFF

64

0000_0000

0000_0000

RSVD1

FFF1_0000

FFF1_3FFF

FFF1_0000

FFF1_3FFF

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ERRSLV

DMC Performance measurement using the proposed SoC Interconnect Verification


Methodology

The proposed Methodology allows user to configure the DUT to pick the actual RTL File for any IP or the VIP
instantiated top File of the IP on the go.
This can be extended to do a DMC performance analysis.

This can be achieved by choosing a DUT configuration that picks DMC as rtl_top flavor while all the IP Masters can
be chosen to be in their vip_top flavor.
Performance monitors can be instantiated at the interface level of the IP Masters and DMC.
The sequences generated from each master can be bombarded simultaneously to stress test the performance of the
DMC.

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Issues found in Interconnect/SoC

Some of the issues that have been identified and resolved are:

Address Maps specified in MAS not matching the RTL implementation


A few Slave/Master ports not implemented in the Interconnect which otherwise are caught only when the IP is verified
for functionality.
ID width Mismatches
Width Mismatches of certain AMBA protocol signals between the Master-Interconnect-Slave
Clock/Reset signal not driven
Outstanding issuing and accepting capability of Interconnect not defined correctly
Latency issues with a few slaves (DMC) that adversely affect performance.

Note : The proposed Methodology was proven on a SoC with multi-level Interconnect architecture. The SoC had
close to 50 AMBA Masters and close to 80 AMBA Slaves

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Conclusion

The proposed Methodology ensured that the Specification and the final RTL of the Interconnect are coherent.
The Interconnect verification environment using a single Perl script

Saves a lot of time in the verification cycle


Only manual effort needed is for input text file creation as per the project specifications

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THANK YOU
ganesh.venkatakrishnan@open-silicon.com
prajakta.rohom@open-silicon.com

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