CAD for VLSI Design - II

Lecture 6
V. Kamakoti and Shankar Balachandran

Overview of this Lecture

CMOS Transistor Theory
Delay Issues (Contd)
Types and effects of Capacitances on delay

Parasitic Capacitance
Switching speeds of MOS systems strongly depend on
the parasitic capacitances associated with MOSFETs
and interconnections
Total Cload on the output of a CMOS gate is the sum of:
Gate capacitance (Cg)
Junction capacitance due to the source and drain
regions and their surroundings (Csb and Cdb)
Interconnect (or routing) capacitance (Cw)
Gate oxide capacitance per unit area,

C ox

0 ox
=
tox

MOSFET Capacitances
xd

xd

xd

Gate Capacitance
Gate capacitance, Cg = Cox WL
Total gate capacitance Cg can be
decomposed in two elements:
1. Overlap capacitance: due to the topological
structure of the MOSFET.
2. Gate-to-Channel capacitance: due to the
interaction between gate voltage and channel
charge.

Gate Overlap Capacitance

In reality , actual channel length, Leff < drawn length, L
(mask length), due to the extension of the source and
drain regions somewhat below the oxide by an amount
xd, called the lateral diffusion, i.e., Leff = L 2.xd
xd gives rise to overlap capacitance which is linear and
has a fixed value.

C gso = C gdo = C ox xdW = C oW

Co is overlap capacitance per unit transistor width

(fF/m)

Gate-to-Channel Capacitance
It has thee components: Cgs, Cgd and Cgb

Average Gate Capacitance

Region

Cgb

Cgs

Cgd

Cg

Cutoff

CoxWL

CoxWLeff+2CoW

CoxWLeff/2

CoxWLeff/2

CoxWLeff+2CoW

(2/3)CoxWLe

(2/3)CoxWLeff+2C
oW

eff

Linear
Saturation

ff

Area and Side-wall Capacitance

Area Capacitance (Carea) due to the bottom-plate
junction formed by the source (drain) region with doping
ND and substrate with doping NA (bottom area 5).
C area = C j WLs

where, C j is junction capacitanceper unitarea

Side-wall (perimeter) Capacitance (Csw) formed by

junctions 2, 3, and 4. These are surrounded by the p+
channel-stop implant with doping level NA+ which is
usually larger than that of the substrate larger
capacitance per unit area.
C sw = C jsw (W + 2 L s )

where , C j sw is junction side-wall capacitanceper unit

length

(C

jsw

= C jsw x j )

MOSFET Capacitance Model

C g = C gb + C GS + C GD
C GS = C gs + C gso
C GD = C gd + C gdo

Wire (Routing) Capacitance

C w C pp + C fringe
o ox wl
2 ox

+
h
log h
t

( )

Parallel-plate and Fringing

Capacitance
Total Cap.

t/h=1
t/h=0.5
Cpp

w
t
h

w/t

Modern Interconnect

Inter-layer capacitance increases with decreasing feature

sizes.
Multi-layer capacitive interactions result in unwanted
coupling among neighboring signals cross talk

Impact of Inter-layer
Capacitance

Capacitances for a 0.25m Process

Capacitance
Poly - substrate
Metal1 - substrate
Metal2 - substrate
n+ diff - substrate
p+ diff - substrate
n+ overlap cap.
p+ overlap cap.
Cox
Metal1 - poly
Metal2 metal1

Area Cap
(fF/m2)
0.088
0.041
0.015
1.660
1.832
--5.951
0.017
0.038

Perim. Cap
(fF/m)
0.054
0.047
0.027
0.399
0.323
0.562
0.630
0.041
0.054

0.25m Interconnect Hierarchy

Global

Intermodule

Intercell
Intracell

Optimize interconnect structure at

each layer.
for local wires, density and low
C are important use dense
and thin wiring grid
for global wires in order to
reduce delays, use fat, widely
spaced wires.
Improve wire delays by using
better material (Cu) and low-K
dielectrics for insulators.

Electrical Wire Models

Ideal Wire - it is simply a line with no attached
parameters or parasitics it has no impact on electrical
behavior.
Lumped Model simplified model simple and fast
computation, e.g., lumped C, lumped RC or lumped
RLC

Clumped = lwire.cwire

Distributed Model - Parasitics of a wire are distributed

along its length and are not lumped into a single
position, distributed C, distributed RC, or distributed
RLC

Elmore Delay Formula

For an n stage RC chain, the first order time constant is

i
given by,n
n = Ci R j
i =1

j =1

= C1R1 + C 2 ( R1 + R2 ) + ... + Cn ( R1 + R2 + ... + Rn )

n (n + 1)
for all i and j , (1 i, j n) then,
If Ri = Rj and Ci =nC=j RC
2

Distributed RC Model for a Wire

Using Elmore delay formula we can determine the dominant time constant
of the wire, i.e., it is a first-order approximation.

Questions and Answers

Thank You