New SoC Integration Strategies for

Multi-million Gate,
Multi-power/Voltage Domain Designs
Sarveswara Tammali, RTL Lead, TI
sarvesh@ti.com

Mayank Jindal, RTL Designer, TI

m-jindal@ti.com

Dave Matt, SMTS, TI

d-matt@ti.com

Gokulkrishnan Manoharan, RTL Designer, TI

g-manoharan@ti.com

Bernard Murphy, CTO, Atrenta

bmurphy@atrenta.com

Ayon Dey, RTL Designer, TI

a-dey@ti.com

Agenda

SoC design challenges

Trends of SoC integration past and current

Architecture based integration

Power management insertion

Design reuse in new era

Challenges and key benefits

Metrics

Future work

Conclusions
2

Productivity Challenge
8

(Source ITRS 2005)

Design reuse
2X more
productive

0
2005

2007

2009

Required productivity for new designs

2011

Productivity
must increase
4X in 6 years

Required productivity for reused designs

SoC Design Challenges

Integrate SoC (IP>100) with minimum design resources
Productivity challenge

Accelerate SoC development cycle
Time to market

Third party IPs are used to meet product goals
Time to market

Complexity due to higher integration
- Increased verification cycles due to increased bugs

SoC Integration - Past

Specification

Challenges
Hardware
IP Library

IP Selection

Design bugs due to IP

incompatibility
Active low interrupt source
connected to active high
interrupt destination

AHB/APB/OCP bus signals

are connected from
master <-> slave port by port

XLS2HDL

Local scripts/flows specific to

SoC teams resulting in ad hoc
SoC integration flows

HDL file
5

SoC Integration - Today

SoC designer
etc
.

TI
Autogen

IP library
(IP-XACT, etc.)

SoC top level

netlist RTL

SoC testcases,
C library

Chip w/ IP
instance Info

IP
info

1Team-Genesis DB

Review
views

IP data (IP-XACT)

Connectivity information

What are the benefits?

xml
Translators

Underlying database

Provides APIs to access

Provides GUI

1Team-Genesis
GUI

TI architecture
tables

TI Autogen

TI wrappers + 1Team-Genesis

1Team-Genesis provides

Generators

Files
(RTL, etc)

IP Information

Automatically loads arch tables

Performs automated checks

IP-XACT Adoption @ TI

IP-XACT refers to a set of XML schemas defined by the SPIRIT
Consortium (www.spiritconsortium.org)

IPXACT Describes

IP boundary ( ports, direction, width, default value etc)

Registers

User can extend with attributes and parameters to describe IP

configuration

E.g. UART_RX_INT is an active-low, level interrupt

Within TI, IP-XACT is used to help automate RTL hook-up, generation

of register info (docs, C APIs, test cases)

IP teams provide IP-XACT files to SoC teams

1Team-Genesis provides several ways of creating IP-XACT files

Import RTL entity / excel

Other formats of IP-XACT
7

Architecture Based Integration (1/2)

Definition:
Hook-up of IPs within SoC, based on knowledge of port
characteristics embedded in IP-XACT

All associated ports are grouped into a busdef based on

architectural relation e.g, OCP, DFT, power management

Enables correct by construction hook-up

1Team-Genesis tool will error-out if hook-up is forced
against architectural rules
Active low interrupt source connection to active high interrupt
controller

Architecture Based Integration (2/2)

Power Management Insertion (1/2)

In an SOC with
tens of thousands of signals
with thousands of cells,
this effort has to be
automated

10

Power Management Insertion (2/2)

The user describes the SoCs voltage &
power domains, and assigns the IP
instances to them

TI-developed utilities use 1Team-Genesis
APIs to determine all the connections
between IPs that cross power and/or
voltage domain boundaries. These
connections will need isolation cells and
level shifters

Power management blocks holding these
isolation cells & level shifters will be
created and added to the design
Instead of specifying thousands of low-level
details, the designer fills out a few high-level
tables describing the domains and assigns
the IP blocks to them

11

Design Re-use

Design re-use is critical factor in this SoC era
Faster time-to-market
Adding features to existing designs (Derivatives)

The 1Team-Genesis flow provides a smooth platform to re-use

connections
Connection data between IPs is captured in Tcl format which is easy to
process

IP2

IP1
IP3
Design-1

mon
m
o
c
the ns
g
n
ctio
usi
Re- conne

Re-u
sing
con the com
nec
tion mon
s

IP1

IP2
Design-2

IP1
IP3
Design3
12

Challenges of New Integration Methodology

IP modeling and IP packaging

Which set of signals need to be grouped as a busdef?

Busdefs are not backward compatible

Inconsistency between IPXACT and entity due to process immaturity

Designers view, paradigm shift

Understanding the existing IP models and their busdefs

Understanding the grouping to be followed in case of creating new
busdefs

Modeling custom and 3rd party IPs with the existing busdefs and newly
created busdefs

Working with Tcl as against HDL/xls (Easier though!)

13

Challenges of New Integration Methodology

(Continued)

Handling multiple hierarchies in a single design
Instantiation of a design created in the tool in a new
design through IP-Model

14

Key Benefits of the Flow

Design re-use
Connection database can be reused for derivative SoCs

RTL health checks

Provides connection status of each port / interface
Provides multi-drivers, floating inputs
Provides data in Excels csv format

Usage of 1Team-Genesis database for verification

RTL health check database used to create connectivity test cases

Eases phase wise integration strategy

Eases the job of the integration engineer by auto-insertion of
default values to unconnected inputs

15

Integration Metrics (1/2)

SoCs
Application processor
Image co-processor

Profile of SoC

Cortex ARM processor

Hardware accelerators
Sophisticated power, clock management module
Low cost, low DPPM DFT sub-system
Emulation sub-system
Security controller
Peripherals (I2C, SPI, UART, GPIO etc.)
DDR controller
MIPI PHYs

16

Integration Metrics (2/2)

Benefits of using IP-XACT and busdef in SoC integration
Sl. No

IP

Ports

# of busdefs

IP1

1200

145

IP2

890

115

IP3

645

43

Savings in man months (MM)

Sl.No

SoC

Total # of
connections
(K)

Total # of
reused
connections

# of
instances

MM
effort

Savings
(MM)

SoC1

35

12

112

24 MM

12 MM

SoC2

50

34

180

14 MM

7 MM

SoC3

58

34

192

26 MM

15 MM
17

Future Work

Single flow for SoC integration and RTL quality
checks

Auto ECO ports addition for subchip hierarchies

Handling hierarchies better

18

Conclusions

Complexity, gap in productivity, cycle times are key
challenges of SoC design

IP-XACT and architecture based integration helped TI to
address above challenges

1Team-Genesis together with TI wrappers have enabled TI to
pioneer in this new era of integration

Key challenges include IP modeling and busdef alignment

New integration strategy started showing R&D efficiency but
more positive impact will be seen in next cycle of designs

Number of integration bugs reduced significantly over past
designs

Opportunity seen to reduce design verification effort
19

Acknowledgements

Acknowledges to team who supported flow
Satyam Pentakota (TII)
Subash C (TII)
Nitesh (TII)

Other RTL lead who is involved in discussion

Vincent LeRoy (TIF)

20