FPGA Tutorial IECON06 EM MC PDF

Overview
FPGAs used in
Industrial Control Systems
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Introduction, Presentation of the Current Trends (30 min, MC, EM)

Description of FPGAs (30 min, EM)
Holistic Modelling/Design Methodology (30 min, MC)
Main Design Rules (30 min, EM)
Refinement of Control Algorithms by Simulation

Algorithm Architecture Adequation
Reusability, VHDL Coding
Hardware-In-the-Loop (HIL) Validation
Coffee break --------------------------------------------------------------------------------------
Prof. Eric Monmasson,
Cergy-Pontoise University, Cergy-Pontoise, France

Email: eric.monmasson@u-cergy.fr
1st case studies series: FPGA-based Current Controllers for AC Drives (40 min, EM)
Dr. Marcian Cirstea,
Anglia Ruskin University, Cambridge, UK

Email: marcian@ieee.org
Quasi-Analog Hysteresis Controller

Delta Modulator
PI SVM Controller
Predictive Controller
2nd case studies series: FPGA-based Intelligent Controllers for AC Drives and AC Generators
(40 min, MC)
Induction Motor Control Using Neural Networks
Stand Alone Generator Set Using Fuzzy-Logic and PWM
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Conclusions and Perspectives (10 min, EM, MC)

Hands on practical demonstration on two simple examples (30 min, EM, MC)
Chair: Dr. Marcian Cirstea, Head of Department of Design &

Technology, Anglia Ruskin University, Cambridge, UK.
Email: marcian@ieee.org
ELECTRONIC SYSTEMS ON CHIP

Technical Committee of IEEE Industrial
Electronics Society
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http://vega.unitbv.ro/~ieee
Mission Statement:
This Committee aims to promote professional activities in the area
of low power electronics used in the modern industry, with an
important focus on the design, development, simulation,
verification and testing of digital and analogue circuits integrated
as Systems on Programmable Chips, targeting Field
Programmable Gate Arrays / Application Specific Integrated
Circuits for implementation, and including the use of Hardware
Description Languages or high level programming languages
hardware compilers, as well as embedded electronic systems and
associated software.
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Special conference sessions organisations subcommittee

Coordinator and Committee Vice-Chair: Dr. Manus Henry, Deputy
Director, Invensys University Technology Centre for Advanced
Instrumentation at the Department of Engineering Science, the University of
Oxford, UK.
Dr.Vito Nardi, University of Cassino, Italy.
Special Issues / Sections of Journals subcommittee
Coordinator: Prof. Eric Monmasson, Head of the Institut Universitaire
Professionnalis de Gnie Electrique et dInformatique Industrielle (IUP
GEII), University of Cergy-Pontoise (UCP), France.
Prof. Josep M. Guerrero, Universitat Politcnica de Catalunya (UPC),
Barcelona, Spain.
Dr. Jeen G. Khor, Senior Design Engineer, INTEL, Penang, Malaysia.
Web page subcommittee
Coordinator: Dr. Andrei Dinu, Goodrich Engine Control Systems,
Electromagnetic Systems Technical Centre, Birmingham, UK.
Dr. Otilia Boaghe, Phillips Semiconductors, Zurich, Switzerland.
Conferences / transactions papers review subcommittee
Coordinator: Prof. Dan Nicula, Transilvania University Brasov,

Romania.
Prof. Bogdan Dan Willamowski, Past President of the Industrial

Electronics Society, Auburn University, AL, USA.
Dr. Jeroen Van Den Keybus, Catholic University of Leuven,

Belgium.
Activity Plan 2007
Dr. Yasuhiro Ota, Partner Robot Development Division, Toyota

Motor Corporation, Aichi, Japan.
Prof. Chin-Long Wey, Dean of College of Electrical Engineering
and Computer Science, National Central University, Chung-Li,
Taiwan.
Dr.Robert Seliga, Electronics Design Engineer, Newage AVK
SEG, Stamford, UK.
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Website development to support & promote committees work and to

provide a point of reference on topics of interest.
Guest-Editorship of a special issue of the Transactions on Industrial

Electronics: FPGAs used in Industrial Control Systems. Dr. Eric
Monmasson and Dr. Marcian Cirstea are joint Guest Editors.
Organisation of a best paper prize of $500 for this Special Issue
Organisation of special sessions at the forthcoming IEEE IES

Conference: ISIE07.
Organising ISIE08 in Cambridge
Refereeing of IEEE Transactions and Conference papers.
Contributing to the organisation of other IES conferences by chairing

Technical Tracks, refereeing papers, etc.
Presenting tutorials
Printing materials to advertise the committee, as well as its technical

activities, as posters / leaflets.
Introduction
Introduction
Traditionally, mathematical models were used to functionally evaluate

engineering systems. The development of each system component used then
to be separately addressed, often involving the use of other CAD tools and/or
different software platforms.
Traditionally, mathematical models were used to functionally evaluate

engineering systems. The development of each system component used then
to be separately addressed, often involving the use of other CAD tools and/or
different software platforms.
Traditional methods are not able to cope with increased complexity and
demands of higher levels of systems integration / faster time to market.
Recent advances in CAD methodologies/languages has brought the systems
functional description and hardware implementation closer.
Traditional methods are not able to cope with increased complexity and
demands of higher levels of systems integration / faster time to market.
Recent advances in CAD methodologies/languages has brought the systems
functional description and hardware implementation closer.
Modern Electronic Design Automation (EDA) tools are used to model,

simulate and verify a complex engineering system fast, with high confidence
in right first time correct operation, without producing a prototype.
Modern Electronic Design Automation (EDA) tools are used to model,

simulate and verify a complex engineering system fast, with high confidence
in right first time correct operation, without producing a prototype.
High performance electronic controllers can also be implemented.
High performance electronic controllers can also be implemented.
The presentation reveals recent work that was carried out in the area of
holistic modelling of engineering systems using HDLs.
The presentation reveals recent work that was carried out in the area of
holistic modelling of engineering systems using HDLs.
Comparative Economics
Integrated Circuits
Cost
(relative)
Off-the-Shelf Logic - Function pre-set.
PROM, PAL, FPLA - Programmed by fusible links / charge storage.
FPGAs - User programmable Field Programmable Gate-Arrays.
Gate Array Device - Function set at manufacture in the final stage of

production (metallization).
Cell Based Device - Function set at manufacture using CAD to speed up

design and a library of optimised standard functions.
Full Custom Device - Function set at manufacture - every circuit part is

optimally designed. Long development time even with CAD.
full-custom
cell
-based
system
gate-array
Volume
10,000
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ASICs allow tailoring the design during development stages of an IC.

Advantages:
.
.
.
.
where D=total development cost, N=no. of chips manufactured,

chip=unit chip costs in production, F=packaging, testing per chip
FPGAs have reached high density rate

( > 10 millions gates)
z Performing Electronic Design Automation (EDA)
Tools
z These components allow the programming of
specific hardware architecture
z This leads to a flexible and an efficient solution
(software development of dedicated hardware
architecture that includes parallelism)
z System-on-a-Chip (SoC) scale
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High Speed and Accuracy in Information Processing

Compact Structure
High Reliability of Circuit Operation
Two major ASIC technologies: CMOS and BICMOS - millions gates.
RISC and DSP cores are now offered by chip suppliers. They permit the
design of single chip customised advanced integrated processors.
Field-Programmable Gate Arrays (FPGAs) are a special class of ASIC's

which differ from mask-programmed gate arrays in that the programming is
done by end-users with no IC masking steps.
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Introduction
Reduced Size and Cost
.100,000
True cost formula shows that the final unit cost is:
Application Specific Integrated Circuits

Application Specific Integrated Circuits (ASICs) = any IC designed and built
specifically for a particular application.
50,000
cost = D / N + chip + F
; More gates / chip ==> reduces cost but requires CAD.
SSI / MSI
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Introduction
Advantages:
Many industrial applications
Telecom,
Video,
Signal Processing,
Medical Systems,
Embedded Systems (Aircraft, Automotive),
Electrical Systems:
z PWM inverters,
z Power factor correction AC/DC converters,
z Multilevel converters,
z Matrix converters,
z Active filters,
z Fault-detection on power grid,
z Electrical machines control (induction machine drives, multi-machines
systems,
z Neural Network control of induction motors,
z Fuzzy Logic control of power generators,
z Speed measurement
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The decrease of the cost

An architecture based only on the specific needs of the algorithm to implement,
Application of highly advanced and specific methodologies improving implementation
time also called "time to market",
Expected development in VLSI design that will allow integrating a full control system
with its analog interface in a single chip, SoC.
The confidentiality
Specific architecture, integrating the know-how of a company, is not easily duplicable.
The embedded systems
Many constraints as in aircraft applications, like limited power consumption, thermal
consideration, reliability and Single Event Upset (SEU) protection.
The improvement of control performance
Execution time can be dramatically reduced by designing dedicated parallel architectures,
allowing FPGA-based controllers to reach the level of performance of their analog
counterparts without their drawbacks (parameter drifts, lack of flexibility).
FPGA-based controller can also be adapted in run-time to the needs of the plant by
dynamically reconfiguring it.
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Introduction
Introduction
(d)
Algorithm complexity
Introduction
DSP
(a)
(b)
(c)
(d)
:
:
:
:
Algorithmic Constraints:
high data dependency

high level of parallelism of the algorithm
few functions and / or homogenous functions
lot of functions and / or heterogeneous functions
Boucles
Speed
Boucles
Speed
de
&
de vitesse
vitesse
&
Flux
&
Flux
&
Regulations
Regulators
de
Regulations
Regulators
de flux
flux
isd*
isq
vs*
vsd*
is*
eejj
is
d
vsq*
vs
c1
Vector Control Algorithm:
c2
SVPWM
Current Regulator
Flux Estimator
c3
MLI
PWM
s
is
isd
isq
-j
ee-j
Is
123
123
is1
is2
is3
FPGA
Flux
Reconstruction
Flux
vector
&
estimation
Flux
Reconstruction
Flux
vector
& Speed
Speed
estimation
du
Observation
vecteur
&
du
Observation
vecteur
& flux
flux
Speed
(Sensorless
estimation
operating
&
mode)
Speed
(Sensorless
estimation
operating
& (sensorless)
(sensorless)
mode)
de
de la
la vitesse
vitesse (sans
(sans capteur)
capteur)
(c)
(a)
Algorithm Timing constraints
Transformations
Differences :
Heterogeneous Functions
Various Time Scale
Various Computing Tasks
(b)
Algorithm Architecture Adequation by means of FPGA
A specific architecture for each control algorithm

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Introduction
Introduction
This leads to follow up a design methodology
How to easily implement a control algorithm on

an FPGA-based optimized hardware architecture?
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t e ta m
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teta
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De flu xa g e
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C o n tr l e d e s
C o u ra n ts
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X1
AddSub
c2 Vs2
c2
t et a
a
x l a d d su
a -bb
b
R O M (c o s)
Ce m
C em
I s q re f
M ult
Vs1
c1
I sd q m a x
M u l t3
0
1
I sq re f
N re f
-K -
V s1
N re f
Clo ck
te ta m
rh
c1 Vs 1
W re f
-K -
I s q re f
P I W _ sa t
P ro d u c t
I s d re f
Cem
C em
functional simulation
c2 Vs 2
I s q re f
te ta
Vs 2
teta
-K -
c3 Vs 3
I
c3
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o nd uleu r
C o n t r l e d e s
C o u ra n ts
1 /W m a x
Vs 3
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Cr
6 .0 9 ; 0 .5 9 , 1 5
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Fixed-point quantization
& discrete model
Vs 1
c1
I sd q m a x
c2
-K -
R O M (si n )1
p i /3 0 /W m a x
Data Flow
Graph
Cr
C r0
Is 3
t g (d e c )
Cr
C h a rg e
M SPM
D e fl u xa g e
Cr
Simulink Model
FPGA board
Experimental board
VHDL coding
FPGA target
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Generic FPGA Architecture
Generic FPGA Architecture

Logic Cell / Logic Element :
C onfigurable
Input/O utput
B lock
Output carry
C onfigurable
Logic B lock
Inputs
[3:0]
Interconnection
Pr ogram m able
N etwork
LUT
LUT
Combinatorial
output
D
Bascule
Flip-Flop
D
Flip-Flop output
Carry
Chemin
Path
19
Input
carry
Clock
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Head-to-Head
z
Xilinx Virtex-5
1v 65nm copper
207,360 logic cells
11.6 Mb RAM
192 48-bit MAC Unit
(25x18 multipliers, 550MHz)
Up to four PowerPC 405

cores
MicroBlaze 32-bit soft core
Head-to-Head Low Cost
Altera Stratix II
Spartan 3E
Altera Cyclone II
1.2v 90nm copper

179,400 logic elements
9.4 Mb RAM
96 36x36 multipliers
(384 18x18 multipliers)
1,170 user I/O pins
1.2v 90nm copper

33,192 logic cells
0.65 Mb RAM
376 user I/O pins
8 DCMs
Nios II 32-bit soft processor

core
MicroBlaze 32-bit soft

processor core
1.2v 90nm copper

68,416 logic elements
1.15 Mb RAM
622 user I/O pins
4 PLLs
Nios II 32-bit soft processor

core
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Virtex IV Platforms
Virtex-4 Architecture
RocketIO
Multi-Gigabit
Transceivers
LX
Smart RAM
New block RAM/FIFO
FX
SX
Resource
622 Mbps10.3 Gbps
Advanced CLBs
Xesium Clocking
Technology
200K Logic Cells
500 MHz
Logic
14K
14K200K LCs
12K
12K140K LCs
23K
23K55K LCs
0.9
0.96 Mb
0.6
0.610 Mb
2.3
2.35.7 Mb
412
420
48
32
3296
32
32192
128
128512
240
240960
240
240896
320
320640
RocketIO
N/A
024 Channels
N/A
PowerPC
N/A
Ethernet MAC
N/A
Memory
DCMs
DSP Slices
Tri-Mode
Ethernet MAC
XtremeDSP
Technology Slices
SelectIO
10/100/1000 Mbps
256 18x18 GMACs
PowerPC 405
with APU Interface
1 Gbps SelectIO
ChipSync Source synch,
XCITE Active Termination
450 MHz, 680 DMIPS
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1 or 2 Cores
2 or 4 Cores
N/A
N/A
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Slices and CLBs
Altera Stratix
z
Each Virtex-II CLB

contains four slices
Local routing provides
feedback between slices in
the same CLB, and it
provides routing to
neighboring CLBs
A switch matrix provides
access
to general routing resources
COUT
COUT
BUFT
BUF T
Slice S3
Slice S2
Switch
Matrix
SHIFT
Slice S1
Slice S0
CIN
Local Routing
CIN
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Distributed SelectRAM Resources

z
z
z
Uses a LUT in a slice as memory

Synchronous write
Asynchronous read
Accompanying flip-flops
can be used to create
synchronous read
RAM and ROM are initialized during
configuration
Data can be written to RAM
after configuration
Emulated dual-port RAM
One read/write port
One read-only port
LUT
LUT
Slice
LUT
Simplified Slice Structure

z
RAM16X1S
D
WE
WCLK
O
A0
A1
A2
A3
RAM32X1S
D
WE
WCLK
O
A0
A1
A2
A3
A4
Two registered outputs,

two non-registered outputs
Two BUFTs associated
with each CLB, accessible
by all 16 CLB outputs
RAM16X1D
D
WE
WCLK
SPO
A0
A1
A2
A3
DPRA0
DPRA1
DPRA2
DPRA3
Each slice has four outputs
LUT
LUT
LUT
Carry
Carry
Carry logic runs vertically,

up only
Two independent
carry chains per CLB
DPO
Slice 0
PRE
D
Q
CE
CLR
LUT
LUT
Carry
Carry
D PRE
Q
CE
CLR
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Altera Stratix
Logic Array Blocks (LABs)
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Logic Element
Embedded RAM
z
Xilinx Block SelectRAM

18Kb dual-port RAM arranged in columns
Altera TriMatrix Dual-Port RAM

M512 512 x 1
M4K 4096 x 1
M-RAM 64K x 8
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Xilinx: Embedded Multipliers

z
z
z
Altera: Embedded DSP Blocks

Two DSP Block columns per device
z Number varies by height of column
z Can implement:
18-bit twos complement signed operation

Optimized to implement Multiply and Accumulate functions
Multipliers are physically located next to block SelectRAM
memory
Data_A
(18 bits)
Eight 9x9 multipliers

Four 18x18 multipliers
One 36x36 multiplier
4 x 4 signed
18
18xx18
18
Multiplier
Multiplier
Output
(36 bits)
8 x 8 signed
12 x 12signed
Contains adder/subtracter/accumulator
z Registered inputs can become shift register
z
18 x 18signed
Data_B
(18 bits)
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Altera Multiplier Sub-block
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Virtex: Active Interconnect
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Virtex Hierarchical Interconnect
Altera: MultiTrack Interconnect
Direct link between LABs and adjacent blocks

z Row interconnects
z
4, 8, and 24 blocks left or right

z
Column interconnects
4, 8, and 16 blocks up or down
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MicroBlaze Processor-Based Embedded

Design
BRAM
Local Memory
MicroBlaze
32-Bit RISC Core
Bus
Custom
Functions
Arbiter
Fast Simplex
Link
0,1.7
D-Cache
BRAM
Flexible Soft IP
Configurable
Sizes
SRAM
Possible in
Virtex-II Pro
On-Chip Peripheral Bus
10/100
E-Net
Off-Chip
Memory
PowerPC
405 Core
Bus
Bridge
Data
PLB
Processor Local Bus
Hi-Speed
Peripheral
UART
Dedicated Hard IP
Instruction
OPB
Custom
Functions
CacheLink
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I-Cache
BRAM
e.g.
Memory
Controller
Arbiter
Stratix: R4 Interconnect
GB
E-Net
Memory
Controller
FLASH/SRAM
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Embedded Development
Tool Flow Overview
C Code
Standard Embedded
SW Development Flow
Code Entry
Include
the
BSP
C/C++
Cross
Compiler
and Compile the
Software
LinkerImage
2
Load Software
Into FLASH
Embedded
Development Kit
VHDL or Verilog
Standard FPGA
HW Development Flow
HDL Entry
Board Support
Package
System Netlist
Data2MEM
Compiled ELF
Altera Nios II
Compiled BIT
Download Combined
Image to FPGA
Instantiate the
Simulation/Synthesis
System Netlist
and Implement
Implementation
the FPGA
Download Bitstream
Into FPGA
Chipscope
Debugger
RTOS, Board Support Package
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SoPC Builder
Altera Nios II
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Actel Fusion
Actel Fusion - ADC
Temprature
interne
AT9
AG9
AC9
AV9
AT8
AG8
AC8
AV8
AT1
AG1
AC1
AV1
AT0
AG0
AC0
AV0
Analog
Quad
9
Analog
Quad
8
Analog
Quad
1
Analog
Quad
0
31 30
Flash
memory
ADCCLK
ACM
Analog multiplexer
Vcc
(1.5V)
0
5 bits CHNUMBER
[4 :0]
ADC
ADCSTART
12 bits
ADCRESULT [11 :0]

DATAVALID
CALIBRATE
RTC
CLK
1
Analog Bloc
6 MHz
Freq_div
SYSCLK = 50MHz
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Actel ProASIC
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Actel ProASIC
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Design Methodologies EDA Tools
In trouble with a chip design ?
Modern
Traditional
NOTHING EASIER !
Everybody hates EDA tools at

some stage !!!
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Novel Systems Modelling Method
Design flow
z
z
z
z
z
z
z
z
- main features and context -
Design Entry (schematic,

HDL, state diagram).
Compilation
Apply stimulus
Simulation
Implementation and Layout
Timing Analysis / Verification
Download design into silicon
Testing the chip
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Extends the traditional use of Hardware Description Languages (HDLs) for electronic
circuits design, to encompass holistic modelling of more complex engineering systems.
Outcome: design environment that allows all aspects of the system to be simultaneously
considered, therefore maximising performance.
Proposed approach correlated with powerful international movement/leading edge

research, directed towards system level modelling/design.
The international EDA community, united under ACCELLERA (2000)

(http://www.accellera.org/index.html), assumed the mission to drive the worldwide
development and use of standards required by systems, semiconductors & design tools.
Clear proof of the internationally identified need for the development of holistic models
for complex engineering systems.
Proposed for engineering systems holistic modelling: VHDL = Very high speed
integrated circuit Hardware Description Language. (IEEE, 1993).
52
Specific Advantages Offered by VHDL
Advantages of FPGA Controller Prototyping
Allows the functional/behavioural description of an engineering system to be

combined with a detailed electronic design, on the same CAD platform.
The mathematical aspects of systems and the electronic hardware design are
simultaneously addressed, in a unique environment.
A cheap & fast VHDL code validation is via a prototype board containing reprogrammable devices - Field Programmable Gate Arrays (FPGAs).
It is supported by all major Computer Aided Design platforms
Allows electronic controllers hardware validation that provides significant

information before the decision is taken to invest in an Application Specific
Integrated Circuit (ASIC) = IC dedicated specifically to an application.
Ability to handle all levels of abstraction. The system can be simulated as an overall
model during all stages of the electronic controller design, which can be
subsequently targeted for system on a chip silicon implementation.
It shortens the time to correct any design problem and it ensures an error free
design before permanent ASIC implementation.
Fast implementation & relatively short time to market of new designs.
Hardware Implementation of Artificial Intelligence is facilitated.
The prototype board can be used for hardware testing other system
components.
Versatile reusable models / design modules are generated, in accordance with

modern principles of design reuse.
The general benefits of holistic modelling of systems, combined with the

advantages of VHDL and FPGAs, enable the efficient investigation of new
engineering system topologies employing complex electronic controllers.
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Top-Down Design
Engineering Systems Modelling Approach Summary

Modelling / Development: VHDL
VHDL allows the designer to develop and simulate ideas fast, without
getting caught-up in the details of implementation.
As the design evolves to completion, the language is able to support a

complex detailed digital system description.
Top-down design begins with modelling an idea at an abstract level,

and proceeds through the iterative steps necessary to further refine this
into a detailed system.
A test environment is developed early in the design cycle. Concepts are

tested before investment is made in implementation.
As design evolves to new levels of detail, the test environment will

check compliance with the original specification.
Electronic Controller Hardware Prototyping: FPGA

Advantages of using VHDL
Efficient design process

Single environment for modelling, simulation & electronic controller design.
Easy modifications and system integration of designs
EDA platform independence of VHDL designs (ASCII files)
Reusable IP block modelling/design style becomes possible
Advantages of using FPGAs
Small, compact design

Fast, relatively cheap
Reusable hardware framework for testing a design
Short time to market of product, rapid prototyping
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VHDL Description
Design Units
Evolution of the VHDL language began in 1980's and resulted in the

adoption of the VHDL's IEEE Standard (1993).
Due to increased demands of higher levels of integration / faster time-tomarket, a standard language, that referenced a higher level of design
abstraction was needed. This stand-alone specification is not dependent on
any specific tool.
An entire system, once consisting of many components/circuit boards, can

be replaced by one/two integrated circuits.
VHDL's flexibility and choice of modelling styles enable a natural

progression from idea to implementation, giving the designer the ability to
quickly create, simulate, and verify an abstract model.
z
z
Thus, design concepts can be tested before the investment is made in the
hardware implementation.
A major feature of VHDL is its inherent ability to handle all levels of
abstraction. The designer requires the use of only a single language, as
57
well as a single simulator for all phases of design.
For example, an AND gate with 3 connection points, 2 inputs and 1

output and data type bit (values '0' or '1') might look like:
ENTITY and2 IS
PORT (in1,in2: IN bit;
outp: OUT bit);
END and2;
Architecture: defines an entity's behaviour from a simulation point of

view. It depends upon the information declared within an entity.
58
Behavioural Design
A behavioural architecture example for the and2 entity is:

ARCHITECTURE arch1 OF and2 IS
BEGIN
output <= in1 and in2;
END arch1;
A structural architecture of a 3 input AND gate is:

ARCHITECTURE struct OF and3 IS
COMPONENT and2
PORT(sig1,sig2: IN bit;
sig3: OUT bit);
END COMPONENT;
SIGNAL internal:bit;
BEGIN
u1:and2 PORT MAP(sig1=>in1, sig2=> in2, sig3 => internal);
u2:and2 PORT MAP(sig1=>in3, sig2=>internal, sig3=>output);
END struct;
Entity: describes the interface between the outside world and the
design. The connection points (PORTs) to the design, the direction
and type of data that flows through these points are defined here.
z
z
z
59
In VHDL behavioural descriptions there is no reference to submodules within a

specific VHDL architecture.
This does not preclude the use of subprograms within VHDL descriptions, but
precludes the use of other VHDL components.
Behavioural descriptions are defining the design functionality.
A behavioural description of a multiply accumulate device (mac) is:
USE WORK.util.ALL;
ENTITY mac IS
GENERIC(tco: time := 10 ns);
PORT( in1, in2: IN bit_vector(15 DOWNTO 0);
clk, reset: IN bit;
out1: OUT bit_vector(31 DOWNTO 0));
END mac;
ARCHITECTURE behave OF mac IS
BEGIN
PROCESS (clk, reset)
VARIABLE reg_in1, reg_in2, reg_mul, accum: integer;
60
BEGIN
IF reset = '0' THEN
reg_in1 := 0;
reg_in2 := 0;
reg_mul := 0;
accum := 0;
ELSIF rising_edge(clk) THEN
accum := accum + reg_mul;
reg_mul := reg_in1 * reg_in2;
reg_in1 := vect_to_int(in1);
reg_in2 := vect_to_int(in2);
END IF;
out1 <= int_to_vect(accum,32) AFTER tco;
END PROCESS;
END behave;
z
Bit_vector is a one dimensional array of bits. The width of the array is

determined in the port declaration. The width of in1 and in2 is 16 bits while
out1 is 32 bits. They can be visualised as buses.
COMPONENT multiply
PORT( port1, port2: IN bit_vector(15 DOWNTO 0);
output: OUT bit_vector(31 DOWNTO 0));
END COMPONENT;
COMPONENT buf
PORT( input: IN bit_vector(31 DOWNTO 0);
END COMPONENT;
SIGNAL reg_in1, reg_in2: bit_vector(15 DOWNTO 0);
SIGNAL mul, reg_mul, adder, accum: bit_vector(31 DOWNTO 0);
BEGIN
u1: reg
GENERIC MAP(16) PORT MAP(in1, clk, reg_in1);
u2: reg
GENERIC MAP(16) PORT MAP(in2, clk, reg_in2);
u3: multiply
PORT MAP(reg_in1, reg_in2,mul);
u4: reg
GENERIC MAP(32) PORT MAP(mul, clk, reg_mul);
u5: adder
PORT MAP(reg_mul, accum, adder);
u6: reg
GENERIC MAP(32) PORT MAP(adder, clk, accum);
u7: buf
PORT MAP(accum, out1);
END structure;
Structural Design
z
Structural descriptions are categorised by the instantiation & interconnection

of VHDL components. They can be viewed as VHDL netlists.
The architecture's body instantiates as many declared components as needed,

and connects those components by the use of the PORT MAP construct.
A structural architecture for the mac entity is:

ARCHITECTURE structure OF mac IS
COMPONENT reg
GENERIC(width: integer := 16);
PORT( d: IN bit_vector(width-1 DOWNTO 0);
clk: IN bit;
q: OUT bit_vector(width-1 DOWNTO 0));
END COMPONENT;
COMPONENT adder
PORT( port1, port2: IN bit_vector(31 DOWNTO 0);
62
END COMPONENT;
61
Library/Use statement
z
63
The Library Statement: A library can be referenced by the identifier. The

name of the library must be made visible using the LIBRARY statement:
LIBRARY IEEE;
ENTITY test IS
END test;
VHDL implicitly provides two library statements before every design unit,
making the libraries STD and WORK available:
LIBRARY STD;
LIBRARY WORK;
To make a package in a library visible to a design unit, the package must
be specified with a USE statement including: name of a library followed by
a dot '.', package name followed by a dot '.', and reference to a package
element (type, constant, signal, function, etc.). It ends with semicolon ';'.
USE ieee.std_logic_1164.ALL;
Provided implicitly: a USE statement that makes the STANDARD package
from the STD library available to all design units:
USE STD.STANDARD.ALL;
64
VHDL Design for Synthesis
Clock Signal Situations

Flip-flop Output Driving the Clock Input of Another Flip-Flop
The VHDL model is converted into a hardware structure with

the help of synthesis tools.
>ck qb
First the VHDL model is mapped to a hardware structure

described using cells from a technology library. Then the netlist
is placed and routed.
Usually an optimizer is involved in generating the final result

based on silicon area minimisation or speed considerations.
The VHDL code has to be written in a style that is

implementable and generates reliable circuits.
Synchronous circuits are preferred.
>ck qb
Avoiding Gated Clock by Using a Clock Enable
65
66
Clock Buffering
z
z
z
In FPGAs the clock tree is already designed and the clock distribution is dealt
with automatically be the synthesis tool.
For ASIC design it may be necessary to design the clock tree manually.
It is important to avoid:
Clock skew generated by unequal depth of clock buffering.
Unequal load-dependent delays generated by unbalanced clock buffers fan-out.
Slow clock edges due to excessive buffer loading.
Correct Clock Buffering
Incorrect Clock Buffering

z
z
67
The circuit provides the

same buffering depth at all
clocked points;
All buffers have the same
fan-out;
The buffers are lightly
loaded (less than 50% of
maximum fan-out).
68
Shift Registers and Clock Buffering
Situations to be Avoided when Operating with the

Asynchronous Reset
Shift registers are particularly sensitive to clock skew. The register

operation could be incorrect due to set-up and hold problems.
zIt
>ck qb
>ck qb
>ck qb
>ck qb
>ck qb
is recommended to avoid
driving the asynchronous reset
input of one flip-flop using the
output of the other.
>ck qb
clk
>ck qb
>ck qb
r
clk
>ck qb
>ck qb
>ck qb
>ck qb
>ck qb
Combinational
Logic
>ck qb
>ck qb
>ck qb
r
clk
clk
69
Adders and Multiplexers
The Recommended Solution for flip-flops with Synchronous Reset

d
>ck qb
r
>ck qb
r
>ck qb
r
70
architecture arch of entity1 is

begin
outp <= a + b when sel = '0' else
end arch ;
>ck qb
r
re s e t
c lk
Synchronizing Asynchronous Inputs

zA signal conflict may arise at the interface between a synchronous circuit
and an external asynchronous input. It is recommended to synchronize an
asynchronous input by passing it through one or more flip-flops.
d ( e x t e r n a l)
>ck qb
d ( in te r n a l)
sel
>ck qb
a + c ;
M UX
c lk ( in t e r n a l)
71
72
Modelling Sequential Circuits
Optimised Adder and Multiplexer Circuit
To model sequential logic for synthesis, the clock signal must be used,
following some recommendations:
Designate a signal as a clock through its behavioural description (using
IF or WAIT UNTIL statements).
Use at most one clock with at most one active edge.
All procedural statements must completed into a single clock cycle.
Data-dependent loops must be synchronised by clock.
Modelling Clock Signals with WAIT Statements
z
process (sel, a, b, c)
variable in_add : std_logic_vector(5 downto 0);
begin
if sel = '0' then
b
c
in_add <= b ;
else
in_add <= c ;
sel
MUX
end if ;
a
outp <= a + in_add ;
end process ;
Positive clock edge
Wait until clk'event and clk = '1' ;

Wait until not clk'stable and clk = '1' ;
Wait until clk'event and clk = '1' and
clk'last_value = '0' ;
Negative clock edge
Wait until clk'event and clk = 0 ;

Wait until not clk'stable and clk = 0' ;
Wait until clk'event and clk = 0' and
clk'last_value = 1' ;
73
FPGA-based Controller Design main rules
Some Remarks on VHDL Design for Synthesis

z
VHDL elements which are not synthesizable: AFTER, WAIT FOR,

ASSERT, File operations, REAL signals.
Write all input signals in the sensitivity list, otherwise they will be
latched.
CASE and IF statements must be complete. For std_logic signals the

CASE statement needs OTHERS and IF needs ELSE.
Avoid instantiating too many components because this worsens the size
of optimised implementation.
Avoid large combinational multipliers and dividers. When complicated

equations are used, design the circuit so that all the operands share a
single multiplier or divider.
74
Use of FPGAs for the control of industrial systems
?
Algorithm
Hardware
architecture
Definition
a set
of steps
rules
Definition
of aofset
of steps
andand
rules
of for the a
development
of
a
design
methodology
design methodology
Do not use INTEGER without RANGE:

SIGNAL x: INTEGER RANGE 0 TO 255;
75
76
Design Methodology
Design Methodology
Different steps
Objectives
Modular partitioning
of the algorithm
9 To ensure a more automated and less intuitive approach for the

design of FPGA-based control systems
Simulation procedure
9 Reduction of the development time

Optimization of the
consumed resources
9 Development of a specific library of reusable modules dedicated

to the control of electrical systems
Architecture design
9 First attempt success guarantee of the designed architecture
Validation of the architecture

77
78
Design Methodology
Design Methodology
Continuous Model of a FOC Estimator
Modular partitioning of the algorithm
Reduction of the development time

Extraction of reusable modules
Modle continu
Continuous
Model
Example : dX/dt (X[k+1]-X[k])/Ts
Discrete Model
X/Xb
Per Unit Dicrete Model

79
80
Design Methodology
Design Methodology
Continuous Model of a FOC Estimator

isd =2/3(sin(+60) is1 + sin() is2)
Continuous Model
Simplification
isq =2/3(sin(+150) is1 + cos() is2)
Euler: dX/dt (X[k+1]-X[k])/Ts
r = Lm/(1+Trs) isd
Wdq = w + Lmisq/(Trr)
Discrete Model
Cem = (3/2)p(Lm/Lr) r isq

sd = Lsisd + (Lm/Lr)r
sq = Lsisq
Per Unit Discrete Model
ddq/dt = wdq
81
82
Design Methodology
Design Methodology
Continuous Model
Digital Model of a FOC Estimator
isd[k]=a0(sin([k]+60) is1[k] + sin([k]) is2[k])
isq[k]=a1(sin([k]+150) is1[k] + cos([k]) is2[k])
r[k]=a2 isd [k-1]+ a3 r[k-1]
Wdq [k] =a4 w [k] + a5 isq [k] /r [k]
Cem [k] = a6 r [k] isq [k]
sd [k] = a7 isd [k] + a8 r [k]
sq [k] = a9 isq [k]
dq [k] = dq [k-1] + a10 wdq [k-1]
a0 = 2/3
a1 = 2/3
a2 = Lm Te/Tr
a3 = 1 - Te/Tr
a4 = 1
a5 = Lm/Tr
a6 =(3/2)pLm/Lr
a7 = Ls
a8 = Lm/Lr
a9 = Ls
a10 = Te
Discrete Model
Per Unit Discrete Model

83
84
Design Methodology
Design Methodology
Per Unit Digital Model of a FOC Estimator
A0 = a0
A1 = a1
A2 = a2Ib/b
A3 = a3
A4 = a4wb/wdqb
A5 = a5Ib/(wdqbb)
A 6 = a6
A 7 = a 7 Ib / b
A8 = a8
A9 = a9Ib/b
A10 = a10wdqb
isd[k] =A0(sin([k]+60) is1[k] + sin([k]) is2[k])

isq[k] =A1(sin([k]+150) is1[k] + cos([k]) is2[k])
r[k] = A2 isd [k-1] + A3 r[k-1]
Wdq[k] = A4 w[k] + A5 isq[k]/r[k]
Cem[k] = A6r[k] isq[k]
sd[k] = A7 isd[k] + A8 r[k]
sq[k] = A9 isq[k]
Example 1 : FOC Estimator algorithm
is1
is2
isd
abc to dq
Transformation
(1)
Low Pass
Filter
(2)
r
Library
isq
dq
Integrator
(4)
dq
dq, TL, sd et sq
Estimator
(3)
isd
dq[k] = dq[k-1] + A10wdq[k-1]
TL
85
Design Methodology
sd
sq
86
Design Methodology

Current Control, Torque Control
Speed Control,
Example 2 : Sliding Mode Torque Control algorithm
Isd*
T L*
Table
(1)
Isq*
is1*
dq to abc
Transformation
(2)
is2*
is3
Level 3
Full Control Algorithms
Creation of a specific Electrical System

dedicated library
Hysteresis
Controller
(3)
is1
is2
PI, PID, PPI, Hysteresis controller,
PWM, SVM,
Sb
Regulation
Modulation
Sc
PLL, Torque Estimator, Flux

Estimator
abc-to-, -to-abc, abc-to-dq, dqto-abc
Estimation
Vector Operators
Registers, multiplexers,
demultiplexers,
Adder, multiplier,
sine-cosine, cordic,
Basic Operators
Arithmetic Operators
Sa
is3
Library
87
Level2
Level 1
88
Design Methodology
Design Methodology / Web Site
Library of IP modules dedicated to the Control of Electrical Systems

9 VHDL Programs
9 Matlab Simulink Models
9 Data-sheets
89
90
Design Methodology
Design Methodology
1) Development of a continuous functional continuous model
Verification of the algorithm functionality
Verification of the algorithm functionality

Choice of the suitable sampling period
and fixed-point format
Example 1 : Per Unit FOC Estimator functional model
IFO
Controller +
VSI
Induction
motor
Estimator
algorithm
91
92
Design Methodology
Design Methodology
2) Development of a discrete fixed-point specification model
Example 2 : Per Unit Sliding Mode Torque Control functional model

VSI
Choice of the sampling period and fixed-point format of the digital algorithm
SM
Example1 : FOC Estimator specification model
Torque control
algorithm
93
Design Methodology
94
Design Methodology
Example2 : Sliding Mode Torque Control specification model
Example2 : Sliding Mode Torque Control specification model
95
96
Design Methodology
Design Methodology
5/6
/3
U[p/Q0]
/2
U[p/Q0]
U[p/Q0]
U[p/Q0]
isa[k]
Sin
S[n/Qn-1]
U[p/Q0]
Sin
x
S[n/Qn-2]
Reduction of the consumed resources
S[n/Qn-2]
x
S[n/Qn-1]
S[n/Qn-1]
isq[k]
dq-to-abc transformation
specification model
Optimization procedure
x
S[n/Qn-2]
A0
S[n/Qn-2]
Sin
S[n/Qn-1]
S[n/Qn-2]
A1
isb[k]
Sin
S[n/Qn-1]
S[n/Qn-2]
S[n/Qn-2]
+
U[p/Q0]
S[n/Qn-1]
dq[k]
U[p/Q0]
isd[k]
Dq-to-abc transformation
Data Flow Graph (DFG)
Lots of possibilities in terms of parallelism
97
98
Design Methodology
Design Methodology
Generation of optimized hardware architecture (A3 methodology)
dq[k]
U[p/Q0]
Factorization
x1
A1
S[n/Qn-1]
A2
x2
S[n/Qn-1]
S[n/Qn-1]
x
S[n/Qn-1]
Execution time
x1
x2
0
/3
/2
5/6
A0
A1
Hardware resources
S[n/Qn-1]
S[n/Qn-1]
S[n/Qn-1]
S[n/Qn-1]
S[n/Qn-1]
S[n/Qn-1]
S[n/Qn-1]
S[n/Qn-1]
S[n/Qn-1]
A1
+
U[p/Q0]
Sin
S[n/Qn-2]
S[n/Qn-1]
FF1
S[n/Qn-1]
S[n/Qn-1]
isa[k]
isb[k]
J
S[n/Qn-2]
FF0 : Factorization Frontier 0
Defactorization
FF0
U[p/Q0]
S[n/Qn-1]
S[n/Qn-1]
U[p/Q0]
S[n/Qn-2]
A2
S[n/Qn-1]
Oprations
DFG
FDFG
Addition
Multiplication
Sine
S[n/Qn-1]
+ i [k] i [k] +
sq
sd
FF1 : Factorization Frontier 1
Hardware resources
abc-to-dq transformation
Factorized Data Flow Graph (FDFG)
Execution time
99
100
Design Methodology
Design Methodology
1) Modular Hardware Architecture Design
S1
S3
Start
S2
End
S3
Control unit
Output Data
Input Data
Reset
Clk
Specific
Library
Data-path
Module name
Generic Second Level Module Architecture
Architecture Design
Latency*TClk
TClk
Clk
Start
Input Data
Inputs[k]
Inputs [k+1]
Inputs [k+2]
End
Output Data
Outputs [k]
Design Methodology
Example : FOC Estimator algorithm architecture
Global Control Unit

End1 Start2 End2
Sel Start3 End3
Startn
Sub-Module
1
Endn
Sub-Module n
Sub-Module 3
Input
Data
Sequencer
Output
Data
isa
Sub-Module 2
isb
Reset
Clk
Global sequencer
End
en
102
Design Methodology
2) Design of the whole algorithm architecture
Start1
Outputs [k+2]
Generic Timing Diagram
101
Start
Outputs [k+1]
Data-path
abc-to-dq
isd
Sequencer
Data-path
isq
Sequencer
LP_Filter
transformation
Global Data-path
Module Name
dq
Sequencer
Data-path
Third Level Module Architecture
Global data-path
Specific
Library
Integrator
Data-path
dq
dq, TL, sd and sq

Estimator
TL
isd
sd sq
FOC Estimator Architecture

103
104
Design Methodology
Design Methodology
3) VHDL coding of the architecture
3) VHDL coding TOP DOWN Approach
Mixed Simulation
Environment
Analog
HDL
Simulation
Simulation
Test
Bench
Simulation
Simulation
Behavioral
HDL
Synthesis
System
Level
Circuit
Specifications
Behavioral
Level
RTL or Synthesis
Level
FPGA
Physical
Level
105
ASIC
106
Design Methodology
Design Methodology
3) VHDL coding - Reusability
System
Level
Behavioral
Level
RTL or Synthesize
Level
Library
Library
Reuse and IP
Behavioral M odel
Blocks
Reuse and IP
RTL or Synthesize
M odel Blocks
Architecture Design
Validation of the architecture

Physical
Level
107
108
Design Methodology
Design Methodology
1) Hardware in the loop test

Example : Hardware in the loop results of the FOC Estimator
First attempt success guarantee

Stimuli
Patterns
Functional model
simulation
Architecture
to be tested
Start-up and a speed reversal at 0.27s of a 1 Kw induction machine controlled by a

classical Indirect Field Oriented Strategy.
Serial
interface
Simulation results (isd(A) and isq(A))
FPGA Target
5
4
Configuration process
Host-PC
Hardware in the loop results (isd(A) and isq(A))
Tx
Rx
isd
1
0
Results
isq
-1
Results
Reception
Comparison
-2
isq
-1
-2
-3
-3
-4
-4
-5
-5
0
0.05
0.1
0.15
0.2
0.25
0.3
0.3 5
0.05
0.1
0.15
time(s)
Hardware in the loop Results
Simulation Results
isd
0.2
0.25
0.3
0.3 5
time(s)
109
110
Design Methodology
Design Methodology
Simulation results r(Wb)

Simulation results (T(Nm))
Hardware in the loop results (T(Nm))
Hardware in the loop results r(Wb)
0 .9
0.9
0 .8
0.8
0 .7
0.7
0 .6
0.6
0 .5
0.5
0 .4
0.4
0 .3
0.3
0 .2
0.2
-4
0 .1
0.1
-6
-6
-8
-8
-2
-2
-4
0.0 5
0 .1
0 .15
0.2
time(s)
0.2 5
0 .3
0 .35
0
0
0 .05
0.1
0 .15
0.2
0 .25
0.3
0.0 5
0.1
0 .15
0 .2
time(s)
0 .35
0.25
0.3
0.3 5
0.0 5
0 .1
0 .15
0.2
0.2 5
0 .3
0 .35
time(s)
time(s)
Slight difference between simulation and hardware in the loop results
111
112
Design Methodology
Design Methodology
2) Experimental test
FPGA (Actel Fusion)113
Algorithm
114
1st Case Studies Series:
Conclusion
Design Methodology
FPGA (Actel Fusion)
Hardware
architecture
FPGA-Based Current Controllers for
Advantages :
Synchronous Machine Drive

Less intuitive and more automatic approach
Advantages & Features
Reduction of the development time

Optimization of the consumed resources
Reusability of the design
Development of a specific library
First attempt success guarantee
115
116
Experimental Set-up
Control Algorithm Execution Time

Electrical Supply
Controlled
Inverter
Synchronous Machine
(a) General purpose microcontroller:

- c limitations !
Vf
isa
(a)
(k)Ts
(k-1)Ts
(k+1)Ts
(b)
(k)Ts
(k-1)Ts
TADC
(k+1)Ts
Interface
(b) DSPcontroller:
- VSI limitations
Controller
(c)
(k)Ts
Encoder
Amplification
(k+1)Ts
ADC
Sa Sb Sc
TC
(c) FPGA-based controller:

- Quasi-analog behavior
isa
isa
isb
isb
dq
Host PC
References
RS232
117
Experimental Set-up
isb
isbADC Control
ADC
Interface
Encoder
Interface
Serial Interface
FPGA
118
Experimental Set-up
Voltage Source Inverter
Current sensors
VSI
Interface
Board
FPGA
Spartan3
Encoder
SM
400.000 Gates
AD Conversion Board
119
120
Current Controllers Based on ON-OFF regulators
9 Simplest current regulation schemes
Tow Main groups
Current Controllers Based on ON-OFF Regulators

Variable switching frequency
ON-OFF regulators
Limited switching frequency

ON-OFF regulators
9 Well adapted for analog controls
9 Well adapted for analog & digital

controls
121
122
Variable Switching Frequency ON-OFF regulators

9 Example 1 : Independent three phase free running hysteresis regulators
Start
E
isd*
isq*
dq-to-abc
Sa
Sb
Sc
isb*
isc*
End_AD
isaAD
AD
Interface
Clk
End_OO
Global control unit FSM
ON-OFF Current controller

Algorithm control unit
isd*
dq-to-abc
isq*
Clk
isc isb isa
Reset
isa*
Clk
isbAD
AD Control
isa isb isc
dq
Start_OO
Start_AD
isa*
End
Global control unit

Clk
isb*
isc*
2 level hysteresis
comparators
Sa
Sb
Sc
Clk
dq
SM
tAD
9 TS = TAD = 2.4 s
9 Tex= TAD+ tIP+ tH2 = 2.74 s
Vrd
Controller computation time

123
wait
Start_AD=1
Start_OO=1
Tex
Encoder
End_AD=1
Start=1
Hardware Architecture
End=1
wait
Application
Sa,b,c[k-1]
tIP
tH2
tAD
Ts
Sample
isa[k-1]
isb[k-1]
dq[k-1]
Application
Sa,b,c[k]
tIP
tH2
tAD
Sample
isa[k]
isb[k]
dq[k]
Sample
isa[k+1]
isb[k+1]
dq[k+1]
Application
Sa,b,c[k+1]
tIP
tH2
124
Low execution time
Low execution time
Effects of sampling and delays are very negligible
H
isa
isa
isa
isa
H
isa
isa
isb
isb
H
isa
Execution time = 50 s
isa
isa
isa
isa
isb
isa
isb
Execution time = 2.74 s
125
126
9 Example 2 : Space vector based regulator with three level hysteresis

comparators and look-up table working in the - reference frame

Start
isa*
isb*
isd*
isq*
dq-to-abc
isa*
isb*
isc*
is*
abc-to-
is*
+
-
+
-
isb<isc
is
Table
is
End
Global control unit

Clk
End_OO
Start_OO
Start_AD
End_AD
Clk
isaAD
Sa
Sb
Sc
AD
Interface
isbAD
AD Control
Clk
isc isb isa
isd*
isa*
dq-to-abc
isq*
dq
Reset
isb*
isc*
Clk
is*
abc-to-
3 level hysteresis
comparators
is*
S
Table
Sa
Sb
Sc
Clk
Clk
is
|isb|<|isc|
Clk
abc-to-
abc-to-
is
End_AD=1
Start=1
Clk
is
End=1
wait
wait
Start_AD=1
Start_OO=1
isb* isc* isb isc
Clk
is
dq
isa
isb
h&h
isa isb isc
Tex
9 TS = TAD = 2.4 s
SM
tAD
Application
Sa,b,c[k-1]
tIP tC tH3 tT
tAD
Ts
9 Tex= TAD+ tIP +tC+ tH3+tT = 2.92 s
Encoder
Vrd

127
Sample
isa[k-1]
isb[k-1]
dq[k-1]
Application
Sa,b,c[k]
tIP tC tH3 tT
tAD
Sample
isa[k]
isb[k]
dq[k]
Sample
isa[k+1]
isb[k+1]
dq[k+1]
Application
Sa,b,c[k+1]
tIP tC tH3 tT
128
Low execution time
Low execution time
H
is
is
is
is
is
is
is
H
is
H
is
is
is
H
is
is
is
is
is
Limited Switching Frequency ON-OFF regulators
isd*
isq*
dq-to-abc
Start
Start_OO
Start_AD
isaAD
AD
Interface
Clk
Sc
End_AD
End_OO

isd*
dq-to-abc
isq*
Clk
isc isb isa
Reset
isa*
Clk
isbAD
AD Control
Sb
End
Global control unit

Clk
Sa
isa*
isb*
isc*
130

Ts
129
isb*
isc*
2 level hysteresis
comparators
Sa
Sb
Sc
Clk
dq
End_AD=1
Start=1
wait
Start_AD=1
Start_OO=1
isa isb isc
End=1
wait
Ts
dq
SM
9 TS = tAD = 100 s
p
Encoder
9 Tex= tAD+ tIP+ tH2 = 2.74 s
Vrd

131
Fs
Start
Ts
Tex
tAD
Sample
isa[k]
isb[k]
dq[k]
tIP tH2
Application
Sa,b,c[k]
tAD
Sample
isa[k+1]
isb[k+1]
dq[k+1]
tIP tH2
Application
Sa,b,c[k+1]
132
Low execution time

isa*
isb*
isa
is
isa
isd*
THD=14.9%
isq*
THD=8.9%
dq-to-abc
isa
isb*
isc*
abc-to-
is* +
+
-
isa
isb
isb<isc
Ts
E
Sa
is
Sb
Table
is
Sc
is
abc-to-
is
isa isb isc
SM
dq
Square current vector error (is+is)
Vrd
133
Clk
AD
Interface
isbAD
AD Control
Clk
isc isb isa
isd*
isa*
dq-to-abc
isq*
dq
Reset

Clk
isaAD
Clk
isb*
isc*
is*
abc-to-
3 level hysteresis
comparators
is*
S
Table
Sa
Sb
is
wait
|isb|<|isc|
Clk
abc-to-
isa
End_AD=1
Start=1
Clk
is
isa
End=1
wait
Sc
Clk
Clk
End_OO
Start_OO
End_AD
Low execution time
End
Global control unit
Start_AD
134

Start
p
Encoder
Start_AD=1
Start_OO=1
isb* isc* isb isc
Clk
THD=11.1%
THD=8.9%
h&h
9 TS = tAD = 2.4 s
9 Tex= tAD+ tIP +tC+ tH3+tT = 2.92 s
Ts
Fs
Tex
Start
tAD
Sample
isa[k]
isb[k]
dq[k]
Ts
tIP tC tH3 tT
Application
Sa,b,c[k]
tAD
Sample
isa[k+1]
isb[k+1]
dq[k+1]
tIP tC tH3 tT
Application
Sa,b,c[k+1]
135
136
Current Controller Based on PI Controllers
isq *
Vsd
isd *
Vsq*
+
-
dq-to-abc
Vsa
Vsb*
Vsc*
PWM
Modulator
Sa
Sb
Sc
isd
isa isb isc
dq-to-abc
isq
dq
SM
p
Encoder
Vrd
137
138

9 Case 1 : Synchronized PWM
Start
End
Global control unit

Start_VC
Clk
Carrier
End_VC
Vector current controller

Start_AD
End_AD
Algorithm controller
Ts = tPWM/2
Clk
Start
Vsd*
isd*
is1AD
AD
Vsa*
Sa
PI
Interface
Clk
is2AD
dq-to-abc
Vsq*
isq*
PWM
End_VC
Sb
Vsc*
PI
AD Control
Vsb*
Tex
Sb
tPWM/2
tPWM/2
Clk
Clk
isb
isa
isq
isd
Clk
tAD
Clk
abc-to-dq
Sample
isa[k]
isb[k]
dq[k]
Clk
dq
tAD
tVC
Application
Vsa,b,c*[k]
9 TS = TPWM / 2
139
Sample
isa[k+1]
isb[k+1]
dq[k+1]
tVC
tAD
Application
Vsa,b,c*[k+1]
Sample
isa[k+2]
isb[k+2]
dq[k+2]
tVC
Application
Vsa,b,c*[k+2]
9 Tex= tAD+ tVC = 3.28 s

Vector Control computation time
140
9 Case 1 : Synchronized PWM
9 Case 2 : Non Synchronized PWM

Carrier
Carrier
1 >
Carrier
Ts
Ts
2 >
1) Ch 1:
2) Ch 2:
Carrier vertex
1 >
tk
2 >
Start
1) Ch 1:
2) Ch 2:
Tex
1 >
End_VC
2 >
200 mVolt 10 us
2 Volt 10 us
Start
Tex
tk+1
tk+2
tk+m
Sample
isa[k]
isb[k]
dq[k]
End_VC
Sample
isa[k+m]
isb[k+m]
dq[k+m]
Application
Vsa,b,c*[k]
9 TS = 5 s
1) Ch 1:
2) Ch 2:
tk+m+1
Tex
tk+m+2
2 >
Carrier vertex
1 >
Ts
Tex
200 mVolt 250 us

2 Volt 250 us
200 mVolt 10 us
2 Volt 10 us
Application
Vsa,b,c*[k+m]
Start
1) Ch 1:
2) Ch 2:
9 Tex= tAD+ tVC = 3.28 s

Vector Control computation time
141
End_VC
200 mVolt 2.5 us

1 Volt 2.5 us
142
9Experimental Results
9Experimental Results
isa
Carrier Frequency = 1KHz
Vsa
isd
isb
1 >
isa
Vsb
isq
THD=11.1%
THD=11.1%
2 >
1) Ch 1:
2) Ch 2:
25 ms
25 ms
isa
isa
1 Volt
1 Volt
isb
isb
THD=4.1%
143
144
Predictive Current Controller

9 Sate model of the synchronous machine in the dq rotor reference frame
di sd
dt
di
sq
dt
1

Tsd
= L
sd
(t )
Lsq dq
Lsd
1
dq (t )
i
Lsq
sd + Lsd
1
isq 0
Tsq
V sd
Vsq

dq (t ) i
rd
1
Lsq
M sr
Lsq
9 Digital Prediction Equations
i sd [ k + 1] =
i sq [ k + 1] =
where
T
Ts
(V sd [ k ] e sd [ k ]) + (1 s )i sd [ k ]
T sd
L sd
Ts
T
(V sq [ k ] e sq [ k ]) + (1 s )i sq [ k ]
L sq
T sq
e sd [ k ] = L sq dq [ k ]i sq [ k ]
e
[
k
]
=
L
sq
sd dq [ k ]i sd [ k ] + M sr dq [ k ]i rd [ k ]
145
146
7 different stator voltage vectors Vsdqj=[Vsdj Vsqj]t (j=0..7)

V sdj cos( dq )
j=
V sq sin( dq )
sin( dq ) V sj
cos( dq ) V sj
isdqj[k+1]
q
isdq1[k+1]
tj[k]
isdq*[k]
7 different directions tj(j=0..7) and errors j(j=0..7)

r
r
r
t j [ k ] = i sdqj [ k + 1] i sdq [ k ]
isdq
r j
r*
r
isdq
[ k + 1] = isdq
[ k ] isdqj [ k + 1]
isdqj[k+1]
Ts
Ts
j
j
isd [ k + 1] = L (Vsd [ k ] esd [ k ]) + (1 T )isd [ k ]
sd
sd
Ts
Ts
j
j
isq [ k + 1] =
(Vsq [ k ] esq [ k ]) + (1
)isq [ k ]
Lsq
Tsq
esd [ k ] = Lsq dq [ k ]isq [ k ]
where
=
e
[
k
]
Lsd dq [ k ]isd [ k ] + M sr dq [ k ]ird [ k ]
sq
*[k]
t3
isdq[k]
Predicted current error vector isdqj
147
t2
isdq1[k+1]
t
t1 6
t0,7
t4
t5
isdq[k]
Example of different prediction possibilities
148

9 Hardware architecture
9 Predictive Controller Principle
Start
Global control unit

Clk
Start_AD
isq*
End_AD
Sa
isd*
(isdqj)(j=0..7)
Prediction
isd*
isq*
Sb
Optimization
EAD
isaAD
isbAD
AD Control
Sc
esd esq
isd
Coupling
terms
isq
Clk
m
isa
abc-to-dq
End
Start_Pr
Predictive current controller
Algorithm controller
End_Pr
Reset
E
AD
Interface
Prediction
esd & optimization
isd
isa
abc-to-dq
isb
Clk
Clk
esq
End_AD=1
Start=1
wait
Start_AD=1
Start_OO=1
Clk
Speed
Estimator
End=1
wait
Clk
dq
+
+
offset
isb
Coupling
terms
isq
Sa
Sb
Sc
dq
Clk
Ts
dq
d/dt
SM
dq
Fs
Start
9 TS = 100 s
9 Tex= tAD+ tPr = 4.52 s

Vrd
Tex
tAD
Ts
tAD
tPr
Sample Application
isa[k] isb[k]Sa,b,c[k]
dq[k]
Predictive Controller computation time
Sample Application
isa[k+1] Sa,b,c[k+1]
isb[k+1]
dq[k+1]
149
tPr
150
9 Experimental Results
isa
isa
isb
THD=8.8%
isq
isq
THD=8.8%
isd
isa
Vsa
isb
+ Isn
+ Isn
- Isn
isd
- Isn
Vsb
151
152
Problem Positioning
Objective : Development of a high performance FPGA-based speed controller
FPGA-Based speed control for
Most important criteria for the speed control
Synchronous Machine Drive using PPI controller
9 Fast speed dynamic

9 Accurate speed response
9 Quick speed recovery from disturbances
153
154
Speed Controller Design
9 Synchronous machine model
9 Current controller
V sd
q isq
Vsq
dq
sd
isd
ird
dq
V sq
Vsd
d sd
= R s i sd +
sq
dt
d sq
= R s i sq +
+ sd
dt
= Lsd isd + M sr ird
isd*
isq*
dq-to-abc
isa*
Sa
isb*
isc*
Sb
Sc
isa isb isc
sq = Lsq isq
Vrd
Sa
rd = Lrd ird + M sr isd
dq
3
Te = p ( sd isq sq isd )
2
SM
p
Encoder
Vrd
155
156

9 Speed controller synthesis
9 Current controller
Current Controller Timing Diagram
Ts=100 s
Tr
Ts=100 s
Tex=2.74s
TAD
TCC
tk
Isn
TAD
Application
Sa,b,c[k]
Sample
isa,b[k+1]
dq[k+1]
PI
Kv
isq
1
T isq s + 1
isq
pMsrird
p
Js + f
TCC
time
tk+1+Tex
Current Control Loop
Application
Sa,b,c[k+1]
Internal Loop (Proportional controller)
isq
- Isn
tk+1
tk+Tex
Sample
isa,b[k]
dq[k]
+
-
Speed Control Loop
isa
isd
isa
isb
External Loop (PI controller)
isb
157
158
Internal Loop (Proportional Controller)
Impose the controlled system

poles at the desired positions
Kv
Proportional
Gain
isq
isq
1
T isq s + 1
pMsrird
p
Js + f
+
-
PI
(s +
1
1 2
)
2Tisq
=1
External speed control loop transfer function
Re
=1
PI
Im
Internal speed control loop transfer function
1 .5 K v p M sr i rd
JT isq
=
1 .5 K v p M sr i rd
1
i
s +
s+
Tisq
JT isq
+
-
Tr
*
External Loop (PI Controller)

- Zero steady-state error
=
1 2
i
(s +
)
- Impose the shape and the dynamic of

the speed response
2T isq
Roots Locus
159
1 .5 K p K v p M sr i rd
=
*
JT isq
1 .5 K p K v p M sr i rd
1
s +
s+
JT isq
2T isq
2n
n2
160
400V/50Hz
9 Speed estimator design

Backward difference
10 bits
+1
[k ] =
Current Controller
Speed Controller
*
isd*
dq-to-abc
isq*
Kv
isa*
Sa
isb*
isc*
Sb
Sc
1024 points
Absolute Encoder
4 m [ k ] m [ k 1]
(
)
1024
T
Variable sampling period

Operating mode synchronized with state changes of the LSB of the
encoder
isa isb isc
Internal Loop
SM
(P9 P8..P1 P0)
Determined via the state changes of the two LSB P0 and P1

External Loop
SM
dq
d/dt
[ k ] = Sense
Encoder
Speed Estimator
Vrd
4 1
1024 Tk
Denotes the time spent for one unit displacement of the

encoder
161
162

Tk Computation
Sense Computation
P0[k]
P1[k]
P0[k+1]
P1[k+1]
Sense
+1(positive)
-1(negative)
+1(positive)
-1(negative)
+1(positive)
-1(negative)
+1(positive)
-1(negative)
Data-Path
P0
Counter
ETAT0
Clk
1 2
nk 0
Fcompt
nk+1
Rc
1/Fc
P0
Compteur
[ k ] = Sense
n
Tk = k
Fc
4 1
1024 T k
en2
Determined via the state changes of the two LSB P0 and P1
Clk d0=0
en1
Clk
ETAT2
Fcompt=1
Clk
Sense Computation
+
-||
en0
en1
XOR
d0
Start=1
ETAT1
en0=1
P1
en0
nk
||
4 1
[ k ] = Sense
1024 Tk
Reset
Control Unit
T(k+1)
Tk
d0=1
ETAT3
en2=1
Clk
ETAT4
en3=1
en3
Denotes the time spent for one unit displacement of the

encoder
Clk
ETAT5
en1=1
Rc=1
Clk
Speed Estimator Hardware Architecture

163
164
9 Speed controller architecture
9 Experimental Set-up
400V/50Hz
Vrd
Speed Controller Timing Diagram

Start
Global control unit
Ts=100 s
End
Clk
Speed controller control unit
is1_AD
is2_AD
is1*
is2*
is3*
Clk
AD
AD
control Clk
Interface
*
is1 is2 is3
P-PI
Clk
isd*=0
isq*
(dq/123)
Clk
Clk
Speed
estimator
3 Phases
hysteresis
controller
TAD
offset
tk
FPGA-based Speed controller
isa
Tex=3.45s
C1
C2
C3
Clk
isb
Ts=100 s
Sample
isa,b[k]
dq[k]
TCC TSC
tk+Tex
Application
Sa,b,c[k]
TAD
tk+1
tk+1+Tex
Sample
isa,b[k+1]
dq[k+1]
Application
Sa,b,c[k+1]
Encoder
Interface
TCC TSC
Amplification
A/D
time
Sa Sb Sc
Speed
Controller
isa
isa
isb
isc
isbAD Control
dq
AD
Interface
Host-PC
Note : The speed estimator works independently from the other modules and is
synchronized to the state changes of the LSB of the encoder
References
Serial Interface
RS232
FPGA
Spartan3 Xc3s400
(400.000 gates)
165
166
Step Speed Response
Speed tracking performance
Current waveforms
Current waveforms for a

reversal speed operation
isa
=200 rad/s
isa
=200 rad/s
=0 rad/s
isb
isb
=0 rad/s
Response to a step of a rated load torque

=200 rad/s
=-200 rad/s
=200 rad/s
TL=5Nm
=-200 rad/s
167
168
Conclusions
Induction Motor Experimental Set-up

LOAD
IM
400V/50Hz
A full FPGA-based speed controller for SM drive has been presented

A very efficient P-PI speed regulator has been synthesized
VSI Interface
An original speed estimator has been developed, it allows to obtain the best accuracy
Gate pulses
An original speed estimator has been developed, it allows to obtain the best accuracy
controller
algorithm
The obtained experimental results give proof of the ability of the developed speed control
system to achieve an efficient and robust speed control under different operating conditions
isa
isb
isc
AD
Interface
AD
Control
12
12
AD
10
Encoder
References
RS232
UART
FPGA
169
170
Interface
and
Control
Boards
IM
VSI
AD Converters
Board
VSI
Interface
Board
FPGA
Spartan 2
100.000 Gates
Laboratoire Systmes lectriques
172

Load Control
Load

ADC Board
VSI
Incremental
Encoder
Induction
Machine
University of Aleppo
VSI Interface
Board
173
2nd Case Studies Series:
SY N C H R O N ISATIO N : (C arrier-triangular / M odulator-sinusoidal)
C ounter output bus
* A PWM control system modelling / design / FPGA

implementation using VHDL
174
* PWM Control System Design Using VHDL
FPGA-based Intelligent Controllers for AC Drives and

AC Generators:
FPGA Spartan 3
400.000 Gates
Triangular waveform generator

M ax_count
M ax_count
Modelling an induction motor drive system using

an FPGA PWM neural controller
C lock
(R eversible up-down counter)
Start
R eset
O U T_SIGN AL
C O N TR O L
C O M PAR ATO R
C lock
Modelling a diesel driven generator employing

fuzzy-logic/PWM FPGA control
(PW M )
N ext
Address
generator
M em ory
(Sinewave)
175
176
Block diagram of the 3-phase PWM circuit
Three-Phase Sinusoidal PWM Pattern Generation
177
Complete VHDL Code - 1 Phase PWM Generator

library ieee;
use ieee.std_logic_1164.all;
entity pwm is
port(out_signal: out std_logic;
clock,start: in std_logic;
Max_count: in integer);
end pwm;
architecture behav of pwm is
signal counter_out_bus : integer;
signal next_pulse,reset: std_logic;
signal val_max, adr, data: integer;
begin
counter_rev: process(clock,reset)
variable direction: std_logic :='1';
variable v: integer :=0;
begin
if reset'event and reset='1' then
v:=1;
elsif clock'event and clock='1' then
if direction='1' then
if v<val_max then
v:=v+1;
else
v:=v-1;
direction:='0';
end if;
else
if v>-val_max then
v:=v-1;
else
v:=v+1;
direction:='1';
end if;
end if;
end if;
counter_out_bus<=v;
end process;
adr_gen: process (next_pulse,reset)
179
178
begin
if reset='1' then
adr<=0;
elsif next_pulse'event and
next_pulse='1' then
adr<=(adr+1) mod 18;
end if;
end process;
comparator:
process(counter_out_bus,data)
begin
if data<counter_out_bus then
out_signal <= '0';
else
out_signal <= '1';
end if;
end process;
memory: process(adr)
type mem_data is array (0 to 17) of integer;
variable d : mem_data :=(-250,-230,-190,100,0,100,190,230,250,250,230, 90,100,0,
-100, -190,-230,-250);
begin
if adr >=0 and adr<18 then
data<=d(adr);
else
data<=0;
end if;
end process;
control:
process(start,clock,counter_out_bus,
Max_count)
variable temp_Max_count: integer;
begin
if Max_count'event then
temp_Max_count:=Max_count;
end if;
if start='1' and start'event then
temp_Max_count:=Max_count;
val_max<=temp_Max_count;
reset<='1';
next_pulse<='0';
elsif start='1' and clock='0' and
clock'event then 180
reset<='0';
end if;
if
counter_out_bus=-val_max
clock='0' and clock'event then
next_pulse<='1';
val_max<=temp_Max_count;
elsif clock='1' then
next_pulse<='0';
end if;
if start='0' then
reset<='1';
end if;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity test is
end test;
end behav;
and
architecture arch_test of test is

component pwm
port(out_signal : out std_logic;
clock,start: in std_logic;
Max_count: in integer);
end component;
signal clock: std_logic :='0';
signal start: std_logic := '0';
signal Max_count: integer;
signal out_signal: std_logic;
begin
Max_count<=300, 500 after 40 ms;
clock <= not clock after 1 us;
start <= '1' after 5 ns;
x: pwm port map(clock=>clock,start
=>start, Max_count=>Max_count,
out_signal=>out_signal);
end arch_test;
configuration conf_test of test is
for arch_test
end for;
end conf_test;
Simulation Results of the 3-phase PWM circuit
181
Achievements
Original design of a 3-phase PWM generator, successfully
modelled, designed and simulated using VHDL.
182
1. Modelling of an induction motor drive

system using PWM neural controller
Important original aspect = the (64x2) ROM, efficiently targeted by

a three-way routing circuit.
The functional simulation results proved the correct controller
operation, followed by practical tests that validated the circuit.
A plethora of other synchronous and asynchronous modes can be
tested, since the circuit is very flexible in producing a range of
carrier frequencies between 5 KHz to 427 KHz.
The amplitude modulation index, which was set to 1 for this
particular test, can be varied in the full range between 1 and 0.
In terms of silicon usage, the circuit proposed is the optimum
choice. The memory size is the minimum one required to efficiently
183
describe the 0-phase sinewave.
184
The Neural PWM Controller
The RLe Equivalent Circuit of the

Induction Motor
L s L r L2m
L
=
Lr
R
R
=
s
L
e = m R i s + j L i s + L i s = L m R i s + j s
r
r r
er
r r
m s
r r
er
Lr
Lr
u = u
s
i = i s
)]
)
185
186
Simulation
Speed Control Principles

z The
control is achieved in polar coordinates (module and angle).
z The
rotor speed is controlled by compensating the slip frequency.
z Slip
frequency is kept constant for any load torque & any rotor speed.
Basic Control
Algorithm
Improved
Control
Algorithm
slip frequency depends on the angle between e and is,,, controlled

by means of:
* stator frequency
* stator current amplitude
z The current amplitude Is is corrected according to the position of vector e
in the complex plane.
z The
z The
stator frequency fs follows the reference speed profile.
z Very
fast stator frequency changes have to be avoided because they cause

slow transient response.
187
188
Neural PWM Controller

VHDL Design for Implementation
Simulation /Test Results PWM Neural Controller
189
190
Achievements
Test Results - Motor
zInduction motor drives can be controlled using neural algorithms,

implying a smaller number of calculations than vector control.
zThe proposed speed control algorithm can be expressed as a set of
mathematical equations written in polar co-ordinates.
zThe angle and sector calculations are carried out by hardware
implemented neural networks.
zThe entire control scheme has been modelled and designed in VHDL,
synthesised and implemented into Xilinx XC4010 FPGA.
zThe implementation offers a cost-effective solution for industrial
applications without high dynamic requirements.
Controlled versus natural torque characteristic
zTest results have confirmed correct operation of the controller.
Speed control at step torque rise

191
192
2. MODELLING A STAND ALONE DIESEL

DRIVEN GENERATOR SET USING
FUZZY-LOGIC AND PWM CONTROL
STAND-ALONE
RECTIFIER
Project Background
In a given synchronous machine the operational speed is dependent on
the desired output frequency.
PWM INVERTER
Variable speed operation of generators increases design freedom: speed

is not determined by the desired electrical frequency.
GENERATOR
V DC
Synchronous
Generator
Diesel Engine
3 phase
output
It allows engine-generators systems to be operated at speeds which

optimise desired parameters such as noise, vibrations, fuel efficiency,
engine emissions.
FPGA Controller
Fuzzy Control
The research aim is to design and build a control system for a stand
alone variable speed PM synchronous generator.
PWM Control
Fuel Control
This has been developed on the basis of fuzzy logic, using VHDL and
is implemented in Xilinx FPGA.
193
Fuzzy Variable Speed Governor
PWM Inverter Simulation Results

600
300
194
Fuzzy Variable Speed Governor (FVSG) - controller based on fuzzy logic.
Designed using VHDL for easy correction and future integration with other
components to extend the system.
Vdc
System configuration allows variable speed operation of the generator.
Vout
a.c.
output
generator
engine
valve
Inference
Machine
-300
x1
Fuzzy
Defuzzifier
Fuzzy Rule Base
time [ms]
195
inverter
rectifier
Fuzzifier
x2
d
dt
PWM
Control
FVSG
196
DC Voltage Fuzzy Controlled Response to

Load Current Step Increase
Experimental Test Results
ILOAD =20A
1200
1000
800
600
ILOAD =10A
400
350
300
250
200
150
100
50
0
d .c . v o lt a g e [ v o lt ]
1400
d .c . v o lta g e [v o lt]
Voltage (normalised)
200
10 15 20 25 30 35 40 45
350
300
250
200
150
100
50
0
0
10 15 20 25 30 35 40 45
time [sec]
time [sec]
0
1
21
41
61
81 101 121 141 161 181 201 221 241 261 281 301 321 341 361 381
time (sampling units)
Without controller
Reference Voltage
DC Voltage (Normalised to 1000)
Load Current
With controller
Step Change in a.c. Load Current d.c. Voltage response

197
Achievements
198
General Conclusions
A novel modelling technique is proposed for the holistic investigation of
engineering systems. This is based on Hardware Description Languages (VHDL).
PWM controller
voltage control using PWM is a simple and effective strategy for
obtaining and maintaining the desired output voltage parameters.
The sample systems were developed from idea, through modelling / simulation, to
complete systems commissioning, in short time, giving further advantages:
Fuzzy logic
an effective design solution for the speed governor.
able to produce a competent control system without the need for a
precise mathematical model of the plant.
the controller is reconfigurable by changing the rule base.
design can be easily extended to include more parameters.
9easy integration of electronic controllers in complex engineering system models.

9 reliable framework for design verification
9high confidence in correct first time operation
9allows rapid FPGA prototyping of electronic controllers
9gives multiple choices for controllers final implementation technology
9high degree of flexibility
A CAD platform independent model & design are developed and therefore valuable
IPs can be produced, in co-relation with the modern principles of design reuse.
VHDL
design, modelling & simulation performed on a single platform
the same design tool can be used for hardware implementation
reusable design modules are produced
new developments of the design can easily be performed
Concurrent engineering basic rules (unique EDA environment and common design
database) are fulfilled.
199
Estimation: HDL based holistic modelling methodologies will be increasingly used

200
in the future and expanded to encompass other areas of engineering systems.
Recent Developments
HandelHandel-C a novel compiler for Hardware-Software co-design from Celoxica.
C/C++ System Model
Handel-C compiler
Assembly code compiler
VHDL hardware description
Microprocessor software code
Rosetta is a language for modelling/describing engineering systems

Presently the focus is on complex electronic systems -> SOC
Being explored for complex mechanical systems
Defines systems by writing and composing models with respect to domains.
Consists of a syntax (a set of legal descriptions) and a semantics (a meaning
associated with each description)
Millenium Machine new EPSRC (UK) funding initiative for holistic modelling
of engineering systems (systems of systems).
201
Perspectives
In the near future, the complexity of the control systems will continue to grow.
The tasks devoted to the control algorithm will no longer be limited to regulation but will have to
manage diagnosis and fault-adaptive on line control.
The research effort on the theory and the applications of dynamic reconfiguration is crucial.
Network-on-a-Chip (NoC)
SoC design that can include digital control and its analog interface (sensors, ADC, power drivers, etc.).
Co-design issue must be addressed, since the borders between software and hardware are rapidly
vanishing. The main problem in this case is to propose automatic rules of partitioning, based on relevant
quantitative indicators.
Another interesting direction of research is based on the following observation: a control algorithm,
when implemented in an FPGA, can have a very short execution time due to the high degree of
parallelism of its architecture. At the same time, the constraints imposed by the power electronic
components imply a sampling period that is much higher than the execution time. The resulting wasted
time could be advantageously employed.
Several examples of relevant FPGA utilizations in this context were presented. They consist of
predictive control, over-sampling strategies, multi-plants control, etc. All these very promising control
203
paradigms must still be improved.
General Conclusions
The simultaneous increase of the control algorithm complexity and the
chip density implies the use an efficient design methodology.
A modeling technique is proposed for the holistic investigation of power
electronic systems. This is based on System Level Modeling Languages
or HDL and allows rapid FPGA prototyping of the control systems.
Three main design rules are presented.
the algorithm refinement,
the modularity,
the systematic search for the best compromise between the control
performances and the architectural constraints (see A3 section).
Full and timely examples are presented to illustrate the benefits of
FPGA implementation when using the proposed design approach.
It is demonstrated that in both cases a low cost FPGA-based controller
can greatly improve the control performance, especially due to the
reduction of execution time, while keeping a high level of flexibility.
202
Bibliography
M.N. Cirstea, A. Dinu, J. Khor, M. McCormick, "Neural and Fuzzy Logic Control
of Drives and Power Systems", Elsevier Science Ltd., 2002.
M.N. Cirstea, A. Dinu, D. Nicula: "A Practical Guide to VHDL Design", Editura
Tehnica, Bucharest, Romania, 2001, ISBN: 9733115398.
A. Dinu: "FPGA Neural Controller for Three Phase Sensorless Induction Motor
Drive Systems", PhD Thesis, De Montfort University, 2000.
J. Khor, "Intelligent Fuzzy Logic Control of Generators", PhD Thesis, De Montfort
University, UK, 1999.
A. Zregh: Holistic Modelling of Stand Alone Generators, MPhil thesis, De
Montfort University, UK, 2003.
B.K Bose: Modern Power Electronics & AC Drives, Prentice Hall, 2002.
M. P. Kazmierkowski, R. Krishnan, F. Blaabjerg, J. D. Irwin (Editors): Control in
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Xilinx home page: http://www.xilinx.com/
Celoxica home page: http://www.celoxica.com/
Rosetta home page: http://www.sldl.org/
204
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Overview

Introduction, Presentation of the Current Trends (30 min, MC, EM)

Refinement of Control Algorithms by Simulation

Coffee break --------------------------------------------------------------------------------------

Prof. Eric Monmasson,

Cergy-Pontoise University, Cergy-Pontoise, France

Dr. Marcian Cirstea,

Anglia Ruskin University, Cambridge, UK

Quasi-Analog Hysteresis Controller

Conclusions and Perspectives (10 min, EM, MC)

Chair: Dr. Marcian Cirstea, Head of Department of Design &

ELECTRONIC SYSTEMS ON CHIP

Special conference sessions organisations subcommittee

Conferences / transactions papers review subcommittee

Coordinator: Prof. Dan Nicula, Transilvania University Brasov,

Prof. Bogdan Dan Willamowski, Past President of the Industrial

Dr. Jeroen Van Den Keybus, Catholic University of Leuven,

Activity Plan 2007

Dr. Yasuhiro Ota, Partner Robot Development Division, Toyota

Website development to support & promote committees work and to

Guest-Editorship of a special issue of the Transactions on Industrial

Organisation of a best paper prize of $500 for this Special Issue

Organisation of special sessions at the forthcoming IEEE IES

Organising ISIE08 in Cambridge

Refereeing of IEEE Transactions and Conference papers.

Contributing to the organisation of other IES conferences by chairing

Printing materials to advertise the committee, as well as its technical

Traditionally, mathematical models were used to functionally evaluate

Traditionally, mathematical models were used to functionally evaluate

Modern Electronic Design Automation (EDA) tools are used to model,

Modern Electronic Design Automation (EDA) tools are used to model,

High performance electronic controllers can also be implemented.

High performance electronic controllers can also be implemented.

Off-the-Shelf Logic - Function pre-set.

PROM, PAL, FPLA - Programmed by fusible links / charge storage.

FPGAs - User programmable Field Programmable Gate-Arrays.

Gate Array Device - Function set at manufacture in the final stage of

Cell Based Device - Function set at manufacture using CAD to speed up

Full Custom Device - Function set at manufacture - every circuit part is

ASICs allow tailoring the design during development stages of an IC.

where D=total development cost, N=no. of chips manufactured,

FPGAs have reached high density rate

High Speed and Accuracy in Information Processing

Two major ASIC technologies: CMOS and BICMOS - millions gates.

Field-Programmable Gate Arrays (FPGAs) are a special class of ASIC's

Reduced Size and Cost

Application Specific Integrated Circuits

; More gates / chip ==> reduces cost but requires CAD.

Many industrial applications

The decrease of the cost

high data dependency

Vector Control Algorithm:

Algorithm Timing constraints

A specific architecture for each control algorithm

How to easily implement a control algorithm on

Generic FPGA Architecture

Generic FPGA Architecture

Up to four PowerPC 405

Head-to-Head Low Cost

1.2v 90nm copper

1.2v 90nm copper

Nios II 32-bit soft processor