Vignan BTech Syllabus PDF

CONTENT
Page No
1
Academic calendar
Pulse & Digital Circuits
Switching Theory & Logic Design
54
Electronic Circuit Analysis
102
Electromagnetic Theory & Transmission Lines
149
Principles Of Electrical Engineering
195
Pulse & Digital Circuits Laboratory
250
Electronic Circuit Analysis Laboratory
252
Electrical Engineering Laboratory
255
ACADEMIC CALENDAR
VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
DEPARTMENT ACADEMIC CALENDAR

B. Tech Academic Year 2013 - 2014 - II - Semester
S.No
Event
Date
th
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
Submission of abstracts of main project by IV years

Faculty orientation program
Commencement of Class work
Spell for UNIT I Instructions
Freshers day
Spell for UNIT II Instructions
Alumni meet
VIGNAN TARANG
Spell for Unit-III Instructions
st
nd
Assignment -1/ Unit test-1 on I & II Units
Submission of results & week students list to Dept
Spell for Unit-IV Instructions
University I-Mid-Exam- II & IV Year
rd
University I-Mid-Exam- III Year
Spell for UNIT V Instructions for II &IV years
rd
Spell for UNIT V Instructions for III year
LAB INTERNAL-1
Commencement of Special classes for Slow learners
Spell for UNIT VI Instructions for II &IV years
rd
Spell for UNIT VI Instructions for III year
16-12-13
28-11-13 to 05-12-13
09-12-13
09-12-13 to 21-12-13
14-12-13
23-12-13 to 04-01-14
29-12-13
02-01-14 to 04-01-14
06-01-14 to 25-01-14
06-01-14 to 10-01-14
20-01-14
27-01-14 to 07-02-14
10-02-14 to 12-02-14
13-02-14 to 15-02-14
13-02-14 to 25-02-14
17-02-14 to 27-02-14
17-02-14 to 22-02-14
24-02-14
26-02-14 to 10-03-14
01-03-14 to 12-03-14
21.
22.
23.
24.
Submission of Mini project title along with guide for III year
04-03-13
Spell for Unit VII Instructions for II &IV years
11-03-14 to 24-03-14
Spell for UNIT VII Instructions for III year
13-03-14 to 27-03-14
Assignment-II / Unit test on Vth & VIth Units
17-03-14 to 21-03-14
25. Submission of results & week students list to Dept

26. Spell for Unit- VIII Instructions for II & IV year
19-03-14 to 22-03-14
25-03-14 to 05-04-14
27. Spell for Unit- VIII Instructions for III year
28-03-14 to 09-04-14
28. Thanks giving party
01-04-14
29. Farewell to final years from staff and pre final years and student memoir
distribution
30. LAB INTERNAL-2
31. University II-Mid-Exam- II & IV Year
03-04-14
32. University II-Mid-Exam- III Year
10-4-14 to 12-4-14
33. Practical Examinations for II Year
10-04-14to 14-04-14
34. Final Project demo and draft copy submission
28-03-14
35. Practical Examinations for III Year
15-04-14 to 17-04-14
36. EXTERNAL PROJECT VIVA (IV years)
15-04-14
37. End Semester Examination
21-04-14 to 03-05-14
38. Commencement of next semester
16-06-14
rd
24-03-14 to 29-03-14
07-4-14 to 09-4-14
Note: class review meeting for II and III year students and faculty on every Thursday at 1:00 pm onwards
Cc: principal
All staff members
HOD,ECE
PULSE &DIGITAL
CIRCUITS
MS. VijayALAXMI
Associate. Professor
&
Mrs.P.Padmaja
Assistant Professor
COURSEFILE
Department of
ELECTRONICS AND COMMUNICATION ENGINEERING

VIGNAN HILLS, DESHMUKHI VILLAGE, POCHAMPALLY (MANDAL)
NALGONDA (DISTRICT) - 508284
Sponsored by
Lavu Educational Society
(Approved by AICTE and Affiliated to JNT University, Hyderabad)
COURSE
OBJECTIVE
Pulse and Digital Circuits
Course Objective
COURSE OBJECTIVE
1. To understand the concepts of wave shaping and to design various circuits for any application.
2. Understand the principles of digital electronics and abstractions on which the design of digital
systems is based. These include TTL and CMOS digital systems.
3. Use these engineering abstractions to analyze and design simple digital circuits.
4. Build digital logic gates and take measurements of such parameters as propagation delay, noise
margins, fan-out. Compare the measurements with the behavior predicted by mathematic models
and explain the discrepancies.
5. Understand the relationship between the mathematical representation of circuit behavior and
corresponding real-life effects.
6. Obtain V-I characteristics of TTL and CMOS inverters and determine their noise margins.
7. Understand the operation of various memory units.
8. Implement multivibrators/timing circuits of specified duty cycles.
9. Understand the principle and operation of BiCMOS and GaAs circuits.
10. Learn VLSI fabrication techniques.
11. Appreciate the practical significance of the systems developed in the course.
12. Understand the, transistor switch, and logic families of TTL and CMOS.
13. Understand how to use and implement ADC and DAC, and how to design the timing circuits.
14. To provide the student with an understanding of the transistor level design of the most
commonly used BJT and MOSFET logic families. Emphasis is placed on design and analysis of
the logic gate hardware rather than logic design via inter-connection of standard gates. Dynamic
response of the logic gates and other specialized pulse and switching circuits is a key topic
including transmission line effects for high frequency circuits.
Vignan Institute of Technology & Science
II Year B.Tech. 2nd Semester

Page 5
Syllabus
Syllabus
SYLLABUS
UNIT I:LINEAR WAVESHAPING:
High pass, low pass RC circuits, their response for sinusoidal, step, pulse, square and ramp
inputs. RC network as differentiator and integrator, attenuators, its applications in CRO probe, RL
and RLC circuits and their response for step input, Ringing circuit
UNIT II: NON-LINEAR WAVE SHAPING :
Diode clippers, Transistor clippers, clipping at two independent levels, Transfer characteristics of
clippers, Emitter coupled clipper, Comparators, applications of voltage comparators, clamping
operation, clamping circuits using diode with different inputs, Clamping circuit theorem, practical
clamping circuits, effect of diode characteristics on clamping voltage, Transfer characteristics
of clampers.
UNIT III: SWITCHING CHARACTERISTICS OF DEVICES:
Diode as a switch, piecewise linear diode characteristics, Transistor as a switch, Break down voltage
consideration of transistor, saturation parameters of Transistor and their variation with temperature,
Design of transistor switch, transistor-switching times.
UNIT IV: MULTIVIBRATORS :
Analysis and Design of Bistable, Monostable, Astable Multivibrators and Schmitt trigger using
transistors
UNIT V: TIME BASE GENERATORS :
General features of a time base signal, methods of generating time base waveform, Miller and
Bootstrap
time
base generators
basic
principles, Transistor
miller time base generator,
Transistor Bootstrap time base generator, Current time base generators.

UNIT VI: SYNCHRONIZATION AND FREQUENCY DIVISION :
Principles of Synchronization, Frequency division in sweep circuit, Astable relaxation circuits, Monostable
relaxation circuits, Synchronization of a sweep circuit with symmetrical signals, Sine wave frequency
division with a sweep circuit.
UNIT- VII: SAMPLING GATES:
Basic operating principles of sampling gates, Unidirectional and Bi-directional sampling gates,
Reduction of pedestal in gate circuits, Applications of sampling gates.
UNIT-VIII: REALIZATION OF LOGIC GATES USING DIODES & TRANSISTORS:

AND, OR gates using Diodes, Resistor, Transistor Logic, Diode Transistor Logic.

Page 7
Syllabus
TEXT BOOKS
1. Pulse, Digital and Switching Waveforms - J. Millman and H. Taub, McGraw-Hill, 1991.
2. Solid State Pulse circuits - David A. Bell, PHI, 4th Edn., 2002 .
REFERENCE BOOKS
1. Pulse and Digital Circuits A. Anand Kumar, PHI, 2005.
2. Wave Generation and Shaping - L. Strauss.
3. Pulse, Digital Circuits and Computer Fundamentals - R.Venkataraman.
WEBSITES
1.
2.
3.
4.
http://www.onsemi.com/
http://www.kpsec.freeuk.com/symbol.htm
http://buildinggadgets.com/index_circuitlinks.htm
http://www.guidecircuit.com/
JOURNALS
1.
2.
3.
4.
5.
IEEE Transaction on Electronic Devices (ISSN: 0018-9383)

Journal of Active and Passive Electronic Devices (ISSN: 1555-0281)
International Journal of Micro and Nano Electronics, Circuits and Systems (ISSN: 0975-4768)
Active and Passive Electronic Components (ISSN: 0882-7516)
Journal of Electronic Testing (ISSN: 0923-8174)

Page 8
STUDENT'S
SEMINAR
TOPICS
Seminar Topics
STUDENTS SEMINAR TOPICS

1. High pass filter response for square-wave input
2. Ringing circuits
3. Zener slicer working
4. Diode Switching times
5. Triggering methods of bistable multivibrator
6. UJT relaxation oscillator
7. Principles of Synchronization
8. Working principle and VI characteristics of UJT
9. Miller time base generators basic principles
10. Bootstrap time base generators basic principles

Page 10
LECTURE PLAN
Lecture Plan
LECTURE PLAN
NAME OF THE TOPIC
Proposed Date
S.No
No of
Periods
Method of Teaching
Actual Date of Completion
Remarks
UNIT I:LINEAR WAVESHAPING

1.
Introduction
---
2.
Introduction to PDC
3.
LINEAR WAVESHAPING: Introduction
Black board and Chalk
4.
Different types of inputs
Black board, Chalk and LCD Projector
5.
Response of high pass and low pass circuits for: Sine input
6.
Step and Pulse input
7.
Square input
8.
Ramp input
9.
Attenuators
10.
Applications of attenuators in CRO probe
11.
Response of RL circuits for step input
12.
Response of RLC circuit for step input
13.
Ringing circuits
---
UNIT II: NON-LINEAR WAVE SHAPING

14.
NON LINEAR WAVE SHAPING: Introduction
15.
Diode clippers
16.
Clipping circuits
II B.Tech 1st Semester

Page 12
Lecture Plan
17.
Transistor clipper
18.
Analysis of waveforms
19.
Clipping at two independent levels
20.
Transfer characteristics of clippers
21.
Emitter coupled clipper
22.
Comparators
23.
Applications of voltage comparators
24.
Clamping operation
25.
Clamping circuits using diode with different inputs
26.
Practical clamping circuits
27.
Effect of diode characteristics on clamping voltage
UNIT III: SWITCHING CHARACTERISTICS OF DEVICES

28.
Diode as a switch, piecewise linear diode characteristics
Black board, Chalk and LCD projector
29.
Transistor as a switch
30.
Breakdown voltage consideration of transistor
31.
Saturation parameter of transistor and their variation with temperature
32.
Design of transistor switch
33.
Transistor switching times
UNIT IV: MULTIVIBRATORS

34.
Multivibrators
35.
Analysis of Bistable multivibrators.
II B.Tech2 ndSemester
Page 13
Lecture Plan
36.
Design of Bistable Multivibrators
37.
Analysis monostable Multivibrators
38.
Design monostable Multivibrators
39.
Analysis astable Multivibrators
40.
Design astable Multivibrators
41.
Schmitt trigger using transistors
UNIT V: TIME BASE GENERATORS

42.
General features of a time base signal
43.
Methods of generation of time base waveform
44.
Miller time base generator.
45.
Bootstrap time base generator
46.
Transistor miller time base generator
47.
Transistor bootstrap time base generator
48.
Current time base generator
UNIT VI: SYNCHRONIZATION AND FREQUENCY DIVISION

49.
Principles of Synchronization, frequency division
50.
Frequency division in sweep circuit
51.
Synchronization in astable relaxation circuits
52.
Synchronization in monostable relaxation
53.
Frequency division in monostable relaxation circuits
54.
Frequency division in astable relaxation circuits
Page 14
Lecture Plan
55.
Synchronization of a sweep circuit with symmetrical signals
56.
Sine wave frequency division with a sweep circuit
UNIT- VII: SAMPLING GATES

57.
Basic operation principles of sampling gates
58.
Unidirectional sampling gates
59.
Bi- directional sampling gates using diode
60.
Reduction of pedestal in gate circuits
61.
Bi- directional sampling gates using transistor
62.
Four diode and six diode sampling gate
63.
Application of sampling gates.
UNIT-VIII: REALIZATION OF LOGIC GATES USING DIODES & TRANSISTORS

64.
Introduction to logic gates
65.
OR, AND & NOT gate using diodes and transistors.
66.
Transistor logic
67.
Diode transistor logic
68.
Totempole nand gate
69.
Comparision of all logical families, Problems
70.
Revision on I and II Units
71.
Revision on III and IV Units
72.
Revision on V and VI Units
73.
Revision on VII and VIII Units
Black board, Chalk and

LCD Projector
LCD Projector
Page 15
LEARNING
OBJECTIVES
Learning Objective
LEARNING OBJECTIVES
UNIT I: LINEAR WAVE SHAPING

At the conclusion of this unit student will
1. Define linear wave shaping.
2. Explain low pass RC circuit
3. Explain high pass RC circuit.
4. Explain different types of inputs signals.
5. Explain RC network as differentiator.
6. Explain RC network as integrator.
7. Define attenuators.
8. Explain RL and RLC circuits.
9. Define ringing circuit.
UNIT II: NON LINEAR WAVE SHAPING

1. Explain diode clippers.
2. Explain clipping at two independent levels using diode.
3. Explain positive clipper.
4. Explain negative clipper.
5. Explain single ended clipping circuits.
6. Explain transistors clippers.
7. Define comparator.
8. Explain voltage comparator circuits.
9. Define clamping.
10. Explain clamping circuit theorem
11. Explain positive clamping.
12. Explain negative clamping.
13. Explain transfer characteristics of clamper.
14. Explain the function of rectifier
UNIT III: SWITHING CHARACTERISTICS OF DEVICES

1. Name the devices that can be used as switches.
2.Explain how a diode acts as a switch.
3.Define forward recovery time.
II B.Tech2 nd Semester
Page 17
Learning Objective
4.Define reverse recovery time.

5.Define storage time of a diode.
6.Define transition time of a diode.
7.Explain avalanche break down.
8.Explain zener break down.
9.Justify the transistor acts as a switchList out the applications of BJT
10.Explain the three region of operation of a transistor.
11.When does the transistor acts as a closed switch and an open switch.
12.Define rise time.
13.Define storage time.
14.Define fall time.
15.Explain diode switching time.
16.Explain transistor switching time.
UNIT IV: MULTIVIBRATORS

1.Define multivibrator.
2.Discuss the types of multivibrator.
3.Define dc coupling.
4.Discuss the application of bistable multivibrator.
5.Explain the stable state of a binary.
6.Define loop gain.
7.Explain collector catching diodes.
8.Write a short note communicating capacitor.
9.Define resolving time.
10.Define settling time.
11.Define resolution time.
12.Define transition time.
13.Define triggering.
14.Explain symmetrical triggering.
15.Explain unsymmetrical triggering.
16.Explain Schmitt trigger.
17.Define the term upper triggering point.
18.Define the term lower triggering point.
19.Define ac coupling.
20.Define quasi stable state.
21.Explain monosatable multivibrator.
Page 18
Learning Objective
22.Explain astable multivibrator.
Unit V: TIME BASE GENERATORS

1.Why time circuits are called sweep circuits.
2.List the application of time base generators.
3.Define sweep time.
4.Define restoration time.
5.Define slope error.
6.Define displacement error.
7.Define transmission error.
8.Drive the relation between different types of errors.
9.Explain the methods of generating a time base waveform.
10.Explain the principle of miller ad boot strap time base generators.
11.Explain the working of transistor current time base generators.

1.Explain the principles of synchronization.
2.Explain synchronization on one to one basis.
3.Explain synchronization with frequency division.
4.Explain relaxation circuit. Give some example of it.
5.Name some negative resistance used in relaxation oscillators.
6.Explain synchronization of sweep generator with pulse signals.
7.Explain how the synch signal affects the frequency of operation of the sweep generator.
8.Explain frequency division with respect to a sweep circuit.
9.Explain frequency division by an astable blocking oscillator.
10.Explain frequency division by an astable mutlivibrator.
11.Explain synchronization of a sweep circuit with symmetrical signals.
12.Compare sine wave synchronization with pulse synchronization.
UNIT- VII: SAMPLING GATES

1.Explain sampling gates.
Page 19
Learning Objective
2.Why sampling gates are called as linear gates.

3.Differentiate sampling gate and logic gates.
4.Explain unidirectional sampling gate.
5.Explain bidirectional sampling gate.
6.Define gate signal.
7.Define pedestal.
8.Explain the working of bidirectional gates using transistor.
9.Explain the working of four diode gate.
10.Explain the working of six diode gate.
UNIT-VIII: LOGIC GATES

1.Draw the OR logic using diodes.
2.Draw the AND logic using diodes.
3.Draw the NOT logic using transistor.
4.Explain the transistor logic.
5.Explain diode transistor logic.
Page 20
OBJECTIVE
TYPE
QUESTIONS
Pulse and digital circuits
Objectives Questions
OBJECTIVE TYPE QUESTIONS

UNIT I: LINEAR WAVE SHAPING
1. The response of a high pass RC circuit to a step input of amplitude V is
a) V(1-e-t/RC )
b) Ve-t/RC ) c) V d)None
2. The response of a differentiator circuit to a pulse input is

a) ramp
b) spikes c) square d) none
3. A High pass RC circuit acts like a differentiator for the condition

( RC = Time constant of the circuit & T= Time period of the input signal ) [
a) RC = T
b)RC>>T c) RC<<T d) None
4. The response of a low-pass RC circuit to a step input is

a) ramp b) square wave c)exponential rise d) exponential decay
5. A low pass RC circuit acts like an integrator for the condition

( RC = Time constant of the circuit & T= Time period of the input signal )
6. The response of an integrator circuit to a square wave input is

a) sine wave b) triangular wave c) pulse d) ramp
7. The condition for perfect compensation in an attenuator is

a) R1 = R2
b) C1=R2C2/ R1 c) C1= C2 d) None
a) RC = T b) RC << T c) RC >>T d) None
8. The circuit which passes low frequencies readily , but attenuates high frequency is
called
[
]
a) High pass RC circuit b) Low pass RC circuit c) Both a & b d)None
9. In a high Pass RC circuit, the output (Vo) is taken across
a) Resistor b)capacitor c) inductor d) none
10. The condition for a RLC circuit to ring for many cycles is ( k is damping constant)
a) k > 1 b) k < 1 c) k = 1 d) None
[
]
11. The response of a RLC circuit to a step input for damping constant k = 1,
corresponds to
[
a)over damping b) critical damping c) under damping d) none
12. The response of a series RL circuit to a pulse input for smaller time constant is
a) ramp b) exponential c)spikes d) None
[
13. Attenuator is used to
[
a)Reduce the amplitude of a signal b) increase the amplitude of a signal
c) change the frequency of the signal d) none
]
]
Page 22
14) The time constant of a series RL circuit is

a) LR b) L/R c) R/L d) None
15 The expression for transmission error (et), when ramp input is applied to a High pass
RC circuit for the condition RC >> T is
[
]
a) T/RC
b)T/4RC c) T / 8RC d) T / 2RC
16. The expression for transmission error (et ), when ramp input is applied to a Low pass
RC circuit for the condition RC << T is
[
]
a) 2RC / T
b) 4RC / T
c) RC / T d) None
ANSWERS:
1 (b)
9 (a)
2 (b)
10 (b)
3 (c)
11 (b)
4 (a)
12(c)
5 (c)
13 (a)
6 (b)
14 (c)
7 (b)
15 (d)
8 (b)
16 (b)

1. The circuit which converts sinusoidal wave form into square under some special condition is [
a) Dc restorer b) Double ended clamper
c) Attenuator
d) Clamper
2. zener diode has ---------- temperature coefficient

a) some times positive and sometimes negative
b) Only NEGITIVE
c) Both positive and negative
d) Only positive
3. the semiconductor diode current equation is given by

a) I=(1-eV/Vt )
b) I=Io (e1/Vt -1)
c) I=Io (eV/Vt -1)
d) I=Io (1-e1/Vt )
4. a comparator is a basic building block in a system used to analyze the -------- distribution of noise
generated in active device
a) Both frequency and phase
b) Amplitude
c) Phase
d) Frequency
5.The breakdown occurring due to direct rupture of bonds because of existence of strong electric field is
a)avalanche breakdown
d)none[
6.The circuit which converts sinusoidal wave form into square under some special condition is [
a) Dc restorer
b) Zener breakdown
c) Forward breakdown
b) Double ended clamper
c) Attenuator
d)none
7.Under steady state the output is given by, when the circuit and input are as shown in the figure[
a) Vo = Vi .Vm
b) Vo = Vi + Vm
c) Vo = Vi - Vm
8.the application of voltage comparartor

a)
ohm meter b)
voltmeter c)ammeter d)
b)R+L
c) RL
10the disadvantage of shunt clipper

d) Vo = Vi / Vm
[
phasemeter
9.time constant or RLciruit

a) R/L
d) L/R
Page 23
a) Round shaped edges of input waveform
b) No transmission of signal
c) Transmits same signal
d) Doubles amplitude of input waveform
11.the negative clamper is also called
a) Positive peak clamper b) Negative peak clamper c) Positive peak clipper d) Negative peak
clipper
ANSWERS:
1 (d)
2 (b)
3 (c)
4 (b)
5 (b)
6 (d)
7 (c)
8 (d)
9 (d)
10 (a)
11 (a)

1.if the transistor is indeed in saturation ,the following condition must be satisfied
2.The reverse saturation current increases approximately for every ------- rise in temperature [
a) ic=iB/hfe(min) b) iB>iC/hfe(min)
a) 30 c
C)
iB=iC+Vce d) iB=iC
b) 50 c
c) 70 c
d) 10 c
3. Turn off time of the transistor is =-------
4T The reverse saturation current increases approximately for every ------- rise in temperature [
a) toff =tf +ts

a) 30 c
b) toff =tf +ton

b) 50 c
c) toff =tfd +ts

c) 70 c
d) toff =ton +t.s
d) 10 c
5) The Vce of the n-p-n transistor is

a)-0.1v
b)0.1v
c) 0.7 v
d)0 v
6.the capacitance which appears across a reverse biased function of a diode is called
a) Diffusion capacitance b) Fixed capacitance c) Transition capacitance d) Valuable capacitance

7. common base configurations is little used because
a) High voltage gain b) High current gain c) It has low input impedance d) High input impedance
8. the Vce (sat) of Si n-p-n transistor at 27 c is
a) 0.7 v b) 0.3 v c) 0.8 v d) 0.1 v

9. smallest times between two successive triggers is ----------a) Restoring time b) Storage time c) Delay time
d) Rise time
10.zener diode has ---------- temperature coefficient

a) some times positive and sometimes negative b) Only NEGITIVE
c) Both positive and negative
d) Only positive
11) Turn off time of the transistor is =------a) toff =tf +ts
b) toff =tf +ton
c) toff =tfd +ts
d) toff =ton +ts
12.when does the transistor act as a closed switch

a) both junctions are forward biased
b) input junction is reverse biased and output junction is forward biased
Page 24
c) input junction is forward biased and output junction is reverse biased

d) both junctions are reverse biased
13.when does the transistor act as open swit
a) input junction is reverse biased and output junction is forward biased

b) both junctions are forward biased
c) both junctions are reverse biased
d) input junction is forward biased and output junction is reverse biased

14.transiton capacitance of diode is given as
n/(VB)3
a)
b) /(VB)n
c) n/VB d) (VB)n /
15.the base width in a junction transistor is deliberately chosen small so that
a) the concentration of injected carrier is small b) the majority carriers easily reachs the collector
c) the electric field s large d) to reduce the recombination of injected minority carriers
16.which of the following is the fastest switching device
a) MOSFET
b) DIODE
c) JFET
b) minority carriers c)concentration of majority carriers d) none of the above
18.for an ideal p-n junction diode the current I=Io (eV/Vt -1) than what is the value for Ge
a)5
d)BJT
17.in a transistor leakage current mainly depends on

a) temperature
b) 15
c) 1
d) 10
19. at constant base and collector current forward B-E voltage has typical temperature sensitivity in the
range of
a) -7.5 m V /c to -8.0 m V /c b) -1.5 V /c to -2. m V /c c) 1.5m V /c to -2 m V /c d) -7.5 m V /c to 8.0

m V /c
20the maximum reverse biasing voltage which may be applied before breakdown between collector
and base terminals is
a) BVCEO
[
b) VCE
c) VCB
d) BVCBO
21.a large signal approximation which often leads to a sufficient accurate solution is the -----------representation
a) Ebers model
[
b) Hybrid model
c) Pi model
d) Piecewise linear
22.in the diode the time required for minority charge carriers to move into the other side of the PN
junction and become majority charge carrier is called
a) Delay time
b) Transition time
c) Reverse recovery time
d) Storage time
23. the collector to emitter breakdown voltage with base not open ckt is BVCER is given by [
BVCBOn (1-ICORB/V) b) BVCEO (1-ICORB/V) c) BVCBO (1-ICORB/V) d) BVCEOn (1-ICORB/V)

24. if the VCB of n-p-n transistor in CE configuration is negative when the transistor is in
a) Active region
b) Cut off region
c) Saturation region
d) Inverted
ANSWERS:
Page 25
1 (b)
9 (a)
2 (d)
10 (b)
3 (d)
11 (a)
4 (a)
12 (a)
5 (b)
13 (c)
6 (c)
14 (b)
7 (c)
15(d)
8 (b)
16(d)
17 (a)
18 (c)
19 (b)
20 (d)
21 (d)
22(d)
23(a)
24(c)
UNIT IV:MULTIVIBRATORS
1.in a design of fixed bias binary VCC =VBB =12v ,hfe(min)=20, ic sat=4 mA,assume n-p-n(Si) transistor
then Rc is =
a) 2.925 k b) 200 c) 0.5 k d) 100

2) The duration of quasi stable state of a mono shot is-----
a) Fall gate b) Gate time c) Storage time d) Recovery time

3. the capacitor which assists the binary in making abrupt transition between states are called [
a)delay b) Storage c) commutating d) translation

4. monostable vibrators generates
a) Pulse wave form b) Ramp signal c) Sine wave d) Square wave

5. -------- Are basically regenerative circuits comprising of two cross coupled active devices [ ]
a)filters b) Multivibrators c) Attenuators d) Clampers
6.Which one of the following circuits converts any arbitrary waveform into a square wave
a. Monostable Multivibrator
b. Bistable Multivibrator
c. Astable Multivibrator
d. Schmitt Trigger
7.The Schmitt Trigger is also called as
a. emitter coupled binary
b. collector coupled binary
c. any of the two
d. none
8.The Astable Multivibrator has one of the following applications

a. voltage to frequency converter
b. gating circuit
c. comparator
d. none
9. The Monostable Multivibrator has one of the following applications

a. Schmitt trigger b. gating circuit
c. square wave generator
d. none
11. The time period of the quasi stable state in a Monostable Multivibrator is given by
a. T=0.69RC
b. T=0.63RC
c. T=1.38RC
d.T=RC
12.the pulse width or gate width of monoshot is

a) RC
b) 2 RC
c) 0.69 RC d)none
13. if VTP=5.12 and LTP =3.312 then the value of hysterisis in schimmit trigger is
a) 1.81 V
b) 5.4 V
c) 4.8 V
d) 3.2V
14.the commutating capacitor are also called

a) speed up capacitor b) varicap c) tuning capacitor d) delay capacitor
Page 26
15. a stable state of binary is one in which the current and voltages satisfy kirrchofs laws and are
constant and the condition satisfied that loop gain is
a) =1
b) <1
c) >>1
d) >1
16. the schmit trigger can be used as a

a) filter
b) attenuator
c) comparator
d) clamper
17. a ckt which can indefinitely exist in either of two stable state and which can be induced to make
abrupt transition from one state to other by means of external excitation
a) monoshot
b) oscillator
c) binary
d) attenuator
18. which of the following is the advantage of emitter coupled over collector coupled multivibrator
a) inherently self starting b) low power dissipation c) less noisy d) only one trigger signal is enough
19.no of triggers required for monostable multi to change from stable state to quasi stable state and vice
versa
21. find the value of collector resistor in a collector coupled stable multi for the following [
a) 1 b) 2 c) 3 d) 4
20. monostable multi vibrators generates
a) Square
b) Pulse
c) Sine
d) Ramp
specifications f=10 KHZ ,Vcc=9 V, ic(max) =2 mA,hfe=20

a) 1
b) 4.35 K
c) 3 K
d) 2K
22.the binary is sometimes referred to as

a) Nortons ckt
b) Eccless Jordon ckt
c) Thevinins ckt
d) Millimans ckt
ANSWERS:
1 (a)
12 (c)
2 (b)
13 (a)
3 (c)
14 (a)
4 (b)
15 (b)
5 (b)
16 (c)
6 (d)
17 (c)
7 (a)
18 (c)
8 (a)
19 (a)
9 (b)
20 (b)
10 (a)
21 (b)
11 (a)
22(b)

1. The input impedance of bootstrap integrator Is
(a) low (b) high (c) moderate (d) Too high

2. A set of coil is called as
(a) magnetic coil (b) LOT (c) yoke (d) sweep coil
3. Sweep speed error is defined as
(a) initial ramp speed/final ramp speed (b) initial ramp speed-final ramp speed/ initial ramp speed
(c) initial ramp speed +final ramp speed/initial ramp speed (d) final ramp speed/ initial ramp speed
4. Waveform can have either positive slope or negative slope
(a) Ramp (b) square (c) Trapizoidal (d) Rectangular

Page 27
5. The variations in phase delay occur due to variations in factors like and
(a) Q point only (b) current gain & voltage gain (c) Q-point, supply voltage and gain
(d) loop gain, suply voltage and transistor parametres
6. The phenomenon of charging and discharging of a capacitor in a pulse digital circuit is called as
(a) Relaxation circuit (b) Timing circuit (c) Stable circuit (d) unstable circuit
7. The duration during which the voltage level decreases to the initial level is Known as
(a) Trace (b) Retrace interval (c) sweep interval (d) Signal reconstruction
8. Difference between the input and output divided by the input is called as
(a) transistor error (b) et (c) translational error (d) translational & transmission error
9. Current time base generators are used in
(a) In Radar screen scanning (b) Tv scanning

(c) Sonar application
(d) where large raster area is to be scanned
10. In integrator neither terminals of the capacitor are connedcted to ground

(a) Emitter follower (b) Source follower (c) Bootstrap (d) Miller Integrator
11. The three different stages of ramp waveforms are
(a) Recycling ,Non-return to zero (b) Rise or fall, recycling arrangement, return to original;
(c) Rise or fall, recycling
(d) Recycling only
12. Slope error is given by

(a) final slope/initial slope
(b) initial slope+final slope/final slope
(c) initial slope-final slope/initial slope (d) Initial slope/final slope

13. The biggest disadvantage of Bootstrap using Darlington circuit is
(a) gain greater than unity (b) gain of the composite amplifier is smaller than each stage
(c) gain less than unity
(d) gain of comosite amplifier is too large
14. Millers sweep circuit produces type of waveform
(a) negative going ramp (b) Sinusodalwave (c) positive going ramp (d) squarewave
15. Millers Integrator generates a ramp voltage
(a) sinusoidal (b) non-linear (c) linear (d) Cosinusoidal

16. The error arising due to transmission through a linear network is known as .transmisssion error
(a) Transmission error (b) True (c) Sweep error (d) False
17. Current time base generators are used in
(a) In Radar screen scanning (b) Tv scanning

(c) Sonar application
(d) where large raster area is to be scanned
18. For a basic Bootstrap integrator the transistor is connected as
(a) common base (b) common emitter (c) Common collector configuration (d) emitter follower
19. The maximum deviation in rate of change of sweep voltage with time is called differential linearity
Page 28
(a) False (b) Sweep voltage (c) Sweep error (d) True
20. The Sweep speed error in a current time base generator is given by
(a) IL[RL + Rcesat]/Vcc (b) (VCC/RL)IL (c) (RL/VCC) (d) [RL + RCE]/Vcc
ANSWERS:
l (b)
11 (b)
2 (c)
12 (c)
3 (b)
13 (b)
4 (a)
14 (a)
5 (d)
15 (c)
6 (a)
16 (c)
7 (b)
17 (b)
8 (b)
18 (b)
9 (b)
19 (a)
10 (d)
20 (a)

1. If synchronisation is achieved with different frequencies , ie., one Frequency being twice the other
then it is termed as
(a) No synchronization occurs (b) frequency matching

(c) synchronization
(d) synchronisation with frequency division
2. The variations in phase delay are called as

(a) Sampling gates (b) phase jitters (c) phase shifters (d) Blocking jitters
3. When two generators with equal frequencies run in synchronism the Synchronisation is said to be on
(a) one-to many (b) multiplexing (c) one-to-one basis (d) many to one
4. When two generators produce waveforms at different frequencies, it is Essential for proper
synchronization that the frequency of one generator is an of that of the other generator.
(a) odd multiples (b) secondary harmonies (c) even multiples (d) integral multiple
5. If synchronization is achieved with different frequencies , ie., one Frequency being twice the other
(a) frequency matching (b) No synchronization occurs

(c) synchronization
(d) synchronization with frequency division
6. When two generators with equal frequencies run in synchronism the Synchronization is said to be on
(a) many to one (b) one-to-one basis (c) one-to many (d) multiplexing
7. The biggest advantage of Triggered sweep circuit is
(a) slow wave operation (b) Free running operation

(c) Complex operation (d) Fast running operators
(a) No synchronization occurs (b) synchronization (c) frequency matching (d) synchronization
with frequency division
9. A sampling gate is also termed as
Page 29
(a) linear gate (b) time-selection gate (c) time selection & linear gates (d) non-linear gate
10. Synchronization of sweep circuit can be obtained by
(a) Non identical phase signals (b) identical phase signals

(c) Symmetrical signals
(d) unsymmetrical signals
11. Monostable relaxation circuit is used as a

(a) time division
(b) both time and frequency
(c) frequency division (d) only frequency multiplexing

12. By making , a divider circuit with a division factor n can be built
(a) TO < nTp (b) TO > nTp (c) TO = 2nTp (d) TO = nTp
13. Sampling gate for which input voltage is
(a) dc only (b) Sampling of acsignal (c) ac only (d) Either dc or ac
14. When two generators with equal frequencies run in synchronism the Synchronisation is said to be
on a
(a) many to one (b) multiplexing (c) one-to many (d) one-to-one basis
15. stray signals are
(a) Introducing distortion
(b) affects synchronization severely
(c) doesnt affect synchronization
(d) unwanted noisy signals
16. In a Sinusoidal synchronization signal UJT is used as a switch beause
(a) negative resistance voltage controlled device(b) negative resistance current controlled device
(c) voltage divider
(d) Current divider
17. Synchronization of sweep circuit can be obtained by
(a) Non identical phase signals (b) Symmetrical signals

(c) identical phase signals
(d) unsymmetrical signals
18. Monostable relaxation circuit is used as a

(a) both time and frequency
(c) only frequency multiplexing
(b) time division

(d) frequency division
then it is termed n as
(a) frequency matching (b) No synchronization occurs

(c) synchronization
(d) synchronization with frequency division
20. The biggest disadvantage of sampling gate is

(a) fast rise of control voltage (b) the slow rise of control current
(c) the slow rise of control voltage
(d) Risetime fall time
ANSWERS:
Page 30
1(d)
11 (c)
2 (d)
12 (b)
3 (c)
13 (d)
4 (d)
14 (d)
5 (d)
15 (b)
6 (b)
l6 (b)
7 (b)
17 (d)
8 (d)
18 (d)
9 (c)
19 (d)
UNIT- VII :SAMPLING GATES

1. The biggest disadvantage of sampling gate is
10 (c)
20 (c)
(a) the slow rise of control voltage (b) the slow rise of control current
(c) Rise time fall time
(d) fast rise of control voltage
2. The parameters of a Non-ideal switch are

(a) Digital and analog control (b) Digital switch control
(c) Analog & Digital
(d) Analog channel & digital control line control parameters
3. Sampling gate for which input voltage is
(a) ac only (b) Sampling of acsignal (c) dc only (d) Either dc or ac

4. Advantages of Diode sampling gate over the transistor Sampling gate are
(a) Linearity only (b) Non-linearity of operation and elimination of pedestal
(c) Linearity of operation and elimination of pedestal (d) stable operating point achievement
5. Chopper amplifier is also known as
(a) modulator
(b) signal generator
(c) Non-linear wave form generator (d) Waveform generator

6. The interval of time is selected by means of an externally applied signal is Termed as
(a) ramp (b) square wave (c) sync pulse (d) gating signal
7. The time interval for transmission is selected by means of an externally applied signal Called as
(a) Gating signal (b) control signal (c) Logic signal (d) Threshold signal
8. A Sampling gate which can handled the input signal excursion of both polarities is termed as
[
(a) multidirectional gate (b) n-directional gate (c) Bi-directional gate (d) unidirectional gate
9. The parametres of a Non-ideal switch are
(a) Analog channel & digital control line control parameters (b) Analog & Digital
(c) Digital and analog control
(d) Digital switch control
10. Chopper amplifier is also known as
(a) Waveform generator (b) modulator

(c) signal generator
(d) Non-linear wave form generator
11. A is basically a transmission circuit which allows input signal to pass through it during selected
interval and blocks its passage outside this this time interval.
(a) XOR gate (b) Sampling gate (c) OR gate (d) nor gate
Page 31
ANSWERS:
l (a)
2 (d)
3 (d)
4 (c)
5 (a)
6 (d)
7 (a)
8 (c)
9 (a)
10 (b)
11(b)

1. Complementary output is available in which of the following logic families
(a) RTL (b) TTL (c) ECL (d) DTL

2. The noise - margin of ECL family is given by
(a) 200 milli watt (b) 10 milli watt (c) 250 milli watt (d) 110 milli watt
3. The IC74147 which acts like
(a) AND gate (b) adder (c) multiplexer (d) encoder
4. Which of the following logic family is called TRISTATE gate
(a) TTL (b) RTL (c) ECL (d) DTL
5. Differential signals are used in the following logic family
(a) .RTL (b) DTL (c) TTL (d) ECL
6. Two basic technologies for digital ICs are bipolar and MOS Bipolar technology is preferred for
(a) LSI & MSI (b) LSI only (c) LSI, MSI & SSI (d) MSI and SSI
7. Complementary output is available in which of the following logic families

(a) TTL (b) DTL (c) ECL (d) RTL
8. Which of the following flip-flops is used as latch
(a) ECL (b) TTL (c) ISL (d) CMOS
9. An AND gate is a
(a) Multiplexing circuit (b) sequential circuit (c) combinational circuit (d) Memory circuit
10. The programmable logic device (PLD) having a programmable AND-array at the Input
and]programmable OR array at the output is called
(a) programmable gate array(PGA)
(b) programmable array logic (PAL)
(c) programmable logic Array (PLA)
(d) ASIC
11. Two similar RTL gates are wire-ANDed. What will be the fan-out of the Combined gate if each has
fan-out of 5?
(a) five (b) two (c) eight (d) ten

12. The cost of Schottky clamped TTL is
(a) low (b) average (c) very high (d) moderate
13. An IC that is a 4-bit latch is
(a) 7400 (b) 7446 (c) 7410 (d) 7475
14. The ECL can be used to switch frequencies as high as
Page 32
(a) 100MHz (b) 1MHz (c) 1GHz (d) 500MHz

15. Which of the following logic has the fan-out more than 90
(a) TTL (b) 8ns ECL (c) 4nsECL (d) CMOS

16. NOR operation is
(a) X + Y (b) X . Y (c) ( X + Y ) ( X + Y ) (d) XY
17. Power dissipation of logic family is defined as the supply power required for the gate to operate
with duty cycle at a certain specified frequency
(a) 50% (b) 25% (c) 100% (d) 75%

18. Fan-in for a TTL gate is given by
(a) 5 (b) 8 (c) 6 (d) 7

19. A NAND circuit with positive logic will operate as
(a) NOR with negative logic
(b) AND with negative logic
(c) AND with positive logic
(d) OR with negative logic
20. The programmable logic device (PLD) having a programmable AND-array at the Input and
programmable OR array at the output is called
(a) programmable gate array(PGA)
(b) programmable array logic (PAL)
(c) programmable logic Array (PLA) (d) ASIC

21. Name the logic family which can always be Wire-Ored
(a) DTL (b) TTL (c) RTL and DTL (d) IIL
22. The cost of Schottky clamped TTL is (a) very high (b) moderate (c) low (d) average
23. In Boolean algebra , A+A+A+ +A is same as
(a) An (b) nA (c) Zero (d) A
ANSWERS:
1 (c)
9 (c)
17 (a)
2 (c)
10 (c)
18 (b)
3 (d)
11 (d)
19 (a)
4 (a)
12 (b)
20 (c)
5 (c)
13 (d)
21 (c)
6 (a)
14 (d)
22(d)
7 (c)
15 (b )
23(d)
8 (a)
16 (b)
Page 33
ESSAY TYPE
QUESTIONS
Essay Type Questions
ESSAY TYPE QUESTIONS

1 a) A symmetrical square wave whose peak-to-peak amplitude is 2V and whose average value is
zero as applied to on RC integrating circuit. The time constant is equals to half -period of the
square wave. Find the peak to peak value of the output amplitude. Also sketch the output
waveform.
b) Derive the expression for percentage tilt for a square wave output of RC high pass circuit.
2. (a) A pulse of amplitude 5 V and duration 20 sec is applied to High pass RS circuit having
R= 10 k and C = 1000 pf. Calculate the output V0 (t) Sketch the output waveform. Calculate the
tilt and undershoot.
(b) What is meant by an attenuator and explain the application of an attenuator in a CRO probe.
3. a) The output of a high pass RC circuit for a symmetrical square wave input is shown in
figure.1. Derive
the expression for percentage tilt in the output.
Figure.1
b) Explain about RLC Ringing Circuit.
4. a) Explain the response of RC low pass circuit for exponential input signal.
b) Derive the expression for percentage tilt for a square wave output of RC high pass circuit.
5.What is an attenuator? Draw the circuit of compensated attenuator. While sketching the
response of compensated attenuator for perfect compensation, over compensation and under
compensation, show that the condition for perfect compensation is R C = R C .
1 1
2 2
6. a) Draw the series RLC circuit and derive expression for its transfer function.
b) A ramp input, shown in Figure.1 is applied to a high-pass RC circuit. Draw to scale the
output waveform for the following cases:
i) T = 0.2 RC ii) T = 10 RC [7+8]
Figure.1
7.a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is
the period of an input E sin t.
m
Page 35
b) What is the ratio of the rise time of the three sections in cascade to the rise-time of
Single section of low pass RC circuit?
8. a) Explain RC double differentiator circuit.
b) An oscilloscope displays a 5Hz square wave with 6% tilt. The signal input has no tilt and is
coupled to the oscilloscope via a 4.7F capacitor. Calculate the input resistance of
oscilloscope.
c) Draw the basic ringing circuit. Explain how it provides undamped oscillations.
9.a)The output of a high pass RC circuit for a symmetrical square wave input is shown in
Figure.1. Derive the expression for percentage tilt in the output.
Figure.1
b) An oscilloscope displays a 5Hz square wave with 6% tilt. The signal input has no tilt
and is coupled to the oscilloscope via a 4.7F capacitor. Calculate the input resistance of
the oscilloscope.
10.a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is
the period of an input E sin t.
m
b) What is the ratio of the rise time of the three sections in cascade to the rise-time of
Single section of low pass RC circuit?
1.a) Draw the diode differentiator comparator circuit and explain its operation when a ramp input
signal is applied.
b) For a shunt diode clipper circuit V = 20 sin t, V = 10V is obtained from a potential divider
i
circuit using 100V supply and 10K potentiometer

i) Draw the circuit diagram.
ii) If R = 50, R = and V = 0, sketch the transfer characteristic, output waveform for the given
f
2.a) A square wave input as shown in figure.2 is applied to a negative clamper circuit. Sketch the
steady-state output waveform and derive the necessary expressions.
Page 36
Figure.2
b) Explain negative peak clipper with and without reference voltage.
3.a) Draw the basic circuit diagram of a DC restorer circuit and explain its operation.
b) For the circuit shown in Figure.1, a sine wave input of 100V peak is applied. Sketch the
output voltage V to the same time scale & transfer characteristic. Assume ideal diodes.
O
Figure.1
4.a) State and prove clamping circuit theorem.
b) Determine Vo for the network shown in Figure.1 for the given 16V P-P sine wave input. Also
sketch the transfer characteristics. (Assume ideal diodes).
Figure.1
5. a) A square wave input of period T=1000 sec, Vpeak = 10V and Duty cycle = 0.2 is applied
to the circuit shown in figure.1. Given, R = 100, C = 1F, R = 10K & Diode forward
S
resistance, R = 100.
f
i. Sketch the output waveform with voltage levels at steady state.

ii. Forward and reverse direction tilt
iii. A / A
f
Figure.1
b) Write a short note on voltage comparators.
6. a) Draw the basic circuit diagram of negative peak clamper and explain its operation.
b) For the circuit shown in figure.2, an input voltage V linearly varies from 0 to 150V is applied.
i
Sketch the output voltage V and transfer characteristics. Assume ideal diodes.
O
Page 37
Figure.2
7.a) State and prove clamping circuit theorem
b) In the diode circuit shown in figure.1b, the diode has R = 100, R = 10K, V=0. Sketch the
f
steady state output voltage indicating all voltages and time constants, for the given square
wave input with T1 = 2sec and T2 = 1sec, shown in figure.1a.
Figure.1a
Figure.1b
a) Input signal
b) Diode circuit
8. a) Explain negative peak clipper with and without reference voltage.
b) Draw the circuit diagram of an Emitter-Coupled clipping circuit. Explain its operation with its
transfer characteristic and necessary expressions.
9. a) Draw the diode differentiator comparator circuit and explain its operation when a ramp
input signal is applied.
b) For a shunt diode clipper circuit V = 20 sin t, V = 10V is obtained from a potential divider
i
circuit using 100V supply and 10K potentiometer

i) Draw the circuit diagram.
ii) If R = 50, R = and V = 0, sketch the transfer characteristic, output waveform for the given
f
V.
i
10.
a) A square wave input of period T=1000 sec, Vpeak = 10V and Duty cycle = 0.2 is applied to
the circuit shown in figure.1. Given, R = 100, C = 1F, R = 10K & Diode forward
S
resistance, R = 100.
f
i. Sketch the output waveform with voltage levels at steady state.

ii. Forward and reverse direction tilt
iii. A / A
f
Page 38
Figure.1
b) Write a short note on voltage comparators.
1. a) Write about diode switching times.
b) Explain Zener & Avalanche breakdown mechanisms in diodes.
2. a) Explain the terms pertaining to transistor switching characteristics.
i. Rise time. ii. Delay time. iii. Turn-ON time.
iv. Storage time. v. Fall time. vi. Turn-OFF time.
b) Calculate the maximum operating frequency of a diode with storage time of 1ns and transition
time of 8ns.
3.a) The circuit shown in figure. 2 uses a silicon transistor with h = 100 and V = 0.7V. Find
FE
BE
the value of R which saturates the transistor, when input voltage is +5V. Given R = 1K
b
& V
CC
+5V.
Figure.2
b) Write about diode switching times.
4. a) Explain the switching characteristics of a bipolar junction transistor.
b) A germanium transistor is operated at room temperature in the CE configuration. The supply
voltage is 6 V, the collector-circuit resistance is 200 and the base current is 20 percent higher
than the minimum value required to drive the transistor into saturation. Assume the following
transistor parameters: I = -5A, I = -2A, h = 100, and r = 250. Find V (Sat) and
co
EO
FE
bb'
BE
V (Sat).
CE
5. a) Explain how transistor can be used as a switch in the circuit, under what condition a
transistor is said to be OFF and ON respectively.
b) A germanium transistor is operated at room temperature in the CE configuration. The supply
voltage is 6 V, the collector-circuit resistance is 200 and the base current is 20 percent
Page 39
higher than the minimum value required to drive the transistor into saturation. Assume the
following transistor parameters:
I = -5A, I = -2A, h = 100, and r = 250. Find V (Sat) and V (Sat).
co
EO
FE
bb'
BE
CE
6. a) With neat sketches and necessary equations, explain in detail about transistor switching
times.
b) Explain
Zener
&
Avalanche
breakdown
mechanisms in diodes.
7.
a)
Explain the phenomenon of latching
in
a
transistor switch.
b)
For
the CE transistor circuit shown in
Figure.2, V = 15V and R = 1.5K.
CC
Calculate the power dissipation in the transistor, when it is in

i) cut-off ii) saturation.
Figure.2
8. a) Explain the transistor switch in saturation region.
b) Explain the diode switching characteristics.
9. (a) Explain the terms pertaining to transistor switching characteristics.
i. Rise time. ii. Delay time. iii. Turn-on time. iv. Storage time. v. Fall time. vi. Turn-off time.
(b) Give the expression for risetime and falltime in terms of transistor parameters and operating
currents.
10.(a) Diode switching times
(b) Switching characteristics of transistors
(c) FET as a switch
1.Draw and explain the circuit of Astable Multivibrator with necessary waveforms and also derive
the expression for its frequency of oscillations.
2.a) Explain different triggering methods of binary circuits.
b) What are transpose capacitors? Explain how the commutating capacitors will increase the
speed of a fixed-bias binary
3. Draw the circuit diagram for Schmitt trigger and explain its operation. What are the
applications of the above circuit? Derive the expressions for UTP and LTP.
4.In the monostable circuit shown in figure.2, the resistor R is connected to an auxiliary supply
V1 instead of V . If Q2 is in saturation or clamp and if Q1 is OFF in the stable state, verify that
YY
Page 40
the gate time T is given by equation, T = ln (V +I R V ) / (V

YY
YY
V ) with V
YY
replaced by
V1.
5. a) With reference to multivibrators, explain:
i) stable-state ii) loop-gain iii) quasi stable-state
b) Design a collector coupled astable multivibrator for the following specifications with silicon
transistor. I (sat) = 10mA; h (min) = 20; V =10V; pulse width=10sec; duty cycle=40%.
C
fe
CC
6. a. Design the Astable Multivibrator to generate 5 KHz square wave. The supply voltag
VCC=10V, IC(sat)=10mA hFE=50 and assume Si transistors.
b. Explain the operation of Schmitt trigger wit h circuit diagram and and waveforms. Define UTP
and LTP.
7.a. Explain the operation of Astable Multivibrator and derive the expression for time-period of
output square wave.
b. Design collector coupled fixed-bias Bistable Multivibrator to operate from 6Vsupply.Given
IC(sat)= 1mA, hFE=35. Assume Si transistor.
8. a. Explain the operation of Fixed-Bias Bistable multivibrator with circuit diagram and
wavefoms.
b. Design collector coupled monostable multivibrator for the following specificatios. VCC=10V,
VBB= -5V, IC(sat)= 10mA, hFE=20 ,VBE(off)= -0.5V, Output pulse width tp= 200S. (assume
Si transistors)
9. a. Design the Astable Multivibrator to generate 1 KHz square wave. The supply voltag
VCC=10V, IC(sat)=10mA hFE=50 and assume Si transistors.
b. Explain the operation of Monostable Multivibrator wit h circuit diagram and derive the
expression for output pulse width.
10. (a) Draw the circuit diagram of a Schmitt trigger circuit and explain its operation. Derive the
Expressions for its UTP and LTP.
(b) Explain how an Schmitt trigger circuit acts as a comparator.
1.a) With the help of a circuit diagram and waveforms, explain frequency division of an astable
multivibrator with pulse signals.
b) With a neat sketch, explain the frequency division by a factor of 2 in sweep generators.
2. Define sweep speed error, transmission error and displacement error pertaining to sweep
circuits. Also derive the expressions for the same with respect to an exponential sweep circuit.
3. 1.(a) How are linearly varying current waveforms generated?
(b) In the boot strap circuit shown in figure5 Vcc = 25 V, VEE = -15 V, R = 10 K ohms, RB =
150 K
ohms, C = 0.05 F. The gating waveform has a duration of 300
s. The transistor parameters are hie = 1.1Kohms, hre = 2.5 x 104 K ohms hfe =50 hoe =
1/40K ohms.
i. Draw the waveform of IC1 and Vo , labeling all current and voltage levels,
ii. What is the slope error of the sweep?
iii. What is the sweep speed and the maximum value of the sweep voltage?
iv. What is the retrace time Tr for C to discharge completely?
v. Calculate the recovery time T1 for C1 to recharge completely.
4 .(a) What is a Linear time base generator? Give its Applications
Page 41
(b) Write the differences between the voltage and current time base generators?
(c) Why the time base generators are called sweep circuits?
5. (a) What is a linear time base generator?
(b) Write the applications of time base generators.
(c) Define the sweep speed error, displacement error and transmission error of voltage time
base waveform
6. (a) If the amplifier gain is different from unity in a bootstrap circuit, what is the effect on the
sweep voltage? What is the effect of amplifier bandwidth on the sweep output?
(b) In UJT sweep circuit VBB = 20 V, VY Y = 50V, R = 5k , RB1 = RB2 = 0 and C= 0.01 F.
the UJT fires when Vc = 10.6V and goes to OFF state when Vc = 2.8V. Find the
i. the amplitude of sweep signal
ii. the slope and displacement error
iii. the duration of the sweep, and
iv. the recovery time
7. (a) Draw the circuit diagram of fixed amplitude sweep circuit and explain its operation.
(b) Draw the circuit diagram of transistor Miller time base generator and explain its working.
8. (a) With the help of neat diagram explain the working of transistor Bootstrap time base
generator.
(b) Draw a simple current sweep circuit and explain its working with the help of diagrams.
9.(a) Draw and clearly indicate the restoration time and flyback time on the typical waveform of a
time
base voltage.
(b) Derive the relation between the slope, transmission and displacement errors
(c) Explain how UJT is used for sweep circuit?
10. (a). Explain the basic principles of Miller and Bootstrap time base generators.
(b). Define the terms slope error, displacement error and transmission error of time-base signal
1. a) With the help of a circuit diagram and waveforms, explain frequency division of an astable
b) Describe synchronization with 2:1 frequency division with neat waveforms
2. (a) Explain the method of synchronization of a sinusoidal oscillator with pulses.
(b) Describe frequency division employing a transistor monostbale multivibrator.
3. (a) Describe the sine wave frequency division with a sweep circuit.
(b) Compare sine wave synchronzation with pulse synchronization.
(c) What is Synchronization on one-to-one basis?
4. (a) With the help of a circuit diagram and waveforms, explain frequency division of an astable
(b) The relaxation oscillator, when running freely, generates an output signal of peak - to - peak
amplitude 100V and frequency 1 kHz. Synchronizing pulsesare applied of such amplitude
that at each pulse the breakdown voltage is lowered by 20V. Over what frequency range
may the sync pulse frequency bevaried if 1 : 1 synchronization is to result? If 5 : 1
synchronization is to beobtained (fP /fS = 5), over what range of frequency may the pulse
source be varied?
Page 42
5. (a) What is relaxation oscillator? Name some negative resistance devices used as relaxation
oscillators
and give its applications.
(b) With the help of a circuit diagram and waveforms, explain the frequency division by an
astable multivibrator?
6. (a) What do you mean by synchronization ?
(b) What is the condition to be met for pulse synchronization?
(c) Compare sine wave synchronization with pulse synchronization?
7. (a) Explain the factors which influence the stability of a relaxation divider with the help of a
neat waveforms.
(b) A UJT sweep operates with Vv = 3V, Vp=16V and =0.5. A sinusoidal synchronizing
voltage of 2V peak is applied between bases and the natural frequency of the sweep is 1kHz,
over what range of sync signal frequency will the sweep remain in 1:1 synchronism with the
sync signal?
8.a) What is relaxation oscillator? Name some negative resistance devices used as relaxation
oscillators and give its applications.
9. (a) Explain how monostable multivibrator is used as frequency divider?
(b) Draw and explain the block diagram of frequency divider without phase jitter.
10.a) Draw the circuit diagram of an astable multivibrator to obtain frequency division by 6.
Explain its working with waveforms.
(b) Explain the terms phase delay and phase jitter.
1.a) Explain the operation of a six - diode gate.
b) Briefly describe the operation of chopper amplifier.
2. a) Draw the circuit of FOUR-DIODE sampling gate. Derive expressions for its gain (A) and
V .
min
b) Explain the application of sampling gate in a sampling scope.

3. a) Illustrate the principle of sampling gates with series and parallel switches and compare them.
b) Explain with circuit diagram the operation of a two input sampling gate which does not have
any loading effect on control signal.
4. a) Draw the circuit of two-diode bi-directional sampling gate. Explain its operation & derive
expressions for gain and minimum control voltage in the circuit.
b) Illustrate the principle of sampling gates with series and parallel switches and compare them.
5. a) Illustrate with neat circuit diagram, the operation of unidirectional sampling gate for multiple
inputs.
b) Derive expressions for gain and minimum control voltages of a bi-directional two- diode
sampling gate.
6. a) Explain the operation of a six - diode gate.
b) Briefly describe the operation of chopper amplifier.
7. a) Draw the circuit of FOUR-DIODE sampling gate. Derive expressions for its gain (A) and
V .
min
b) Explain the application of sampling gate in a sampling scope.

8.(a) Why are sampling gates called linear gates?
Page 43
(b) What are the other names of a gate signal?

(c) Compare the unidirectional and bi-directional sampling gates.
9.(a) Explain the effect of circuit capacitances on the operation of a bi-directional diode gate.
(b) In the circuit of figure 2 consider that RL=RC=100K ohms and that R2=2 K ohms, Rf=50
ohms for Vs=25V, compute A, Vnmin, and Vcmin.
10.(a) Explain the basic principles of sampling gates using series switch and also give the
applications of sampling gates.
(b) Explain the effect of control voltage on gate output of unidirectional sampling gate using
diode with some example.
1.a) Define positive and negative logic system
b) Define fan-in and fan-out
c) Draw and explain the circuit diagram of a diode OR gate for positive logic.
2. a) Realize two-input AND & OR gates using diodes and explain their operation with the help of
truth-tables.
b) Realize a three-input NOR gate using Resistor Transistor Logic and explain its operation
with the help of truth-table
3. a) Realize NAND & NOR gates using CMOS Logic and explain their operation with the help
of truth-tables.
b) Draw the circuit diagram of Resistor-transistor logic NOR gate and explain its operation.
4. a) Explain about DTL NAND gate.
b) Give some applications of logic gates.
c) Define positive and negative logic systems.
5. a) With reference to logic families, define:
i) Positive & negative logic system ii) Fan-in & fan-out
b) Draw and explain the circuit diagram of a diode OR gate for positive logic.
6. a) Realize two-input AND & OR gates using diodes and explain their operation with the help of
truth-tables.
b) Realize a three-input NOR gate using Resistor Transistor Logic and explain its operation
with the help of truth-table.
7. a) Explain about DTL NAND gate.
b) Give some applications of logic gates.
c) Define positive and negative logic systems.
8. a) With reference to logic families, define:
i) Positive & negative logic system
Page 44
ii) Fan-in & fan-out

b) Draw and explain the circuit diagram of a diode OR gate for positive logic.
9 (a) Why totem pole is used in DTL? Draw the circuit diagram and explain a DTL gate with this.
(b) Verify the truth table of RTL NOR gate with the circuit diagram of two inputs.
10.(a) Draw and explain the circuit diagram of integrated positive DTL NAND gate
(b) Consider a two input positive logic diode OR and AND gates. Sketch the output waveform.
Shown in figure
Page 45
ASSIGNMENt
QUESTIONS
Assignment Questions
ASSIGNMENT QUESTIONS
Unit I: LINEAR WAVE SHAPING
1. A pulse generator with an output resistance R s = 500 is connected to an

oscilloscope with an input capacitance of Ci=30 pf. Determine the fastest rise time
that can be displayed.
2. A 10V step is switched on to a 50k resistor in series with a 500pf capacitor.
Calculate the rise time of the capacitor voltage, the time for the capacitor to charge to
63.2% of its maximum voltage, the time for the capacitor to be completely charged.
3. An ideal 1s pulse is fed to an amplifier. Calculate and plot the output waveform
under the following conditions: The upper 3-db frequency is i) 10MHz ii) 0.1MHz.
4. The periodic waveform shown in figure 1.1 is applied to an RC integrating network
whose time constant is 10s. Sketch the output waveform. Calculate the maximum
and minimum values of the output voltage with respect to ground under steady state
conditions. Also calculate and plot the output for the first two cycles.
fig ure1.1
1. Draw the transfer characteristics for the circuit shown in figure 2.1. Also draw the output
Waveform for a sinusoidal input of amplitude of 20V.
Figure 2.1
2. The input voltage vi to the two level clipper show in figure 2.2 varies linearly from 0 to
150V. Sketch the output voltage vo to the same time scale as the input voltage. Assume ideal
diodes.
Page 47
figure 2.2
3.(a) Draw the diode comparator circuit and explain the operation of it when ramp
input signal is applied.
(b) Explain the operation of two level slicer.
4.(a) For the circuit shown in figure 2a , Vi is a sinusoidal voltage of peak 100
volts. Assume ideal diodes. Sketch one cycle of output voltage. Determine
the maximum diode Current.
(b) Explain positive peak clipping with reference voltage.

5. (a) Draw the basic circuit diagram of negative peak clamper circuit and explain
its operation.
(b) What is meant by comparator and explain diode differentiator comparator
operation with the help of ramp input signal is applied
6. (a) Determine Vo for the network shown in figure 1 for the given waveform. Assume ideal Diodes.
Page 48
7. a. Draw the shunt clipper that clips the sine wave signal above +5V and explain its
Working with waveforms.
b. Draw the circuit of combinational clipper and explain with its transfer
Characteristics
8. a. Explain the operation of positive clamper circuit using diode.
b. State and prove clamping circuit theorem with relevant circuit and waveforms
9. a. Explain the operation of negative clamper circuit using diode.
b. State and prove clamping circuit theorem with relevant circuit and waveforms.
10 a. Draw the diode shunt clipper that clips the sine wave signal above +5V and below -5V.
Explain its Working with transfer characteristics.
b. Explain the working of an Emitter coupled clipper with circuit diagram.

1. A common- emitter circuit (figure 3.1) has Vcc = 20V and a collector resistor which can
be either 20k or 2k . Calculate the minimum level of base current to achieve saturation in
case.
figure 3.1
2. For CE transistor with Vcc = 15 V, Rc= 1.5K , Calculate the transistor power dissipation a)
At cut off and at saturation.figure3.2
Page 49
figure3.2
1. The fixed bias binary shown in figure 4.1 uses n p n silicon transistors with Vce(sat)
=0.5V, Vbe(sat) = 1V, Icbo = 10nA at 25 deg C and zero base to emitter voltage at cut off.the
circuit parameters are Vcc = Vbb = 6V, Rc = 1.2k , R1= 4.7k ,R2 = 27k .
Find a) hfe(min) and stable state voltages and currents.b)if the reverse saturation current
doubles for every 10 deg C rise in temp,what is the maximum temperature at which the
circuit can operate properly with one device remaining OFF?
figure 4.1
2. For the astable multivibrator shown in figure 4.2 if R1=20k , R2= 10k , C1= 0.02F
and C2=0.015F. find the frequency of oscillation and duty cycle of the output waveform.
figure 4.2
Page 50
3. Find the ratio Vcc/V, if a voltage to frequency converter generates oscillations of frequency
twice of that whenV = Vcc.

1. In the UJT sweep circuit of figure 5.1 Vbb=20V, Vyy=50V, R=5k , Rb1=Rb2=0 ,and
C=0.01F. Using UJT characteristics, find a) the amplitude of a sweep signal, b) the slope
and displacement errors, c)the duration of the sweep, and d) the recovery time.
2.
Design a relaxation oscillator to have 2 kHz output frequency, using 2N3980 and a 20V
supply. Calculate the output amplitude. (Note: the specification from the data sheet are given
as = 0.68 to 0.82, Ip = 2A, Iv =1 mA and Veb(sat)= 3V. figure 5.2.
figure 5.2, 5.1.

3. The specification of UJT are given as = 0.6,Vv = 2V, Rbb = 5k , Iv = 1.5mA, Ip
=8A, and Vbb = 18 V. Calculate the component values of the UJT sweep circuit to generate
an output sweep frequency of 10kHz with a sweep time of 12V. figure 5.2

1. Explain phase delay and phase jitters.
2. Explain monostable relaxation circuits as dividers.
3. (a) Describe the sine wave frequency division with a sweep circuit.
(b) Compare sine wave synchronzation with pulse synchronization.
(c) What is Synchronization on one-to-one basis?
4. (a) With the help of a circuit diagram and waveforms, explain frequency division
of an astable multivibrator with pulse signals.
(b) The relaxation oscillator, when running freely, generates an output signal of peak - to peak amplitude 100V and frequency 1 kHz. Synchronizing pulses
are applied of such

Page 51
amplitude that at each pulse the breakdown voltage is lowered by 20V. Over what frequency
range may the sync pulse frequency be varied if 1 : 1 synchronization is to result? If 5 : 1
synchronization is to be obtained (fP /fS = 5), over what range of frequency may the pulse
source be varied?
5. (a) What is relaxation oscillator? Name some negative resistance devices used as relaxation
oscillators and give its applications.
6. (a) What do you mean by synchronization ?
(b) What is the condition to be met for pulse synchronization?
(c) Compare sine wave synchronization with pulse synchronization?

1. Explain about sampling scope.
2. Explain about chopper amplifier.
3. Explain basic operating principle of sampling gates.
4. a. What are the applications of sampling gates.
b. Explain unidirectional and bidirectional sampling gates.
5. a. Explain the Basic operating principle of sampling gate.
b. Explain unidirectional and bidirectional sampling gates
6. (a) Why are sampling gates called Selection circuits?
(b) What are the advantages of unidirectional sampling gates?
(c) What are the applications of sampling gates?
7.(a) What is sampling gate? Explain how it differ from Logic gates?
(b) What is pedestal? How it effects the output of a sampling gates?
(c) What are the drawbacks of two diode sampling gate?
.
1. Realization of NAND and NOR gate using diode and transistors.
2. Realization of universal gates using NAND and NOR gates.
3. (a) Draw the circuit diagram of diode - resistor logic OR gate and explain its operation.
Page 52
(b) The transistor inverter (NOT gate) circuit has a minimum value hfe = 30, VCC = 12V, RC
= 2.2k, R1 = 15k and R2 =100k, VBB = 12V. Prove that circuit works as NOT gate. Assume
typical junction voltages. The input is varying between 0 and 12V
4. (a) Draw the circuit diagram of diode - resistor logic OR gate and explain its
operation.
(b) The transistor inverter (NOT gate) circuit has a minimum value hfe = 30,
VCC = 12V, RC = 2.2k, R1 = 15k and R2 =100k, VBB = 12V. Prove that circuit works as
NOT gate. Assume typical junction voltages. The input is varying between 0 and 12V.
5. a. Draw the circuit of 3-input OR gate using diodes and resistors and explain with
truth table.
b. Draw the circuit diagram of NAND gate using DTL logic and explain.
6. a. Draw the circuit of 3-input AND gate using diodes and resistors and explain with
truth table.
b. Draw the circuit diagram of NAND gate using TTL logic and explain.
****THE END***
Page 53
SWITCHING THEORY
AND LOGIC DESIGN
mr.S.sreehari
AssT. Professor
COURSEFILE
Department of

Sponsored by
COURSE
OBJECTIVE
Switching theory and logic design
Course Objective
COURSE OBJECTIVE
This course is a comprehensive study of principles and techniques of designing digital systems. It
teaches the fundamentals of digital systems applying the logic design and development techniques. This
provides the platform to learn principles of digital systems logic design and distinguish between analog
and digital representations. It will be able to analyze a given combinational or sequential circuit using kmap and Boolean algebra as a tool to simplify and design logic circuits. Construct and analyze the
operation of a latch flip-flop and its application in synchronization circuits.
This provides the following key features
Understand the different number system, its conversions and binary arithmetic.
Know the fundamentals of Boolean algebra and theorems, Karnaugh maps including the
minimization of logic functions to SOP or POS form.
Analysis of logic circuits and optimization techniques to minimize gate count, signals, IC count,
or time delay.
To strengthen the principles of logic design and use of simple memory devices, flip-flops, and
sequential circuits.
To fortify the documentation standards for logic designs, standard sequential devices, including
counters and registers.
To understand the logic design of programmable devices, including PLDs, RAMS, and ROMS
including its sequencing and control.

Page 56
Syllabus
Syllabus
SYLLABUS
UNIT I: Number Systems & Codes:
Philosophy of number systems complement representation of negative numbers-binary arithmeticbinary codes-error detecting & error correcting codes hamming codes
UNIT II: Boolean Algebra And Switching Functions:
Fundamental postulates of Boolean Algebra - Basic theorems and properties - switching functions
Canonical and Standard forms-Algebraic simplification digital logic gates, properties of XOR gates
universal gates-Multilevel NAND/NOR realizations.
UNIT III: Minimization Of Switching Functions:
Map method, Prime implicants, Dont care combinations, Minimal SOP and POS forms, Tabular
Method, Prime Implicant chart, simplification rules
UNIT IV: Combinational Logic Design:
Design using conventional logic gates, Encoder, Decoder, Multiplexer, De-Multiplexer, Modular
design using IC chips, MUX Realization of switching functions Parity bit generator, Code-converters,
Hazards and hazard free realizations.
UNIT V: Programmable Logic Devices, Threshold Logic:
Basic PLDs-ROM, PROM, PLA, PLD Realization of Switching functions using PLDs. Capabilities
and limitations of Threshold gate, Synthesis of Threshold functions, Multigate Synthesis.
UNIT VI: Sequential Circuits - I:
Classification of sequential circuits (Synchronous, Asynchronous, Pulse mode, Level mode with
examples) Basic flip-flops-Triggering and excitation tables. Steps in synchronous sequential circuit
design. Design of modulo-N Ring & Shift counters, Serial binary adder, sequence detector
UNIT- VII: Sequential Circuits - II:
FET common source amplifiers, Common Drain Amplifies, Generalized FET amplifiers, Biasing FET,
FET as voltage variable resistor, Comparison of BJT and FET, The UJT
UNIT-VIII: Algorothimic State Machines:
Salient features of the ASM chart-Simple examples-System design using data path and control
subsystems-control implementations-examples of Weighing machine and Binary multiplier.
TEXT BOOKS:
1. Switching & Finite Automata theory Zvi Kohavi, TMH,2nd Edition
2. Digital Design Morris Mano, PHI, 3rd Edition, 2006.
3. Switching theory and logic design-Bhanu baskar

Page 58
Syllabus
REFERENCE BOOKS:
1. An Engineering Approach To Digital Design Fletcher, PHI. Digital Logic Application and
Design John M. Yarbrough, Thomson
2. Fundamentals of Logic Design Charles H. Roth, Thomson Publications, 5th Edition, 2004.
3. Digital Logic Applications and Design John M. Yarbrough, Thomson Publications, 2006
WEBSITES:
1.
2.
3.
4.
5.
www.asic-world.com/digital/gates3.html
en.wikipedia.org/wiki/Hamming_code
www.hyperphysics.phy-astr.gsu.edu/hbase/electronic/dflipflop.html
en.wikipedia.org/wiki/Algorithmic_State_Machine
www.ocho.uwaterloo.ca/Teaching/192/ASM.ppt

Page 59
STUDENT'S
SEMINAR
TOPICS
Seminar Topics

1. conversion of number format
2. hamming codes
3. properties of Boolean Algebra with some examples
4. realization of universal gates
5. Realization of logic gates
6. Basic flip flops
7. Shift counters
8. Mealy and Moore models
9. Features of ASM chart
10. Sequence detector

Page 61
LECTURE PLAN
Electronic Devices & Circuits
Lecture Plan
LECTURE PLAN
S.No
NAME OF THE TOPIC
No of
Periods
UNIT I: Number Systems & Codes

1
Black board and
2
Chalk
Black board and
2
Chalk
1.
Introduction
2.
History of number systems
3.
Number representation
4.
Binary arithmetic
5.
Binary codes- weighted codes
11.
Fundamental postulates of Boolean algebra
12.
Basic theorems and properties
13.
Switching functions
14.
Canonical and standard forms
6.
7.
8.
9.
10.
Method of
Teaching
Black board, Chalk
Black board and

Chalk
Black board and
Binary codes- Nonweighted codes
2
Chalk
Black board and
Error detecting codes
2
Chalk
Black board and
Error correcting codes
2
Chalk
Black board and
Hamming codes
2
Chalk
Complement representation of negative
Black board and
2
numbers
Chalk
UNIT II: Boolean Algebra And Switching Functions
Black board, Chalk

Black board and
Chalk
Black board and
Chalk
Black board and
Text books referred
--Switching & Finite Automata theory Zvi

Kohavi, TMH,2nd Edition
Digital Design Morris Mano, PHI, 3rd
Edition, 2006
Edition, 2006
Switching & Finite Automata theory Zvi
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
II B.Tech 2nd Semester
Page 63
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
Lecture Plan
Chalk
Algebraic simplification digital logic gates,
Black board and
2
properties of XOR gates
Chalk
Black board and
Universal gates
3
Chalk
Black board and
2
Multilevel NAND/NOR realizations
Chalk
UNIT III: Minimization Of Switching Functions
Black board and
Map method
2
Chalk
Black board and
Prime implicants
2
Chalk
Black board and
Dont care combinations
2
Chalk
Black board and
Minimal SOP and POS forms
2
Chalk
Black board and
Tabular method
2
Chalk
Black board and
Prime implicant chart
2
Chalk
Black board and
Simplification rules
2
Chalk
UNIT IV: Combinational Logic Design
Black board and
Design using conventional logic gates
2
Chalk
26.
Encoder
Black board, Chalk
27.
Decoder
Black board, Chalk
28.
Multiplexer
Black board, Chalk
29.
De-multiplexer
Black board, Chalk
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Page 64
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
Lecture Plan

Edition, 2006
MUX realization of switching functions
2
Black board, Chalk
Edition, 2006
Parity bit generators
2
Black board, Chalk
Edition, 2006
2
Black board, Chalk
Code-converters
Edition, 2006
Black board and
Hazards and hazard free realization
2
Chalk
Black board and
Capabilities and limitations of threshold gates
2
Chalk
Edition, 2006
Black board and
Synthesis of threshold functions
2
Chalk
UNIT V: Programmable Logic Devices, Threshold Logic
Black board and
Basic PLDs
2
Chalk
Edition, 2006
Black board and
ROM
2
Chalk
Edition, 2006
Black board and
PROM
2
Chalk
Edition, 2006
Black board and
PLA
2
Chalk
Edition, 2006
Black board and
PLD
2
Chalk
Edition, 2006
Black board and
Realization of switching functions using PLDs
2
Chalk
Edition, 2006
Black board and
Multi gate synthesis
2
Chalk
Edition, 2006
UNIT VI: Sequential Circuits I
Classification of sequential circuits(synchronous,
Black board and
2
pulse mode, level mode with examples)
Chalk
Edition, 2006
Basic flip-flops triggering and excitation tables
3
Black board and
Modular design using IC chips
Black board, Chalk

Page 65
46.
47.
48.
49.
Lecture Plan
Chalk
Black board and
Steps in synchronous sequential circuit design
1
Chalk
Black board and
Design of modulo-N ring and Shift counters
2
Chalk
Black board and
Serial binary adder, sequence detector
2
Chalk
UNIT- VII: Sequential Circuits - II
Black board and
Finite state machine-capabilities and limitations
1
Chalk
50.
Mealy and Moore models
51.
Minimization of completely specified and

incompletely specified sequential machines
52.
Partition techniques
53.
Merger chart methods
54.
Concept of minimal cover table
55.
56.
57.
58.
59.
60.
Black board, Chalk

Black board and
Chalk
Black board and
Chalk
Black board, Chalk
Black board and

Chalk
UNIT-VIII: Algorothimic State Machines
Black board and
Salient features of ASM chart
1
Chalk
Black board and
Simple examples
2
Chalk
Black board and
System design using path and control subsystem
2
Chalk
Black board and
Control implementations
1
Chalk
Examples of weighted machine and binary
Black board and
1
multiplier
Chalk
Black board and
1
Chalk
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Edition, 2006
Digital Design Morris Mano
Notes
Page 66
Lecture Plan
61.
62.
63.
Black board and

Chalk
Black board and
Chalk
Black board and
Chalk
Notes
Notes
Notes

Page 67
LEARNING
OBJECTIVES
Learning Objective
LEARNING OBJECTIVES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
What is gary code? What are the rules to construct gray code? Develop the 4 bit gray code for the
decimal 0 to 15
List the XS3 code for decimal 0 to 9
What are the rules for XS3 addition? Add the two decimal numbers 123 and 658 in XS3 code
Test if these code words are correct, assuming they were created using an even parity hamming
code. If one is incorrect, indicate what the correct code should have been. Also, indicate what the
original data was
a. 010101100011
b. 111110001100
c. 000010001010
Why the binary number system is used in computer design?
Given the binary numbers a=1010.1 b=101.01 c=1001.1, perform the following:
a+c
a-b
a.c
Convert (2AC5.D)16 to binary and then to octal.
What is the necessity of binary codes in computers?
Encode the decimal numbers 0 to 9 by the means of the following weighted binary codes:
421
2421
6 4 2 -3
Explain how to subtract BCD numbers, by stating the rules for generating borrows and applying
the correction factor with suitable examples
Determine which of the above codes are self-complimenting and why
Encode 11 information bits with suitable parity groups of distance-4 hamming code
Write brief about reflective code, sequential codes, non-weighted codes, excess-3 code, gray
code, repetition codes, checksums, cyclic redundancy checks(CRCs), cryptographic hash
functions.
Write a brief about hamming codes and hamming distance.
Perform the following
(i)
10100.11012=?16
(ii)
75310=?5
(iii)593BCD-971BCD=?BCD

1
2
3
4
State the laws of Boolean algebra

List out the basic operations of Boolean algebra
Represent diagrammatically the basic gates
Relate the basic operations & laws of Boolean algebra to circuits composed of basic gates
Apply these laws to the manipulation of algebraic expressions including

Page 69
Learning Objective
a.Multiplying out an expression to obtain a sum of products.

b.Factoring an expression to obtain a product of sum
c.Simplifying an expression by applying one of these laws
d.Finding the complement of an expression
5 Define the Exclusive OR & equivalence operations
6 Draw a circuit that uses two OR gates & two AND gates to realize the following
function:F=(V+W+X)(V+X+Y)(V+Z)
7 prove the following function using truth tables:wxy+wz=(w+z)(w+xy)
factor to obtain a product of sum:
ABC+ACD+ABC+BCD
8 State and prove Boolean laws
9 Which gate can be used as parity checker? Why?
10 Simplify the following Boolean functions to minimum number of literals:
(a+b)(a+b)
y(wz+wz)+xy
11 realize XOR using minimum number of NAND gates
12 prove AND-OR network is equivalent to NAND-NOR network

1 Obtain the prime-implicant chart for the following logic function and obtain the minimal
expression F (A,B,C,D,E) = (0,1,2,3,4,5,10,151,14,20,21,24,25,26,27,28,29,30)
2 Using Karnaugh maps, find minimal SOP expressions for the following logic functions.
a) F = w,x,y,z ( 0,1,2,3,7,8,10,11,15) (4M)
b) F = w,x,y,z ( 4,5,9,13,15) + d(0,1,7,11,12) (6M)
c) F = A,B,C,D (1, 5, 12, 13, 14, 15) + d(7, 9)
3 Using 5-variable Karnaugh maps, find minimal SOP expressions for the following logic
functions.
a) F (A, B, C, D, E) = (0,2,4,5,6,7,8,10,14,17,18,21,29,31) + d(11,20,22)
b) F(A,B,C,D,E) = (4,6,7,9,11,12,13,14,15,20,22,25,27,28,30)+ d(1,5,29,31)
4 Realize XOR gate using minimum number of NAND gates
5 Simplify the following Boolean expressions using K-map and implement them using NOR
gates:
(a)
F
(A,
B,
C,
D)
=
ABC
+
AC
+
ACD
(b) F (W, X, Y, Z) = WXYZ + WXYZ + WXYZ + WXYZ
6 Design BCD to Gray code converter and realize using logic gates
7 Design 2*4 decoder using NAND gates.

1. Discuss about the IC chips of decoder, multiplexer and de-multiplexer circuits
2. Realize 5-32 line decoder using multiple 3-8 line 74x138 decoders

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Learning Objective
3. F(n)= m( 5,7,13,15,16,20,25,27,29,31) Realize using 2n-1x1 multiplexer

4. Find all of the static hazards in the two level AND-OR or OR-AND realizations of the following
logic expressions? Design a hazard free circuit that realizes the same logic function.
F = (W + Y + Z ).(W + X + Z ).(X + Y + Z )
5. Design logic circuit for parity bit generator
6. What is decoder? How do you convert a decoder in to a De-Multiplexer
7. F(w,x,y,z) = m (1,4,5,6,7,9,14,15) Realize using De-Multiplexer
8. Explain the differences between multiplexers and De-multiplexers with the help of neat logic
diagrams.
Unit V: Programmable Logic Devices, Threshold Logic

Draw the logic diagram of Programmable Logic Array? Explain its operation
Realize threshold function f = 2.5x + 3y -1.5z
Briefly describe about the Programmable Array Logic with suitable diagrams
Draw the functional diagram 5-32 line decoder using PLA
Draw the functional logic diagram of PLA and explain its operation
Realize logic expressions of seven segment display with suitably sized ROM
Explain the general CPLD configuration with suitable block diagram.
Write short notes on PLDS
Draw the basic macro cell logic diagram and explain.
10. Derive a PLA programming table for the combinational circuit that squares a
3 bit number.
11. Determine the ROM size to realize the following logic functions
a) BCD to Excess -3 code converter
b) 5-32 line decoder
1.
2.
3.
4.
5.
6.
7.
8.
9.
UNIT VI: Sequential Circuits - I

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Draw the circuit of JK Flip Flop using NAND gates and explain its operation.
Draw and explain the working of 4 bit UP/DOWN synchronous counter.
What is meant by Asynchronous sequential circuits? Design Asynchronous modulo-10 counter.
Draw the circuit diagram of master and slave JK flip flop? Explain its operation.
Draw the logic diagram of a 4 bit binary ripple counter using positive edge triggering.
Draw the block diagram of a 4 - bit serial adder and explain its operation.
Write short notes on the following: (i) Triggering of Flip-Flops ; (ii) Synchronous counters
Design a 4-bit ripple down counter using T flip-flop and no other components.
Design modulo-11 counter with counting sequence 4, 5, 6.13, 14, 4, 5, 6..
Design a clocked synchronous state machine using D flip flops of the following state/output
table? Use two state variables, Q1 Q2 with state assignments A=00, B=01, C=11, D=10.

Page 71
Learning Objective

1. Explain the state minimization procedure with the help of example.
2. Discuss about the capabilities and limitations of Final State Machines
3. Explain the path sensitisation method with an example
4. Write the differences between Mealy and Moore type machines.
(b) A sequential circuit has 2 inputs w1=w2 and an output z. Its function is to compare the i/p
sequence on the two i/ps. If w1=w2 during any four consecutive clock cycles, the circuit
produces z=1 otherwise
z=0
w1= 0110111000110
w2= 1110101000111
z=0000100001110
5. For the machine given below find a minimum state reduced machine using Merger table.

Page 72
6.
Learning Objective
Find the equivalent partition and reduced machine for the machine given below

1. Draw the ASM chart and state table for the synchronous circuit having the following description
The circuit has a control input X, clock and outputs A and B. if X= 1, on every clock
rising edge code on BA changes from 00
01
10
11
00 and repeats. If
x=0, then circuit holds present state.
2. Draw the ASM chart for binary multiplier and realize using JK flip flop & gates. Draw the
timing diagram.
3. Discuss the procedure to implement an ASM chart using Multiplexer.
4. Draw an ASM chart for designing a circuit which is used to count the number
of bits in a register that have a value 1.
5. Design the synchronous state machine to generate the following sequence of states
35791

Page 73
OBJECTIVE
TYPE
QUESTIONS
Switching Theory and logic design

UNIT I: Number Systems & Codes:
1. Decimal number 21.125 may be written in binary system as:
(a)10101.010 (b)10100.001
(c)10101.001
(d)10100.100
2. The largest positive number that can be stored in a computer that has16-bitword length and uses
twos complement arithmetic is
[
]
(a)32767
(b)32768
(c)32
(d)65536
3. Binary 1000 when multiplied by binary 1111 results in binary:
(a)1110000
(b)1111111
(c)1111000
(d)1111100
4. 1k-byte is precisely equal to:
(a)1020bits
(b)1012bits
(c)1000bits
(d)1024bits
5. The1s compliment of 1s compliment of a given number is
(a)1s compliment
(b)9s compliment
(c)the same number itself
6. ASC-II code is used as:
(a) a7-bitcode
(c) an alphanumeric code
7.
(d) 2s compliment
[
(b) a 4-bitcode
(d) a 6-bitcode
Conversion from decimal to hex requires repeated division by

(a)16
(b)4
(c)10
(d)8
8.
Binary coded decimal (BCD) numbers express each decimal digit as :

[
]
(a)bit
(b)byte
(c)unit
(d)nibble
9. In hamming code parity bits are placed in which positions and the data are placed in which
positions?
[
]
(a) odd bit positions are parity bits and even bit positions are data bits
(b) starting from LSB are parity bits and remaining are data bits
(c) All bit positions that are power software used as parity bits and All other bit positions
are for the data to be encoded.
(d) Even bit positions and odd bit positions
10. The 2s compliment of binary number 001011 is
[
]
(a) 0.10100 (b) 1.10100
(c) 1.10101
(d) 0.10101
11. Decimal equivalent of octal number 57 is
[
]
(a) 47
(b) 67
(c) 57
(d) 37
12. Pick out the code from the following which is not a self complementing code
(a) 3321code (b)2421code
(c)8421code
(d)642-3
13. Decimal number 15 may be written in binary system as:
(a)1110
(b)1100
(c)1001
(d)1111
14. The2s compliment of binary number 001011 is
(a)1.10101
(b)0.10100
(c)0.10101
[
[
]
]
(d)1.10100

Page 75
15. Hexa decimal equivalent of decimal number 1000 is:

(a)3E8
(b)3E7
(c)3CF
(d)4E8
16. Decimal number 74 may be written in binary system as:

(a)1001010
(b)1001011
(c)1001001
(d)1000111
17. The1s compliment of 1s compliment of a given number is
(a)9scompliment (b)1scompliment
(c)2scompliment (d)the same number itself
18. Binary division 10010.1011

[
]
(a)101.11
(b)110.11
(c)101.10
(d)100.11
19. Excess-3 equivalent of decimal number 10is:
[
]
(a)1101
(b)1011
(c)1110
(d)1001
20. In the Hamming code 1001101,error has occurred in position
[
]
(a)5
(b)1
(c)4
(d)7
21. The minimum number of bits required to represent negative numbers in the range of -1 to -11
using 2s complement arithmetic is

[
]
(a)2 (b) 3 (c) 4 (d) 5
22. The following code is not a BCD code.
[
]
a)Gray code (b) Xs-3 code
(c) 8421 code
(d) All of these
23. A 15-bit hamming code requires
[
]
(a)4 parity bits
(b) 5 parity bits
(c) 15 parity bits
(d) 7 parity bits
24. When two n bit binary numbers are added , the sum will contain at the most
A) n bits
B) n+1 bits
C) n+2 bits
D) n +n bits
25. In a digital system performance accuracy depends on
[
]
A) nature of devices used B) number of gates C) word length D) propagation delay
ANSWERS:
1
11(a)
21.(d)
2(a)
12(d)
22.(a)
3
13(a)
23.(a)
4(d)
14(d)
24.(b)
5
15(a)
25.(c)
6
16
7(a)
17(d)
8(d)
18
9
19
10(a)
20
UNIT II: BOOLEAN ALGEBRA AND SWITCHING FUNCTIONS

1. The dual of a Boolean theorem is obtained by
(a) inter changing all zeros and ones only
(b) inter changing operators and identity elements
(c) changing all ones to zeros only
(d) changing all zeros to ones only
2. AB+A+1=
(a) B
(b) 1
(c) A
(d) 0
3. Which of the following gates is known as coincidence detector?
(a)NOT gate
(b)AND gate
(c)NAND gate (d)OR gate
4. The NAND can function as NOT gate if
(a) one input is set to 0
(b) inputs are left open
(c)inputs are connected together
(d)one input is set to 1
5. AB+A+0=
[ ]
[ ]
[ ]
[ ]
[ ]

Page 76
(a) B
(b)1
(c)0
(d)A
6. A gate can have input signals and output signals
[ ]
(a) two, two
(b)two or more,two or more
(c)one, one (d)one or more, one
7. Which of the following gates are added to the inputs of The OR gate to convert it into
NAND gate?
[ ]
(a) NOT
(b) OR
(c) AND
(d)XOR
8. Boolean algebra can be used to
[ ]
(a)Minimize the number of switches circular statement
(b)perform arithmetic calculations
(c)Solve the mathematical problems
(d) simplify any algebraic expressions
9. Which of the following Boolean algebra statements represent Commutative law [ ]
(a)A+(B+C)=(A+B) (b)A+B=B+A
(c)A(B+C)=AB+AC (d)A(BC)=(AB)C
10. An OR gate has 36 inputs. How many input words are there in its truth table?
[ ]
(a)64,000,000
(b)6
(c) 64
(d)36
11. The Boolean expression (XYZ+YZ+XZ) after simplification
[ ]
(a)Z
(b)X
(c)(X+Y)Z
(d)YC
12. In which of the following gates, the output is 0 If and only if
[ ]
atleast one input is 0?
(a)NOT
(b)NOR
(c)OR
(d)AND
13. Identify the pair of basic gates from the following
[ ]
(a)AND,NOT
(b)NAND,AND
(c)OR,NOR
(d)NOT,NAND
14. .In which of the following gates,the output is 1 If and only if one input is 1?
[ ]
(a)AND
(b)XOR
(c)NOT
(d)NORD
15. AB+AB+1=
[ ]
(a)B
(b)1
(c)0
(d)A
16. An OR gate has 6 inputs. How many input words are there in its truth table?
[ ]
(a) 64,000,000 (b)36
(c)6
(d)64
17. In which of the following gates,the output is 0 If and only if atleast one input is1? [ ]
(a)AND
(b)NOT
(c)XOR
(d)NOR
18. In Boolean algebra 0 is called
[ ]
(a)additive identity
(b)multiplicative inverse
(c)multiplicative identity
(d)additive inverse
19. The basic gates are
[ ]
(a)AND,OR,NOT (b)AND,ORNOR (c)NAND,NOR
(d)AND,OR,NAND
20.Which of the following gates are added to the inputs of The OR gate to convert it into
NAND gate
[ ]
(a)OR
(b)NOT
(c)AND
(d)XOR
21. The logic expression (A+B)( A+B) can be implemented by giving the inputs A and B
to a two-input
[ ]
(a)NOR gate
(b) NAND gate
(c) X-OR gate
(d) X-NOR gate
22. Which of the following Boolean algebraic expressions is incorrect?
[]
(a)A+ AB=A+B (b) A+AB=B (c) (A+B)(A+C)=A+BC (d) (A+B )(A+B)=A
23. The minimum number of bits required to represent negative numbers in the range of -1 to -11
using 2's complement arithmetic is
[
]
(a)2 (b)3 (c)4 (d) 5

Page 77
24. What is the minimum number of NOR gates required to realize an X-OR gating [
(a)2 (b)3 (c)4 (d) 5
ANSWERS:
1(a)
11
21.(c)
2(b)
12
22.(b)
3
13(a)
23.(d)
4
14(a)
24.(d)
5(d)
15(b)
6(d)
16
7(a)
17(a)
8(a)
18(d)
9(d)
19(a)
10(d)
20(b)

1. Which of the following code is used in K-map for representing them interms?
(a)BCD (b) Graycode (c)8421 (d) Excess-3code
[ ]
2. The given max term is A+B+C, its equivalent Binary representation is

(a)000 (b)101 (c)111
(d)010
[ ]
3. A 1ine cell of k-map can be combined with three other1sin Only one combination The resulting
term of these four 1s is
[ ]
(a) not prime implicant
(b)Dont care
(c)Essential Prime Implicant (d)Minterm
4. The minterm, designator of the term BCD is
(a)12
(b)15
(c)11
(d)10
[ ]
5. The necessary condition to combine the two minterms is Both minterm values must Be
differentiated by power of
[ ]
(a)2 (b)6 (c)4
(d)3
6. If F(A,B,C,D)=1then the K-map contains number of Logic1s is
(a)8 (b)32
(c)4
(d)16
[ ]
7. The Essential Prime Implicant of the function covers all the Minterms then there resultant
expression is a
[ ]
(a)logical expression
(b)arithematic expression
(c)not a unique expression (d)Unique expression
8. In Dont care a minterm /maxterm in a logic function which
(a)is always0
(b) must be included
(c)may or may not be included
(d)ignored
[ ]
9.Which of the following code is used in K-map for representing the minterms ?
(a) Graycode (b)BCD (c)8421 (d)Excess-3codeA
[ ]
10.A Prime Implicant which includes at least a1cell that is not covered by any other Prime
Implicant is called
[ ]
(a)self complimenting
(b)Dominent
(c)essential prime implicant
(d)prime implicant itself
11.The X mark in a cell may be assumed to be Upon which one leads to a simpler expression
(a)1or a 0 depending (b)only 0 (c) only 1 (d) always 2
[ ]

Page 78
12.A maxterm is term,which contains all the variables either in complemented or uncomplemented
form
[ ]
(a)product (b)exclusive (c)difference (d) sum
13. The number of cells in a 6-variable K-map is
(a)64 (b)6 (c)12 (d)36
[ ]
14. A minterm corresponding to Dont care condition may have a value of

(a)0or1
(b)only1 (c)dont care (d)only0
[ ]
15. The necessary condition to combine the two minterms is Both min term values must Be
differentiated by power of
[ ]
(a)4 (b)3
(c)6
(d)2
16. If sqrt(41)=5,the base(radix) of the number system is
[ ]
a)5
(b) 6
(c) 7
(d) 8
17. The hexadecimal number system is used in digital computers and digital systems to [ ]
(a) Perform arithmetic operations
(b) Perform logic operations
(c) Perform arithmetic and logic operations (d) Input binary data into the system.
18. The code used for labeling cells of the K-map is
A) natural BCD
B) Hexadecimal
D) Octal
]
C) Gray
19. Each term in the standard SOP form is called a
A) minterm B) maxterm C) don't care D) literal

ANSWERS:
1(b)
9(a)
2(a)
10(b)
3(c)
11(b)
17.(d)
18.(c)
19.(a)
4(c)
12(b)
5(a)
13(a)
6(d)
14(a)
7(d)
15(d)
8(c)
16.(b)

1. ROM is an example for
(a)Combinational digital circuit
(c) Both combinational and sequential
[ ]
(b)Registers
(d)sequential digital circuit
2. decoder with n inputs produces maximum of number of minterms

(a)2n (b) 2n-1 (c)2n-1 (d)2n
3. A full adder can be realized by
(a)one half-adder, one OR gate
(c)one half-adder, two OR gate
[ ]
(b)two-half-adder, two OR gates

(d)two-half-adder, one OR gates
4. What is the number of inputs,outputs of a decoder that accepts 64 different input combinations?
(a)5
(b)64
(c)6
(d)7
[ ]
5. In a single input-variable Change might cause a momentary incorrect output and output is
constant
[ ]

Page 79
(a) static hazard

(c)Dynamic hazard
(b)Delay problem
(d)synchronization
6.An one-of-16 line decoder can be constructed by using number Of one-of-2lined Encoder
(a)6 (b)3 (c)4 (d)5
[ ]
7.The size of the decoder required to implement 3-variable Boolean Function is
(a)3 to 8 line (b)2 to 4 line (c) 4 to 8 line (d) 4 to 16 line
[ ]
8.The circuit used for parallel to serial conversion of data is known as

(a)Adder (b)Multiplexer (c)parity encoder (d) Demultiplexer
[ ]
9.The race hazard problem occurs due to:

[ ]
(a)fixed low logic circuit
(b)time-delay in circuits due to high speed logic
(c)faulty design of logic circuits
(d)non-redundant form of the circuit
10.A1in a cell of k-map can be combined with three other 1s in Only one combination The
resulting term of these four1s is
[ ]
(a)Minterm
(b) Essential Prime Implicant
(c)not prime implicant
(d) Dont care
11.The number of full adders required to add two 4-bit data in a Serial adder
(a)2 (b)1 (c)4 (d)16B
[ ]
12.A 6-to-64 decoder can be obtained by cascading of

(a)four number 4-to16 decoders and one 2:4 decoder
(b) cannot possible
(c)five number 4-to16 decoders
(d)three number 4-to16 decoders and
two 2:4 decoder
13. A gate is enabled when its enable input is at logic 0. The gate is
[]
(a)NOR
(b) AND
(c) NAND
(d) None of these
14. The output of a logic gate is 1 , when all its inputs are at logic 0.The gate is either
[]
(a)a NOR or an X-NOR
(b) a NAND or an X-OR
(c) an OR or an X-NOR
(d) an AND or an X-OR
15. In which of the following adder circuits is the carry ripple delay eliminated?
A) half - adder
B) full - adder
C) parallel adder
D) carry-look-ahead adder
16) A serial adder requires only one
A) half - adder
B) full - adder
C) counter
D) multiplexer
ANSWERS:
1 (a)
13.(a)
2 (d)
14(a)
3 (d)
15(d)
4
16(b)
5 (a)
6 (d)
7 (a)
8 (b)
9 (b)
10
11
12 (a)
UNIT V: Programmable Logic Devices, Threshold Logic

1. The PROM consists of
(a) Programmable OR , fixed AND gates
(c) Programmable AND , fixed O R gates
2.
[ ]
(b) fixed OR and AND gates
(d) Programmable OR and AND gates
When the power supply of a ROM is switched off , its contents ,

[ ]
( a) become all zeroes ( b ) are unpredictable ( c ) becomes all ones ( d ) remain intact

Page 80
3. A ROM has 16 address lines and 8 data lines . It is organized as

( a) 6 4K 8
( b ) 1 28 K 4
( c ) 6 4K 1 6
[ ]
( d ) 3 2K 1 6
4. A switching function Y can be decomposed into two threshold functions f 1 and f 2 . The function Y can
be implemented using
[ ]
( a) 2 threshold elements interconnected to perform NAND operations
( b ) 2 threshold elements interconnected to perform OR operations
( c ) 2 threshold elements interconnected to perform NOR operations
( d ) 1 threshold element
5. The parameters of a threshold element are
( a) weights as signed to input variables and T
( c ) weights as signed to input variables
6. The Decoder has
( a) fixed OR and AND gates
( c ) Programmable OR and AND gates
7. A PLA is a
( a) Field programmable
( c ) Can be erased and programmed
[ ]
( b ) neither input , nor output variables nor T values
( d ) value of T
[ ]
( b )Programmable OR ,fixed AND gates
( d ) Programmable AND,fixed OR gates
[ ]
( b ) Can be programmed by user

( d ) Mask programmable
8. Four RAM chips of 164 size have their busses connected together .This system will be of size
( a) 256 1
( b ) 16 4
( c ) 1 6 1 6
( d ) 32 8
[ ]
9. The parameters of a threshold element are
( a) output variables
( c ) weights assigned to input variables
10. A threshold function
( a) is not a unite function
( c ) may be a unite function
[ ]
( b ) value of T
( d ) weights assigned to input variables and T
[ ]
( b ) is always a unite function

( d ) may or may not be a unite function
11. The Decoder has

[ ]
( a) fixed OR and AND gates
( b ) Programmable OR, fixed AND gates
( c ) Programmable OR and AND gates
( d ) Programmable AND, fixed OR gates
12. The ROM programmed during manufacturing process itself is called
[]
a)MROM
(b) PROM
(c) EPROM
(d) EEPROM
13. A memory in which the contents get erasedwhen power failure occurs is [ ]
a)EAROM
(b) PROM
(c) ROM
(d) RAM
14. The ROM programmed during manufacturing process itself is called [ ]

A) MROM
B) PROM
C) EPROM
D) EEPROM
15 The data bus width of a ROM of size 2048 x 8 bits is [ ]
A) 8
B) 10
C) 12
D) 16
ANSWERS:
l (a)
2 (d)
3 (a)
4 (b)
12.(a)
13.(d)
14.(a)
15(a)
5 (a)
6 (a)
7 (d)
9 (d)
10 (d)
11 (a)

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UNIT VI: SEQUENTIAL CIRCUITS I

1 .Race around condition occurs in JK Flip - Flops when
[ ]
( b )the inputs are complementary
( d ) both the inputs are 1
( a) One of the input combinations (0, 1) is present

( c ) both the inputs are 0
2. If t set up =set up time , t pd = propagation delay time ,t n s =next state decoder delay, then maximum
frequenc y of edge triggered flip flop is
[ ]
( a) 1 /( t s e t u p + t n s )
( b ) 1 /( t p d + t n s )
( c ) 1 /( t s e t u p + t n s + t p d )
( d ) 1 /( t s e t u p + t p d )
3. Which of the following input combinations is not used in a RS flip flop ?
( a) S = 0 , R = 1 ( b ) S = 0 , R = 0 ( c ) S = 1 , R = 1 ( d ) S = 1 , R = 0
[ ]
4. A sequential circuit with m flip flops and n inputs needs rows in the state table
( a) 2 m -n -1 ( b ) 2 m ( c ) 2 m + n ( d ) 2 n
[ ]
5. A johnson counter is also called as
( a) Inverse counter
( b ) Inverse feedback counter
( c ) Direct counter
( d ) Direct feedback counter
6 . Race around condition occurs in JK Flip - Flops when
( a) One of the input combinations ( 0 , 1) is present
( c ) both the inputs are 0
[ ]
[ ]
( b ) the inputs are complementary
( d ) both the inputs are 1
7. The flip flops used in shift registers are

( a) R S ( b ) T ( c ) D ( d ) J K
[ ]
8. A counter that does not use any additional logic gate is

( a) Pre settable counter ( b ) Johnson counter ( c ) Ring counter ( d ) Up counter
9. A single literal term in SOP expression
[ ]
[ ]
a)Requires an inverter for PLA implementation b)Requires an AND gate for PLA implementation
c)Doesnt requires an AND gate for PLA implementation
d) Doesnt requires an inverterfor PLA implementation
10. When an inverter is placed between the inputs of anS R flip flop, the resulting flip flop is a [ ]
a)J - K flip - flop (b) Master slave flip - flop c)T flip - flop (d) D flip - flop
11. Flip flops can be used to make
a)Latches
[]
(b) Bounce elimination switches
c) Registers
(d) All of the above
12. A combinational PLD with a programmable AND array and a programmable OR array is [
A) PLD
B) PROM
C) PAL
D) PLA
13. Which of the following flip flop is used as a latch? [ ]

A) J-K flip flop B) Master-slave flip flop C) T flip flop D) D flip flop
ANSWERS
1(d)
5 (b)
9.(b)
10.(d)
11.(c)
12(d)
13(d)
6 (d)
8 (a)

Page 82

1. The number of directed arc semanating from any state in a state diagram is
[ ]
( a) an arbitrary number
( b ) 2n where n is number of Flip - Flops in the circuit
( c ) independent of the number of inputs ( d ) 2n ,where n is the number of inputs
2. While constructing a state diagram of a sequential circuit from the set of given statements
[ ]
( a) redundant states must be avoided
( b ) minimum number of states must only be used
( c ) Only input states must be used
( d ) redundant states must be used
3. For a 8 state machine if P4 = ( A ) ( B ) ( C D ) ( E FG ) (H ) then its P3 partition may be
( a) ( A B ) ( C D ) ( E F ) (G H )
( b ) ( C D ) ( A ) ( B ) ( E FG ) (H )
( c ) ( A B C ) (D E F ) (G H )
( d ) ( A B ) ( C D ) ( E H ) (FG )
4. The example of a Mealy machine is
( a) Serial Adder ( b ) Binary Counter ( c ) Half adder ( d ) Sequence detector
[ ]
[ ]
5. Distinguishing sequence for states A and F Present State Next State X = 0 Output X = 1 A E , 0 C , 0
B C,0 A,0 C B,0 B,0 D G,0 A,0 E F,1 B,0 F E,0 D,0 G D,0 G,0
( a) 0 00 ( b ) 0 10 0 ( c ) 0 11 10 ( d ) 1 01 1
6. The example of a Mealy machine is
( a)Half adder ( b ) Serial Adder ( c ) Binary Counter ( d ) Sequence detector
[ ]
7. The output of a clocked sequential circuit is independent of the input. The circuit can be represented by
[]
a)Mealy model (b) Moore model c)Either Mealy or Moore model (d) Neither Mealy or Moore model
8. For designing a finite state machine k maps can be used for minimizing the
[]
a)Excitation expressions of flip - flops
(b) Number of flip flops
c)Output logic expressions
(d) Excitation and output logic expressions
9. An algorithmic state machine is the same as
A) synchronous sequential circuit B) clocked sequential circuit

C) finite state machine
D) all of the above
10. Moore type of outputs are
A) independent of inputs B) dependent only on the inputs
C) dependent on present state and inputs D) dependent on hardware used for implementation
ANSWERS:
l (d)
2 (d)
3 (b)
4 (b)
5 (d)
6 (c)
7.(b)
8.(d)
9.(d)
10.(a)
UNIT-VIII: Algorithmic State Machines

1. An Algorithmic State machine is same as
( a) clocked sequential circuit ( b ) synchronous clocked sequential finite state machine
( c ) finite state machine
( d ) synchronous sequential circuit
2.
[ ]
An asm chart of the mealy model

[ ]
( a) contains only state and decision boxes

Page 83
( b )doesnot contain conditional output box

( c ) outputs are represented by writing output state variable inside state box
( d ) contains conditional output box
3. Which of the following is true
[ ]
( a) A partition P is said to be a refi nement of partition Q if P is 5
( b ) A partition P is said to be a refinement of partition Q if P is greater than Q
( c ) A partition P is said to be a refinement of partition Q i f P i s 190
( d ) A partition P is said to be a refinement of partition Q if P is smaller than Q
4. A program table is used for
( a) Merger table ( b ) A S M ( c ) P L A s ( d ) Partition tables
[ ]
5. In ASM chart Mealy type of outputs

( a) can be represented by writing output state variables inside state box
( b ) can be represented inside decision boxes
( c ) can be represented by conditional output boxes
( d ) cannot be represented
[ ]
6. While constructing a state diagram of sequential circuit from the set of given statements [ ]
a)A minimum number of states must only be used b)Redundant states may be used
c)Redundant states must be avoided
d)None of the above
7. An ASM chart consists of
[]
a)Only state boxes
(b) only decision boxes
c)Only decision and conditional output boxes
(d) All the above.
8. Moore type outputs are
[]
a)Independent of the inputs
b)Dependent only on the inputs
c)Dependent on present state and inputs
d)Any one of the above
9. A synchronous sequential circuit can be described by [ ]
A)a state diagram
B) a state table
C) an ASM chart
D) any one of the above
10 A state box in an ASM chart [
]
A) is included only in one ASM block
B) is not included in any ASM block
C) may be included in any no. of ASM blocks
D) may be shared by two ASM blocks
ANSWERS
1 (b)
2 (d)
3 (b)
4 (c)
5 (a)
6 (b)
7 (d)
8 (a)
9.(d)
10.(a)

Page 84
ESSAY TYPE
QUESTIONS
ESSAY Questions

1. Convert the following numbers:
i. (6753)8 to base 10
ii. (00111101.0101)2 to base 8 and base 4
iii. (95.75)10 to base 2.
2. Represent +65 and -65 in sign-magnitude, sign-1s complement and sign-2s
Complement representation
3. Given a = 10101001 and b = 1101 find:
i. a + b
ii. a - b
iii. a . b
iv. a / b
4. Encode the decimal number 365 in:
i. Binary
ii. BCD
iii. ASCII
5. Convert the following to Decimal and then to Octal.
(a) 123416
(b) 12EF16
(c) 101100112
(d) 100011112
(e) 35210
(f) 99910
6. Convert the following to Decimal and then to Binary.
(a) 101116
(b) ABCD16
(c) 72348
(d) 77668
(e) 12810
(f) 72010
7. i. Convert (1596.675)10 to hexadecimal
ii. Convert (11110.1011)2 to decimal
iii. Convert (10110001.01101001)2 to octal
iv. Convert (235.0657)8 to Binary
8. Obtain the 1's complement and 2's complement of the binary numbers
i. 1011011
ii. 0110101
iii. 10110
iv. 00110
9. a)Convert the number (17.125)16to base 10, base 4, base 5 and base 2.
b) Perform the binary arithmetic operations on (-14)-(-2) using signed 2's complement
representation.
c) Justify the statement that Gray code is a class of reflected code.

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ESSAY Questions
10. a) Convert the following to the required form.

i) (A98B)12= (---------)3ii) (38.65)10= (-----------)2.
b) Use 2s complement form perform subtraction.
i) 1101010-110100 ii) 10011.1101-101.11
11. a)Develop a Gray code for (42)10and (97)10and convert the same to Hex sequence.
b) Explain different error detecting and correcting codes in digital system.
12. a)Convert the number (234)10 to base 16, base 8 and base 2.
b) find the Canonical POS form of F= YZ + XY +XYZ
c) find the sum of -8+2 in 2s complement form

1. Prove the following:
i. XYZ + XYZ + XYZ + XYZ +XYZ = YZ + XY +XYZ
ii. XY + YZ = XYZ + XYZ +XYZ
2. Define the following with an example
i. Canonical form
ii. Standard form
iii. Minterm
iv. Maxterm
3. Draw the truth table and write Boolean expression for the following:
i. F is a 1 only if X is a 1 and Y is a 1 or if X is 0 and Y is a 0.
ii. G is a 0 if any of the three variables X, Y and Z are 1s. G is a 1 for all
other conditions.
4. Write short notes on Universal gates
5. For the given function find the min term designation and max term designation
F = A'BC + ABC' + ABC + A'B'C
6. Write the Min terms and Max terms for the following functions
F1= (1,4,6,7,9)
F2 = (3,5,7,11,14)
7. What are Logic Gates? How do the Gates differ from Logic operators? Explain
Positive Logic and negative logic. Explain each term with examples.
8. Define the function of the following gates with the help of circuit diagram of
each with an output connected to an LED. Give the truth table and symbols for
each.
i. AND gate
ii. OR gate
iii. XOR gate
iv. NAND gate
9. State and prove the following Boolean laws:
i. Commutative
ii. Associative
i. Distributive.

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ESSAY Questions
10. Prove that NAND and NOR gates are Universal gate
11. a)State and Prove the Huntington postulates of Boolean Algebra.
b)Find the complement of the function and represent in sum of minterms
F(x,y,z) = xy + z'
12. Simplify the following function and realize using universal gates
F(A,B,C) = A'BC' + ABC + B'C' + A'B'
13. (a) Prove the following entity : XY + YZ = XYZ + XYZ +XYZ
(b)simplify the given function to minimum number of literals.
F=(1,2,3,4,6,7)

1. Reduce the following function using K- map and implement it in AOI logic as
well as NOR logic F= M(0, 1, 2, 3, 4, 7)
2. What do you mean by K-map? Name its advantages and disadvantages
3. For the truth table given below , find the minimal expression for the out put
(Y) using K-map
Inputs
A
B
Output(Y)
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
4. Expand A + B C + ABD + ABCD to minterms and maxterms.

5. Reduce the following function using K- map and implement it using NAND

Page 88
ESSAY Questions
logic. F= m(0, 2, 3, 4, 5, 6, )
6. What do you mean by dont care combinations?
7. What you mean by min terms and max terms of Boolean expressions.
8. Simplify the Boolean function using K-map F= m(0, 1, 3, 4, 5, 6, 7, 8, 9) +
d(10, 11, 12, 13, 14, 15)
9. Prove that if w'x + yz' = 0, then wx + y'(w' + z') = wx + xz + x'z' + w'y'z.
10. For the given function T(w,x,y,z) = (0,1,2,3,4,6,7,8,9,11,15)
i) Show the map
ii) Find all prime implicants and indicate which are essential.
iii) Find a minimal expression for T and realize using basic gates. Is it unique?
11 Simplify the following function using K-map.
F(A,B,C,D) = (1,3,4,5,6,11,13,14,15)
Simplify the following using Tabular method.
F(A,B,C,D) = (3,7,8,12,13,15)+ d (9,14)
12. For the given function T(w,x,y,z) = (0,1,2,3,4,6,7,8,9,11,15)
i) Show the map
ii) Find all prime implicants and indicate which are essential.
iii) Find a minimal expression for T and realize using basic gates. Is it unique?
13. Design a 16x1 mux using 4x1 mux

1. Explain the type of Hazard if any in the EXCLUSIVE - OR circuit made by five NAND gates
and the EXCLUSIVE ?OR circuit made by four NAND gates as shown in figure.
2. Implement the following multiple output combinational logic using a 4 line to 16 line Decoder.
Y1 = A C + A CD + A C + ABC + A C + A CD
Y2 = A CD + AB C + AB CD + AB CD
Y3 = ABCD + ABC + ABCD
3. A combinational circuit is defined by the following three functions F1 = xy +
xyz F2 =x + y F3 =xy + xy Design the circuit with a decoder and external gates.
4. List the applications of Multiplexer and Demultiplexer.
5. Construct a combinational logic circuit which converts a decimal number into an
equivalent Excess -3 number. Implement the same using
(a) Multiplexer
(b) Decoder
6. Design a Logic circuit which accepts two 5 bit binary numbers. The circuit should perform
binary addition when the carry in is 0 and should perform binary subtraction using 2's
complement addition when the input carry is 1

Page 89
ESSAY Questions
7. a)Design a 64:1 MUX using 8:1 MUXs.

b)Design a 4 bit parallel adder using Full adder modules.
8. Design a 2-bit comparator which compares the magnitude of two numbers X andY and
generates three output f1,f2, and f3.
9. Realize 16 1 Mux using only 2 1 Mux.
10. Simplify the following using Tabular method.
F(A,B,C,D) = (1,5,6,12,13,14)+ d (2,4)

1. Derive the PLA programming table for the combinational circuit that squares a 3 bit number.
2. For the given 3-input, 4-output truth table of a combinations circuit, tabulate the PAL
programming table for the circuit
3. Write short notes on Integrated circuits. Classify the ICs based on the levels of integration.
Discuss on PLDS. What are the different types of programmable devices?
4. Implement the following functions using PAL and PLA
F1 = m(2,3,4,7,8,11)
F2 = m(1,3,5,7,9,11,13,15)
5. Tabulate the PLA programming table for the four Boolean functions. Minimize the following.
(a) F1 (A, B, C) = m (1, 2, 5, 6)
(b) F2 (A, B, C) = m (0, 1, 4, 7)
(c) F3 (A, B, C) = m (2,6,8)
(d) F4 (A, B, C) = m (1,2,3,5,7)
6. What is PAL? How does it differ from PROM and PLA?
7. Design a switching circuit that converts a 4 bit binary code into a 4 bit Gray code using ROM
array.
8. a) Design a square generator logic for 4 bit input using ROM.
b) What are the capabilities and limitations of threshold gate?
9.(a)define static hazard.illustrate with example
(b)design a combinational circuit that convert a given binary code to excess-3 code

Page 90
ESSAY Questions

Compare synchronous & Asynchronous circuits
2. Design a Mod-6 synchronous counter using J-K flip flops
3. Design a sequence detector which detects 110010 Implement the sequence
detector by using D - type flipflops
4. Classify the required circuits into synchronous, asynchronous, clockmode, pulse mode with
suitable examples
5. Find a modulo-6 gray code using k-Map & design the corresponding counter
6. Compare synchronous & Asynchronous.
7. Compare synchronous & Asynchronous.
8. Write the conversion procedures of the ip ops. Convert T flipflop to JK
flipflop.
(a)Convert SR ip op to T flipflop
(b) Convert D flipflop to T flipflop.
9. Design a 4-bit Bidirectional Shift Register.
10. .a) Convert RS flip flop to a
i) D-latch ii) T-latch.
b) Design a FSM which detects 0011 patternand set z = 1 for all other patterns z = 0
11. a) What is meant by clock skew? How to handle it?
b) Explain the term Race around condition.How is it satisfied by Master-slave Flip-Flops.
11. 12. a) Convert RS flip flop to a
i) D-latch ii) T-latch.
b) Design a FSM which detects 0011 patternand set z = 1 for all other patterns z = 0
1.
UNIT- VII: Sequential Circuits II

1. Determine the equivalence classes for the given state - table.
2. Obtain final transition table.

Page 91
ESSAY Questions
3. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed
(a) Obtain State - Diagram.
(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D flipflops.
4. Construct the compatibility graph and obtain the minimal cover table for the sequential
machine described by the state table given
5. The state table of a sequential machine is shown below. Obtain the compatibility
graph using.
(a) Merger graph
(b) Merger Table
6. a) Design a modulo 10 counter JK flipflops.

b) What are the rules to develop a Merger chart?
7. Construct the state diagram and primitive flow table for an asynchronous machine that
has two inputs and one output. The input sequence xy = 00, 01, 10 causes the output to
become 1. The next input change then causes the output to return to 0. No other inputs
will produce a 1 output.
8. Write the usage of merger graph with example.
9. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed
(a) Obtain State - Diagram.
(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D flipflops.

Page 92
ESSAY Questions

1. (a) For the given ASM chart obtain its equivalent state diagram 8.
(b) Design the circuit using mulitiplexes.
2.(a) Draw the state diagram.

(b) Design the control unit using D flip-flops and a decoder.

Page 93
ESSAY Questions
3. Draw the ASM chart for the following state transistion, start from the initial
state T1, then if xy=00 go to T2, if xy=01 go to T3, if xy=10 go to T1, other
wise go to T3.
4. Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state.
5.Draw an ASM chart to convert D-Flip op to T flip flop
6. Give the procedure to design a data processing unit and a control unit
of bits in a register that have a value 1
8. Discuss the procedure to implement an ASM chart using Multiplexer.
9. Design a binary multiplier and its control logic by drawing ASM chart and realize the same using
decoder, MUX and D flipflops
10. Design a control logic through ASM Chart for the sequence detector which detects 1100 and resets
flip flop F to 0 and flip flop E to 1. The patterns come from 4 bit counter A.
of bits in a register that have a value 1

Page 94
ASSIGNMENT
QUESTIONS
1.
2.
3.
4.
5.
6.
7.
8.
Construct an even parity seven bit code to transmit the data 1101.
Find the 10th element in the base 3 number system.
Perform the subtraction with the following unsigned binary numbers by taking the
2s complement of the subtrahend.
(a) 10010 10000
(b) 11010 1000
(c) 1101 110000
(d) 1001100 1011100.
Give a brief description about the following number systems with suitable
examples.
i. Decimal number system
ii. Binary number system
iii. Octal number system
iv. Hexadecimal system.
i. Convert (2598.675)10 to hexadecimal
ii. Convert (10010.1011)2 to decimal
iii. Convert (10111101.01101001)2 to octal
iv. Convert (465.0647)8 to Binary.
Explain the complement representation of negative numbers with examples.
Obtain the 1s complement and 2s complement of the following binary numbers.
i. 1010111
ii. 0111001
iii. 1001
iv. 00010

1. Simplify the following Boolean expressions to minimum no. of literals.
i. ABC+AB+ABC
ii. (BC+AD)(AB+CD)
iii. xyz+xz
iv. xy+x(wz+wz)
2. Obtain the Dual of the following Boolean expressions.
i. AB+A(B+C)+B(B+D)
ii. A+B+ABC
iii. AB+ABC+ABCD+ABCDE
iv. ABEF+ABEF+ABEF
3. Express the following functions in sum of minterms and product of maxterms.
i.(xy+z) (y+xz)

Page 96
ii. BD+AD+BD
4. Obtain the complement of the following Boolean expressions.
i. ABC+ABD+AB
ii. ABC+ABC?+ABCD
iii. ABCD+ABCD+ABCD
iv. AB+ABC
5. Simplify the following Boolean expressions.
i. AC+ABC+AC to three literals
ii. (xy+z)+z+xy+wz to three literals
iii. AB(D+CD)+B(A+ACD) to one literal
iv. (A+C)(A+C)(A+B+CD) to four literals
6. Obtain the complement of the following Boolean expressions.
i. BCD+(B+C+D)+BCDE
ii. AB+(AC)+(AB+C)
iii. ABC+A?BC+ABC+ABC
iv. AB+(AC)+ABC
7. Implement Y = AB+CD + (AB+CD) using NAND gates
8. Verify the following Boolean algebraic expression. Justify each step with a
reference to a theorem or postulate.
(AB +C +D) (C +D) (C +D +E) = ABC + D
UNIT III : Minimization Of Switching Functions

1. Determine the canonical Product of sum form for the function and simplify using
k-map
(a) Y(x,y,z) = x(y'+z)
(b) Y(a,b,c) = ab' + bc
(c) Y(w,x,y,z) = wxy' + x(y'+z)
(d) Y(a,b,c) = (ab + c')(ac + b')
2. Minimize the following Boolean function using K-map F = (2, 7, 8, 9, 10, 12).
3. Design a combinational logic circuit with 4 inputs A, B, C, D. The output Y goes
HIGH if and only if B and C inputs go HIGH. Draw the Truth table. Minimize
the Boolean function using K-map. Draw the circuit diagram.
4. Simplify the following Boolean function using Tabulation method.
Y(A,B,C,D) = _(2,3,5,7,8,10,12,13)
5. What are the advantages of Tabulation method over K-map?
6. Simplify the following Boolean expressions using K-map and implement them
using NOR gates:
(a) F (A, B, C, D) = ABC + AC + ACD
(b) F (W, X, Y, Z) = WXYZ + WXYZ + WXYZ + WXYZ.
7. List the Boolean function simplification rules using Tabulation method.
8. Simplify the following Boolean expression using K-map and implement using
NAND gates.
F(W,X,Y,Z) = XZ + WXY + WXY + WYZ + WYZ

Page 97

1. Design a full adder circuit using 2 half adders.
2. Design a 4 bit Parallel adder using full adders.
3. Design a 3 bit Parallel parity-bit generator. This circuit must produce an output 1
if
and only if an odd number of inputs have value 1.
4. Design a 2-bit comparator using NAND gates.
5. Realize the function F(A,B,C,D) = (1,4,6,10,14) +d(0,8,11,15) using
(a) 16:1 Mux
(b) 8:1 Mux
(c) 4:1 Mux.
6. Implement the following functions using appropriate DECODER
F1 = m(2,4,6,8,12)
F2 = m(1,3,6,7,9,10)
F3 = m(1,3,4,5,6,9,12,14)
F4 = m(2,4,8)
7. What is decoder? Construct 3*8 decoder using logic gates and truth table.
8. What is Encoder? Design Octal to Binary Encoder.

1. Implement the Boolean functions F1 and F2 of a combinational logic circuit using
PLA.
F1(X, Y, Z) = m (1,2,3,5,7)
F2(X, Y, Z) = m (0,3,5,7)
Write the PLA program table and draw the internal connections to implement the
functions.
2. Design excess-3 to BCD converter using
(a) ROM
(b) PAL.
3. Implement the following functions using PROM
F1 = m(0,2,5,7,8,9,10,12)
F2 = m(1,2,3,4,6,7,8,11,13,15)
4. Design an arithmetic circuit that adds 2 binary digits. The circuit should have 2
outputs, one for the sum and the other for the carry. Implement the same in a
PAL.
5. Implement the following boolean functions using PLA.
f1(w,x,y,z) = (0,1,3,5,9,13)
f2 (w,x,y,z) = (0,2,4,5,7,9,11,15).
6. Write short notes on PLDS
7. Implement the following functions using PLA
x1(P,Q,R) (0,1,2,7)
x2(p,Q,R) = (1,4,5,6).

Page 98
8. Derive a PLA programming table for the combinational circuit that squares a 3 bit
number.
9. For a given 3-input, 4-output truth table of a combinations circuit, tabulate the
PAL programming table for the circuit

1. Discuss the disadvantages due to level triggering. Explain the effects of level
triggering in a JK flip flop.
2. Design a clocked D flip flop. Explain its operation with the help of characteristic
table and characteristic equation. Give the symbol of edge triggered D flip flop.
3. Design a Parallel in Parallel out Shift Register.
4. Convert T flip flop to D flip flop.
5. Design a JK flip flop using AND gates and NOR gates. Explain the operation of
the JK flip flop with the help of characteristic table and characteristic equation.
Explain the Race around condition.
6. What is the advantage of choosing D-flipflops in sequential circuits. Explain with
an example.
7. Show that the characteristic equation for the complement out put of a JK
flipflop is
Q (t + 1) = J Q + kQ
UNIT- VII: Sequential Circuits II

1. Design a Serial in and parallel out Shift Register.
2. Design a 8-bit Ring counter.
3. Find the equivalence partition for the machine shown below.
Show a standard form of the corresponding reduced machine.

Page 99
4. For the machine shown, find the equivalent partition and a corresponding reduced
machine in standard form.
5. Explain the following related to sequential circuits with suitable examples.

(a) State diagram
(b) State table
(c) State assignment
6. Draw the logic diagram of a 4 bit binary ripple counter using positive edge
Triggering.
7. Draw the block diagram of a 4 - bit serial adder and explain its operation
8. Explain merger chart methods of minimal convertable.
UNIT-VIII: Algorithmic State Machines

1. Draw the State diagram of a sequence detector which is designed to detect the
pattern 1001 and allowing the overlapping in the input sequence. Draw the ASM
chart for the state diagram. Explain the sequence of operations of each block.
Also design the Data path circuit and control circuit.
2. Design a sequential logic circuit of a 4 bit counter to start counting from 0000 to
1000 and this process should go on. Draw the ASM chart and design the Data
processing unit and the control unit.
3. Design the ASM chart, Data path circuit, Control circuit using multiplexers for
Binary multiplier.
4. Design a synchronous sequential circuit which goes through the following states.

Page 100
1,3,5,3,6,1,3,5.......
Design the ASM chart to implement the above mentioned design. Design the
control unit using PLA control.
5. For the given control state diagram, draw the equivalent ASM chart as shown
in figure
6. For the given state diagram, as shown in figure 8a obtain its ASM chart
****THE END***

Page 101
ELECTRONIC CIRCUIT
analysis
Mrs.P.A.Harshavardhini
Assoc.professor
&
Mr. n.HATHIRAM
Asst. Professor
COURSEFILE
Department of

Sponsored by
COURSE
OBJECTIVE
Electronic circuit analysis
Course Objective
COURSE OBJECTIVE
The course provides a comprehensive understanding of the basic theory of Some practical
knowledge about the design and analysis of basic analog Circuits. Find out how bipolar transistors
really work in circuits. Learn how to design, analyze, and test basic amplifiers. Learn about differential
pairs, current sources and multi-stage amplifier design. Learn how to design, analyze and test multistage amplifiers. Learn about feedback as it applies to amplifiers.
Learn about BJT operation BJT DC Analysis and DC Load Lines, BJT small-signal model hybrid pi looking in each terminal.
Overview of Single-Stage, double stage BJT Amplifiers. To begin estimating frequency
responses of BJT amplifiers by learning about The junction capacitances of BJTs and their effects on
frequency response. The diffusion capacitance of BJTs and its effect on frequency response. A
frequency dependent and more complete Hybrid-p model.
The basics current source circuits. The limitations of common current sources. Design and use
of current sources in multi-stage amplifiers. The basics of feedback. The properties of negative
feedback. The basic feedback topologies. An example of the ideal feedback case. Some realistic
circuit examples and how to analyze them.

Page 104
Syllabus
Syllabus
SYLLABUS
UNIT-1: Single Stage Amplifiers
Classification of amplifiers-Distortion in amplifiers, Analysis of CE, CC and CB Configurations with
simplified Hybrid Model, Analysis of CE amplifier with emitter follower, millers theorem and its dual,
Design of single RC Coupled amplifier BJT.
UNIT-2: Multi Stage Amplifiers
Analysis of Cascaded RC Coupled BJT amplifiers, Cascode amplifier, Darlingtonpair, Different
coupling Schemes used in amplifiers-RC Coupled amplifier, Transformer Coupled amplifier, Direct
Coupled amplifier.
UNIT-3: BJT Amplifiers- Frequency Response
Logarithms, Decibels, General frequency considerations, Frequency response of BJT Amplifier,
Analysis at Low and High frequencies, Effect of coupling and bypass Capacitors, and The Hybrid pi
(?)-Common emitter transistor model, CE Short circuit Gain, Current Gain with resistive Load, Single
stage CE Transistor Amplifier Response, Gain-Bandwidth Product, Emitter follower at higher
frequencies.
UNIT-4: MOS Amplifiers
Basic concepts, MOS Small Signal model, common source amplifier with Resistive load; Diode
connected Load and Current Source Load, Source follower, Common Gate stage Cascode and Folded
Cascode amplifier and their frequency response
UNIT-5: Feedback Amplifiers
Concepts of Feedback, Classification of Feedback amplifiers, General characteristics of Negative
Feedback Amplifiers, effect of Feedback an amplifier characteristics, Voltage series, Voltage shunt,
Current series and Current shunt feedback configurations , Illustrative problems.
UNIT-6: Oscillators
Classification of Oscillators, Condition for Oscillations, RC Phase shift Oscillators-Hartley, and
Colpitts Oscillators, Wien-Bridge& Crystal Oscillators, Stability of Oscillators.
UNIT-7:Large Signal Amplifiers
Classification, Class A large signal Amplifiers, Transformer Coupled class A Audio power amplifier,
Efficiency of Class A Amplifier, Class B Amplifier, Efficiency of class B amplifier, class-B Push-pull

Page 106
Syllabus
Amplifier, Complementary symmetry class B Push- Pull Amplifier, Distortion in power amplifiers
,Thermal stability and Heat Sinks.
UNIT-8: Tuned Amplifiers
Introduction, Q-Factor, Small Signal Tuned amplifiers, Effect of Cascading Single Turned amplifiers
on bandwidth, Effect of Cascading Double Tuned amplifiers on bandwidth, Stagger tuned amplifiers,
Stability of tuned Amplifiers.
TEXT BOOKS
1. Integrated Electronics J.Millman and C.C.Halkias, Tata McGraw Hill.
2. Electronic Devices and Circuits S.Salivahanan.N.Suresh kumar,A.Vallavaraj.2ed.,2009,TMH
3. Design of analog CMOS integrated circuits-Behzad Razavi,2008,TMH
REFERENCES:
1. Electronic Devices and Circuits Theory Robert L. Boylestad and Louis Nashelsky,
Pearson/Prentice Hall,9th Edition,2006.
2. Micro Electronic Circuits Sedra A.S. and K.C. Smith, Oxford University Press, 5th ed.
Micro Electronic Circuits: Analysis and Design M.H. Rashid, Thomson PWS Publ., 1999.
3.
Electronic circuit analysis-K.Lal kishore,2004,BSP
4.
Electronic Devices and Circuits,David A.Bell-5ed,oxford university press.
WEBSITES
1. http://www.onsemi.com/
2. http://www.kpsec.freeuk.com/symbol.htm
3. http://buildinggadgets.com/index_circuitlinks.htm
4. http://www.guidecircuit.com/
JOURNALS
1. IEEE Transaction on Electronic Devices (ISSN: 0018-9383)
2. Journal of Active and Passive Electronic Devices (ISSN: 1555-0281)
3. International Journal of Micro and Nano Electronics, Circuits and Systems (ISSN: 0975-4768)
4. Active and Passive Electronic Components (ISSN: 0882-7516)
5. Journal of Electronic Testing (ISSN: 0923-8174)

Page 107
STUDENT'S
SEMINAR
TOPICS
Seminar Topics

1. Analysis of CE, CC and CB Configurations with simplified Hybrid Model
2. Analysis of Cascaded RC Coupled BJT amplifiers Need for biasing
3.
Darlington pair
4. Analysis at Low and High frequencies, Effect of coupling and bypass Capacitors
5. Diode connected Load and Current Source Load
6. General characteristics of Negative Feedback Amplifiers
7. Current series and Current shunt feedback configurations
8. RC Phase shift Oscillators
9. Complementary symmetry class B Push- Pull Amplifier
10. Efficiency of Class A Amplifier, Class B Amplifier
11. Effect of Cascading Single Turned amplifiers on bandwidth
12. Effect of Cascading Double Tuned amplifiers on bandwidth

Page 109
LECTURE PLAN
Lecture Plan
LECTURE PLAN
No of
Method of
Period
Teaching
s
UNIT-1: SINGLE STAGE AMPLIFIERS
S.No
NAME OF THE TOPIC
Text books referred
---
Introduction
Introduction to ECA
Review of BJT circuit analysis
Analysis of the small signal low frequency BJT

amplifiers for voltage gain, current gain, input and output
impedance.
Black board,
Chalk and
LCD Projector
Integrated Electronics J.Millman and

C.C.Halkias, Tata McGraw Hill.
Analysis of BJT amplifiers for band width calculations
Black board
and Chalk

Analysis of the small signal low frequency FET

amplifiers for voltage gain, input and output impedance.
Black board
and Chalk

Analysis of FET amplifiers for band width calculations
Black board
and Chalk

Millers Theorem and its significance in amplifier circuit

analysis
Black board
and Chalk

Revision class on Unit -1
Black board
and Chalk

Black board
and Chalk
Black board
and Chalk
--Integrated Electronics J.Millman and

UNIT-2: MULTI STAGE AMPLIFIERS

10
Basic structure of Multi Stage Amplifier and need for

Multi Stage Amplifier.
11
Different types of coupling methods used in multi stage

amplifiers.
Black board
and Chalk
Black board,
Chalk and
LCD Projector


Page 111
12
13
14
15
16
Lecture Plan
Analysis of BJT multi stage amplifiers CC-CC, two

stage RC coupled amplifier.
Analysis of BJT multi stage amplifiers CE-CC
amplifier.
Analysis of JFET multi stage amplifiers CD-CS and two
stageRC coupled amplifier.
Analysis of JFET multi stage amplifiers CD-CG
amplifier.
Revision class on Unit-2
1
1
1
1
1
Black board
and Chalk
Black board
and Chalk
Black board
and Chalk
Black board
and Chalk
Black board
and Chalk

C.C.Halkias, Tata Integrated Electronics
J.Millman and C.C.Halkias, Tata McGraw Hill.
UNIT-3: BJT AMPLIFIERS- FREQUENCY RESPONSE
18
Logarithms, Decibels General frequency

considerations BJT high frequency hybrid PI model
and its importance.
Frequency response of BJT Amplifier Relation between
hybrid PI parameters and H parameters.
19
Analysis at Low and High frequencies
17
Black board
and Chalk

Black board
and Chalk

Black board
and Chalk
Black board
and Chalk

Integrated Electronics J.Millman and C.C.Halkias
21
Hybrid PI parameter variation with Ic and Vce and

Temperature Effect of coupling and bypass Capacitors
CE amplifier high frequency analysis using hybrid PI
model.
22
CE Short circuit Gain, Current Gain with resistive Load
23
Single stage CE Transistor Amplifier Response.
24
Gain-Bandwidth Product, Emitter follower at higher

frequencies.
Black board
and Chalk
25
Black board
and Chalk
20
1
1
Black board
and Chalk
Black board
and Chalk
Black board
and Chalk

UNIT-4: MOS AMPLIFIERS

26
Explain Basic concepts of MOSFET amplifiers.
Black board,
Chalk and
II B.Tech 2ndSemester
Page 112
Lecture Plan
LCD Projector
27
Explain Basic concepts and MOS Small Signal model.
28
common source amplifier with Resistive load.
29
Explain common source amplifier with Resistive load

and derive the Maximum voltage gain
30
Source follower with small signal model.
31
Common Gate stage.
32
Folded Cascode amplifier
33
Explain their frequency response
34

Black board,
Chalk and
LCD projector
Black board,
Chalk and
LCD Projector
Black board,
Chalk and
LCD Projector
Black board,
Chalk and
LCD Projector
Black board,
Chalk and
LCD Projector
Black board,
Chalk and
LCD Projector
Black board
and Chalk

UNIT-5: FEEDBACK AMPLIFIERS
36
The basic concepts of feedback, classification of

feedback amplifiers
General characteristics of Negative Feedback Amplifiers.
37
Effect of Feedback an amplifier characteristics
38
Voltage series feedback amplifiers
39
Voltage shunt feedback amplifiers and with transistor.
40
Current series feedback amplifiers and with transistor
35
1
1
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and Chalk
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and Chalk
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and Chalk
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and Chalk
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and Chalk
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and Chalk

Page 113
Lecture Plan
41
Current shunt feedback amplifiers.
42
Illustrative problems
43
Difference between positive FB and negative FB

amplifiers.
44
Classification of Oscillators and Condition for

Oscillations.
45
RC Phase shift Oscillators.
46
Wien-Bridge.
47
Hartley oscillator
48
Colpitts oscillator
49
Crystal Oscillators.
Black board
and Chalk
Black board
and Chalk
Black board
and Chalk

UNIT-6: OSCILLATORS
50
Stability of Oscillators.
51
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and Chalk
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and Chalk
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and Chalk
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and Chalk
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and Chalk
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and Chalk
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Chalk and
LCD Projector
Black board
and Chalk

UNIT-7:LARGE SIGNAL AMPLIFIERS

52
DC and AC load lines.
53
Classification power amplifiers and their operations
54
Analysis of Class A Series fed and transformer coupled

power amplifier.
55
Analysis of Inductive coupled Class A power amplifier.
56
Analysis of Class B Power amplifiers.
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and Chalk
Black board,
Chalk and
LCD Projector
Black board
and Chalk
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and Chalk
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Page 114
Lecture Plan
57
Heat sink and its design.
58
Revision class for Unit 7.
and Chalk
Black board
and Chalk
Black board
and Chalk

UNIT-8: TUNED AMPLIFIERS

59
Introduction about tuned amplifiers, resonant frequency
60
Q-Factor and problems.
61
Small Signal Tuned amplifiers.
62
63
Effect of Cascading Single Turned amplifiers on

bandwidth.
Effect of Cascading Double Tuned amplifiers on
bandwidth.
Stagger tuned amplifiers Stability of tuned Amplifiers.
65
Stability of tuned Amplifiers
66
Problems.
67
68
69
70

64
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and Chalk
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and Chalk

Notes
Notes
Notes
Notes
Page 115
LEARNING
OBJECTIVES
Learning Objective
LEARNING OBJECTIVES
UNIT I: SINGLE STAGE AMPLIFIERS
1.
2.
3.
4.
5.
6.
7.
8.
Define small signal operation of BJT

Define low frequency operation of BJT
Draw the small signal low frequency models of BJT
Derive equations for voltage gain, current gain, input and output impedance for small signal
low frequency BJT amplifiers
Derive equations for voltage gain, input and output impedance for small signal low
frequency
Explain the 3db band width of an amplifier
Derive equations for 3db band width BJT amplifiers
Explain Millers Theorem and its significance in amplifier circuit analysis
UNIT II: MULTI STAGE AMPLIFIERS

At the conclusion of this unit student will Explain the need for multi stage amplifiers.
1
2
3
Explain different types of coupling methods used in multi stage amplifiers.

Explain the procedure to make analysis of BJT multi stage amplifiers CC-CC,CE-CC
and two stage RC coupled amplifier.
Explain the procedure to make analysis of JFET multi stage amplifiers CD-CS, CD-CG and
two stage RC coupled amplifier.
Explain the procedure to make analysis of BJT difference amplifier
UNIT III: BJT AMPLIFIERS- FREQUENCY RESPONSE

1. Define Logarithms, Decibels.
2. Define high frequency and low frequency response of BJT amplifiers.
3. Explain the effect of coupling and bypass Capacitors.
4. Draw the BJT CE high frequency hybrid PI model and explain about the model parameters.
5. Explain the variation of hybrid PI parameters with Ic and Vce and Temperature.
6. Derive an equation for CE short circuit current gain.
7. Derive equations for relation between hybrid PI parameters and H parameters.
8. Derive an equation for CE current gain with load.
9. Explain Single stage CE Transistor Amplifier Response.
10. Derive equations for relation between Gain-Bandwidth Product.
11. Explain Emitter follower at higher frequencies.

Page 117
Learning Objective
UNIT IV: MOS AMPLIFIERS

1.
2.
3.
4.
5.
6.
7.
Explain Basic concepts and MOS Small Signal model.

Explain common source amplifier with Resistive load.
Explain Source follower
Explain Common Gate stage.
Explain Cascode amplifier.
Explain Folded Cascode amplifier.
Explain their frequency response.
UNIT V: FEEDBACK AMPLIFIERS

1.
2.
3.
4.
5.
6.
7.
Explain the basic concepts of feedback, classification of feedback amplifiers.

Explain General characteristics of Negative Feedback Amplifiers.
Explain effect of Feedback an amplifier characteristics.
Explain Voltage series feedback amplifiers.
Explain Voltage shunt feedback amplifiers.
Explain Current series feedback amplifiers.
Explain Current shunt feedback amplifiers.
UNIT VI: OSCILLATORS

1. Explain the difference between positive FB and negative FB amplifiers.
2. Explain the Classification of Oscillators.
3. Derive the Condition for Oscillations.
4. Condition for Bharkhausen criterion for Oscillation.
5. Derive the frequency of Oscillation for RC phase shift oscillator.
6. Explain Wien bridge oscillator.
7. Derive the frequency of Oscillation for Hartley oscillator.
8. Derive the frequency of Oscillation for colpitts oscillator.
9. Explain Crystal Oscillators.
10. Explain the Stability of Oscillators.
UNIT- VII: LARGE SIGNAL AMPLIFIERS
1. Define DC and AC load lines of the amplifiers.
2. Distinguish among Class A, B and C amplifiers.
3. Explain the operation of Class A and Class B amplifiers.
4. Derive an equation for maximum efficiency of series fed Class A power amplifier.
5. Derive an equation for maximum efficiency of transformer coupled Class A power amplifier.

Page 118
Learning Objective
6. Derive an equation for maximum efficiency of transformer coupled Class A power amplifier.
7. Explain the operation of Class B Push pull and complimentary Symmetry circuits.
8. Derive an equation for maximum efficiency of Class B power amplifier.
9. Explain the operation of Class D and Class S power amplifiers.
10. Explain the need for Heat sinks in power amplifiers. And give the design procedure for Heat
sink design.
UNIT-VIII: Tuned Amplifiers
1. Explain the frequency response characteristics of Tuned amplifiers.
2. Explain the need for Tuned amplifiers.
3. Explain the need and operation of single and double tuned amplifiers.
4. Explain the applications of Tuned amplifiers.
5. Explain the need for Stagger tuning in Tuned amplifier.
6. Explain the frequency response characteristics of Stagger Tuned amplifiers.
7. Explain how instability takes place in Tuned amplifiers.
8. Explain different methods to stabilize tuned amplifiers.

Page 119
OBJECTIVE
TYPE
QUESTIONS

UNIT I: Single stage amplifiers
1
the h parameters are called hybrid because they
a) Are mixed with other parameters.

b) Are obtained from different characteristics
c) Are defined by using open and short circuit terminations
d) Apply to circuit contained in a black box
2
the smallest of the four h-parameters of a tristor is,

a) h11 b)h12 C) h21
d) h22
Typical value of hie is

a) 1K b) 10K c) 25K d) 50K
The voltage gain of tristor amplifier is lowest in

a) CE configuration g
b) CB configuration
c) CC configuration
d) Same in all configurations
Tristor amplifier has Lowest input Impedance in

a) CB configuration
b) CE configuration
c) CC configuration r
Parameter hfe of a typical tristor is of the order of

a) 5 b) 50 c) 500 d) 2000
Parameter hie of a typical tristor is et the order of

a) 1OOK
b) 1000 c) 1O000K
d) 10OK
Parameter h of typical tristor is of the order of

a)2.5*10-6 b) 2.5*10-2 c) 2.5*10-4 d) 2.5*10-3
9.
Parameter hoe of a typical tristor is of the order of

a) 2.5 S
b) 25 S
c) 250 S
d) 2.5 mS
10 With load impedance of 4, the current gain of a typical CE amplifier stage has
magnitude of the order of
a) 0.98
b) 5
c) 50
d) 400
11 With load impedance of 4, the current gain of atypical CE amplifier stage has
Magnitude of the order of,
a)0.98 b) 5 c) 50 d) 400

Page 121
12 with load impedance of 4 , the input resistance of a typical CE amplifier stage

has magnitude of the order of
a) 10 b) 100 c) 1000 d) None

13 With source resistance Rs of 1000 , the output impedance of a typical CE amplifier Stage is
ofthe order of
a) 5OOK
[
b) 5K c) 50K
d) 50OK
14 With typical load impedance of 4K, the current gain of a typical CB amplifier stage Is of the
order of
a) 0.98
[
b) 5
c) 50
d) 500
15 With typical load resistance of 4K the voltage gain of a typical CC amplifier stage is of the
order
a) 0.99 V
[
b) 5 V
c) 20 V
d) 200 V
16 In a CE amplifier stage on introducing a resistor RE in the emitter circuit, the input Resistance
RI
a) Remain unaltered
b) Reduces
c) Increase normally
d) Increase very much
17 The current gain of tristor amplifier is lowest in

a) CB configuration
b) CE configuration
c) V CC configuration
d) same in all configurations
18 The voltage gain of tristor amplifier stage is lowest fn

a) CB configuration
b) CE configuration
c) CC configuration
d)4 Same in all configurations
19 Tristor amplifier stage which has lowest output impedance in

a) CB configuration
b) CE configuration
c) CC configuration
20 Tristor amplifier stage has highest input impedance in

a) CB configuration
b) CE configuration
c) CC configuration
Answers:
1.c
11 d
2.d
12 d
3.a
13 d
4. C
14 a
5.a
15a
6.b
16d
7.b
17a
8. C
18 c
9. B
19 c
10. C
20 c

Page 122
UNIT II: Multi stage amplifiers

1) In an R.C coupled amplifier, the reduction In voltage gain in the low frequency Range results due to,
a) Coupling capacitor Cb
b) Shunt capacitance in the input circuit

c) Shunt capacitances in the output circuit
d) Input impedance of the next stage.
2) In an R.C coupled amplifier, the low 3-dB frequency may be reduced by,
a) Reducing the value of coupling capacitor Cb
b) Increasing the value of coupling capacitor Cb
c) Reducing the total effective shunt capacitance
d) Increasing the total effective shunt capacitances.
3) In an R.C coupling amplifier, the high 3-dB frequency may be increased by,
a) Reducing the value of coupling Cb
b) Increasing the value of coupling capacitor Cb
c) Reducing the total effective shunt capacitance in the output circuit
d) Reducing the total effective shunt capacitance in the input circuit of hybrid- model
4) in single stage R.C coupled amplifier stage, the phase shift introduced in the middle frequency ls,
a) Zero b) 180 c) 270 d) 90
5) In single stage R.C coupled amplifier stage, the phase shift introduced at high 3-dB frequency ls,
a) Zero
b) 180
c) 135
d) 225
6) In an R.C coupled amplifier stage as the value of coupling capacitor C b is increased the low 3 dB
frequency
a) Remains unaltered
b) Increases
c) Decreases
d) May increase or decrease
7) In an C.E. R.C coupled amplifier stage as the value of total effective shunt capacitance Increases, the
high 3-all frequency fh.
a) Remains unaltered
b) Increases
c) Decreases
d) May increase or decrease
8) The 3dB frequency of an amplifier is one at which gain reduces to,

a) Unity
b) Zero
c) 1/2 of its midband value
d) Half of its midband value
9). One advantages of transformer coupling in transistor amplifiers is that,
a) It is simple and less expensive than other coupling methods

b) It provides excellent response
c) Low power supply may be used
d) High efficiency and high power output is obtained
10) An advantage of RC coupled amplifier is it's

Page 123
a) High efficiency
b) Economy
c) Excellent frequency response
d) Good impedance matching.
11) in an RC coupled tristor amplifier, typical value of coupling capacitor is,

a) 1000 pF
b) 0.1 F
c) 0.01 F
d) 10 F
1 2) Transformer coupling provides high efficiency because the

a) Collector voltage is stepped up
b) D.C resistance in the collector circuit is low
c) Collector voltage is stepped down
d) Flux linkages are incomplete
13) ln cascade amplifier the coupling method capable of providing highest gain is
a) RC coupling
b) D.C coupling
c) Trformer coupling
d) Inductor coupling
14) Transistor amplifier stage has highest input Impedance in

a) CB configuration
b) CE configuration
c) CC configuration
d) same in all configurations
15) In a RC coupled amplifier by pass capacitor (Cc) is used for

a) Decrease the load value
b) Increase the load value
c) Attain proper stability
d). Decrease VCE
16) In a RC coupled amplifier, coupling capacitor (CC) is used

a)To Match the next stage
b) To limit the bandwidth
c) To isolate the D.C component
d) To control the output voltage
17) The effective load for 1st stage in multistage amplifier having identical stages
a) Less than last stage
b) Equal to the last stage
c) Greater than last stage
d) None of the above
18) An amplifier having a gain of 100 gives an output of 2v then input signal
a) 200V b) 20 mV c) 50 V
d) 2 mV
Answers:
1.a
10.b
2.b
11 d
3.d
12 b
4. b
13 c
5.c
14 c
6.c
15.c
7.c
16.c
8. c
17.b
9. d
18 b
UNIT III: BJT Amplifiers- Frequency Response

1) -cut off frequency of BJT.
a) Increases with increase in base width
b) Increase with increase in emitter width
c) Increase with increase in collector width d) Increase with decrease in base width

Page 124
2) The CE short-circuit gain of a tristor
a) is a monotonically increasing function of IC

b) is a monotonically decreasing function of IC
c) increases with IC for low values of IC , reaches a minimum and then decreases with further
increase of IC
d) is not a function of IC
3) A npn transistor has f = 1MHz and o = 200. Its ft, and f are respectively.
a) 200MHz ;l 201MHZ A
b) 2000MHz ; 199MHz
c) 199MHz ; 200MHz A
d) 201MHz ; 220MHz
4) The ft of BJT ls related to Gm , C, and C as as fT = ------------------5) An npn transistor (with C = 0.3 pF) has { ft of 400 MH at a die bias of ic = 1 mA
The value of C is
a) 15 b) 30 c) 50 d) 96
6) The hybrid-pi model can be used at
a) Low frequencies only
b) High frequencies only
c) At both low and high frequencies d) In the mid frequency region only
7). Hybrid-: model is valud
a) up to fT/3 b) up to fT
c) up to 3fT
d) upto fT/2
8) fT is the frequency at which the short-circuit gain becomes

a) 1/2 b)2
c) 1/2
d) 1
9) gbe =
a) hfegm
b) hfe/gm
c) gm/ hfe
d) none
10) CE = gm/P' P
a) fT
b) ft,.
c) 2fT
d) fT/2
11) According to Giacolletto, the hybrid- parameters are independent of frequency only
when 2f*w2 /6Db
a) = 1 b) > 1 c) C< 1
d) << 1
12) gm of a tristor
a) A varies directly with VCE
b) varies inversely with VCE
c) Varies directly as (VCE)2 d) is independent of | VCE |

13) gm of a tristor is proportional to
a)1/t
b)1/t2
c)1/t
14) The base-emitter resistance rbe
d)1/c
a) is independent of T
b) is independent of Ic

Page 125
c) is directly proportional to T and inversely proportion to IC

d) is directly proportional to IC and inversely, y proportional to T
1 5) The emitter capacitance CE ls proportional to
a) Ic
c) Ic d)1/ Ic
b)1/ Ic
1 6) As vce increases
a) the effective base width increases
b) the. Effective base width. decreases
c) because of (a) CE decreases with increasing VCE
d) because of (b) CC decreases with increasing VCE
17) The collector capacitance
b) is proportional to (VCE) n
a) depends on VCE
c) Decreases with increase in VCE
d) all the above
18) With increase ln VCE

a) CC decreases
b) CE decreases
c) gm decreases
d) a + b ;
19) The parameters that are independent of VCE

a) gm
b) CE
C)CC
d) all
20) With increasing temperature

a) rbe increases
b) rbe decreases
c) rbe does not change
d) CC increases
Answers:
1. d
2. c
3. d
4.Gm/2(
C+ C)
5.a
6.c
7.a
8.d
9.c
10.c
11.d
12.d
13. a
14.c
15.a
16.d
17. d
18.d
19. a
20. a
UNIT IV: MOS Amplifiers

1) The transconductance (gm) of a MOSFET is of the order of
a) 100 mhos
b) 50 mhos c) 0.01 mhos
b) 0.1 pF
c) 100 pF
d) 1 pF
3 The dynamic drain resistance of MOSFET is of the order of

d) 0.1 mhos
2) Interelectrode capacitances in a MOSFET are of the order of

a) 1 pF

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b) 100M
a) 1OK
c) 500k
d) 5M
4 A MOS tristor itself can be used as a current if it operates in

a) Triode region
b) cut-off region
c) Saturation region
d) None of the above.
5 An important property of the cascade structure is its

a) Low input impendence
b) Highoutput impedance
c) Low output impedance
d) High output impedance
6. ------------------- is commonly used as a voltage buffer

7. In a common gate amplifier ,input is applied at a ------------ terminal of MOSFET
8. Common gate amplifier has----------------------- input impedance
Answers:
1. D
2. A
3. A
4. C
5. B
6. SOURCE FOLLOWER
7. SOURCE
8. LOW
Unit V: Feedback Amplifiers

1 The negative feedback in an amplifier
a) Reduces the voltage gain

b) Increases the voltage gain
c) Does not affect the voltage gain
d) Can convert it in to an oscillator if the amount of feedback is enough
2 Negative feedback in amplifiers
a) Lowers its lower cut-off frequency
b) Raises its upper actoff frequency A
c) Increases the band-width
d) Current-shunt type
3 Emitter follower Is
a) Voltage-shunt type.
b) Voltageseries type
c) Current-series type
d)Currentshunt type
4 Positive feedback is used in

a) Amplifiers
b) Transistor
c) oscillators
d) None
5 When the feedback energy (voltage or current) is out of phase with the input signal
and thus opposes it, it is called,
a) Direct feedback
b) Positive feedback
c) Regenerative feedback
d) Degenerative feedback

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6 The advantages of negative feedback is

a) Reduction is distortion
b) Stability in gain
c) Increased bandwidth
d) All
7 In voltage series feedback

a) Increases the input impedance
b) Decreases the gain
c) Decreases the output impedance
d) All the above
8 In current-shunt feedback, the output impedance

a) Decreases b) Increases
c) Remains same
d) None All
9 The voltage shunt feedback

a) Increases both the input and output impedances
b) Increases input impedance and decreases output impedances
c) Decreases both the input and output impedances
d) None
10 The current series feedback
a) Increases both the input and output impedances
b) Decreases both the input and output impedances
c) Increases input impedance and decreases output impedance
d) None
11 In a negative feedback amplifier, shunt-mixing
a) Does not alter the output resistance
b) Tends to increase the input resistance
C) tends to decrease the input resistance
d) Produces the same effect on input resistance as
series mixing
12) In a negative feedback amplifier; series mixing
a) Does not alter the input resistance,

c) Tends to decrease the input resistance
b) tends to increase the, input resistance

shunt mixing
13 In negative feedback amplifier, current sampling
a) Does not alter the output resistance
b) Tends to increase the output resistance
c) Tends to decrease the output resistance
voltage sampling
I4 In a negative feedback amplifier, voltage sampling
a) Does not alter.-the output resistance
b) tends to increase the output resistance
c) Tends to decrease the output resistance a d) Produces the same effect on input resistance as
current sampling
15 In a feedback amplifier, loop gain is

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a) 1/A
c) A
b) A
d) -1/ A
16 in a feedback amplifier, sensitivity D equals

a) 1+ A
b) 1- A
c) A
d) 1/( A+1)
1 7 It is desired to reduce total harmonic distortion of an amplifier from 85 to 20% by

use of 5% feedback. What is the gain of the amplifier with original distortion and
With reduced distortion?
a) 6, 1.5
b) 60, 15
c) 15, 90
d) 1.5, 6
18 Transmission gain in negative feedback amplifier

a) A/(1+/ A )
b) A
C) 1/ A
d) A/(1- A)
19 Negative feedback
a) Decreases lower cut off and increase higher cut off frequencies
b) Decreases higher and lower cut off frequencies
c) Increases higher and lower cut off frequencies
d) None
20 An amplifier with resistive negative feedback has two left half plane poles in its
Open-loop transfer function, the amplifier
a) May be unstable, depending on the feedback factor
b) Will always be unstable at high frequencies ,
c) Will be stable for all frequencies,
d) Will oscillate at low frequencies
Answers:
1A
2.C
3.B
4.C
5.D
6.D
7.D
8.B
9. C
10.C
11. C
12.B
13.B
14.C
15.C
16.A
17.B
18 B
19.A
20.C
UNIT VI: Oscillators

1 An electronic oscillator is,
a) An amplifier
b) An amplifier with feedback
c) Converter of a.c. to d.c.
d) Just like an alternator
2 For sustaining oscillations in an oscillator

a) Feedback factor should be unity
b) Phase shift should be zero
c) F Feedback should be zero
d) Both (a) and (b)
3 For generating 1KHz frequency, the most suitable circuit is,

a) Tuned collector oscillator
b) Hartley oscillator
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c) Collpitts oscillator
d) Wein bridge oscillator
4 The phase difference between input and output voltage of an oscillator is,
a) 180
b) 360
c) 90
b) AB = 1/29 c) AB = 29
a) Amplifier without feedback
b) Amplifier with positive feedback
c) Amplifier with negative feedback
d) ac to dc converter
7 The maximum phase shift produce by an ideal section of the RC circuit Is

b) 90
c) 30
d) AB = 3
6 An electronic oscillator contains
a) 45
d) 270
5 Barkhausen criteria says

a) AB = 1
d) 60 A
8 The phase shift introduced by RC network section is
a) Greater than introduced by the amplifier b) Less than introduced by the amplifier
c) Equal to that introduced by the amplifier d) None of these
9 The number of RC sections required in phase shift oscillator is at least
a) One b) Two c) Three
d Four
10 The phase shift oscillator can produce

a) Rectangular wave shapes
b) Sine waves
c) Irregular wave shapes
d) DC voltages
11 The weinbridge oscillator uses

a) Negative and positive feedback both
b) Negative feedback only
c) Positive feedback only
12 In oscillator circuit the energy feedback to its input terminal from the
a) 90 out of phase with the input signal
b) 180 out of phase with input signal
c) In phase with the input signal
d) None
13 To generate a 1 MHZ signal, the most suitable circuit is

a) Colpitts oscillator
b) Phase shift oscillator
c) Wein bridge oscillator
14 lf Barkhausen criterion is not fulfilled by an oscillator circuit, it will

a) Produces high frequency whistles
b) Stop oscillating
c) Produce damped waves continuously
d) Become an amplifier
15 .Wein bridge oscillator is most often use whenever

a) Square output waves are required
b) High feedback ratio is needed A
c) Extremely high resonant frequencies are required .d) Wide range of high purity sine waves is to be
generated
16 Electronic oscillator is better than mechanical one because

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a) It can produce 20Hz to 20OHz
b) It has better frequency stability
c) It has higher efficiency
d) none
17 The current amplification factor in radian square of Colpitts oscillator is

a) C1 C2
b) C1 C2
c) C1/C2
d) C1 +C2
18 The feedback factor B at frequency of oscillation of Wein bridge oscillator is

a) -1/29
b) 3
c) 1/29
d) 1/3
19) In tuned collector oscillator, frequency w of oscillation is where wo, is frequency of resonance
a) >wo
b) w/hfe
C) <wo
d) =wo
Answers:
1.C
11.A
2.D
12.C
3.D
13.A
4.A
14.C
5.A
15.D
6.B
16.B
7.D
16.B
8.C
17. C
9.C
18.D
10.B
19. A
UNIT- VII: Large Signal Amplifiers

1 ln class-A large signal amplifiers, Q-point is located
a) Below cut-off
b) At cut-off
c) On center of load line
d) below midpoint of load line
2 In class-A power- amplifiers, conduction angle is

a) 360
b) 180
c) 180-360'
b) 50%.
c) 78.5%
b) 50%
c) 25%
b) Class-B
c) Class-AB d)Class-C
6 For a class-B amplifier, Q-point is located

a) Below cut off
b) on cut-off
c) Below midpoint of load line
d) none of the above
7 Maximum theoretical conversion efficiency of class A series fed amplifier is,

a) 15%
d) 28.5%
5 Of the following power-amplifiers, which has maximum theoretical efficiency

a)Class-A
d) 25%
4 In transformer coupled power- amplifier, maximum theoretical efficiency is

a) 78.5%
d) < 180
3 In series-fed class-A power amplifier maximum theoretical efficiency is

a) 28.5
b) 25%
c) 50%
d) 78.5%
8 Maximum theoretical conversion efficiency of class A transformer coupled amplifier is

a) 15%
b) 25%
C) 50%
9 Maximum theoretical collector circuit efficiency of class B amplifier is

d) 78.5%

Page 131
a) 15%
b) 25%
c) 50%
d) 78.5%
10 In the output of a push pull amplifier, the most disturbing harmonic distortion is the
a) Second harmonic
b) Third harmonic
c) Fourth harmonic
d) Fifth harmonic
11 in c class B push pull amplifier, the ratio of the maximum. Collector dissipation to maximum
ac power output is about
a) 0.25
b) 0.4
c) 0.5
d) 0.75
12 ln a large signal amplifier, total harmonic distortion is given by

a) D=D2+D3+D4+ ......
b) D=D22+D32+D42+...
C) D=B0+D22+D32+D42+...
d) D= D2+D3+D4+ ....../ (D22+D32+D42+...)
13 in a class B amplifier, then maximum output power Pmax equals

2
a) Vcc /RL
b)VCC/2RL
c)Vcc /2RL
d)Vcc /2RL
14 Class B push pull amplifier suffers from

a) Crossover distortion
b) Inter modulation distortion
c) Excessive harmonic distortion
d) Phase distortion
15 A push pull amplifier

a) Eliminates add harmonics
b) Eliminate even harmonics
st
c) Is a 1 stage of an audio amplifier d) Uses single transistor.

16 The main purpose of using transformer coupling in a class A amplifier is to make it more
a) Efficient
b) Less costly c) Less bulky d) Distortion free
Answers:
1.c
9.d
2.a
10.b
3. d
11.b
4.a
12.b
5.d
13.d
6.b
14.a
7.b
15.b
8.c
16.a
UNIT-VIII: Tuned Amplifiers

1 Following is the expression for frequency (Hz) of a parallel tuned circuit formed by capacitor C
(lossless) and inductor L (with series. resistance R),
a)1/2LC
b) 1/LC
c) 1/2LC*1-CR2/ L
d) 1/2LC*1-CR/ L2
2 At resonance the impedance of a parallel tuned circuit formed by capacitor C (lossless) and inductor
L (with series resistance R) approximately equals
a)L/CR
b)LC/R
c)LR/C
b)2 f0/Q0
c) Q0 f0/
d)1/LCR
3 3-dB bandwidth in Hz of a parallel tuned circuit equals,

a) 2 f0/Q0
d) f0/Q0
Where f0 is the frequency of resonance and Qo is the effective Q at resonance.

4 In a Single tuned capacitance coupled amplifier, the frequency response depends on,
a) Only the input circuit
b) Only the output circuit

Page 132
c) Both input and output circuits d) Neither input circuit nor output circuit 1
5 In a capacitance coupled single tuned amplifier, the effective Q of the output circuit at resonance
depends,
a) Only on inductance L
b) Only on capacitance C
c) Only on effective shunt resistor Ri d) on suscuptance of L (or C) and shunt resistance Ri

6 In a capacitance coupled single tuned amplifier, phase angle of the relative voltage gain A/Am
equals,
[
a) arc tan (2Qe)
b) -arc tan (2Qe)
c) arc tan (Qe)
d) -arc tan (Qe)
7 The 3-dB bandwidth (radians/sec) of a single tune capacitance coupled amplifier is,
a) Req C
b) C/ Req
c)1/ Req C
d) Req/C
8 ln a single tuned tapped capacitance coupled amplifier, tapping on the coil is used to,
a) Permit use of smaller coiled
b) Permit use of smaller tuning capacitor
c) Permit maximum transfer of power d) Permit adjustment of 3-dB bandwidth

9) ln a double tuned amplifier with coupling greater than critical, maximum transfer of power takes
place,
[
a) Only at the frequency of resonance fo
b) at one more frequency other than fo
c) at two more frequencies other than f0
d) at 4 more frequencies other than f0
Answers:
1.c
2.a
3. d
4. b
5. d
6. b
7. c
8. c
9. b

Page 133
ESSAY TYPE
QUESTIONS
Essay Questions

1 Draw the AC equivalent of a CE amplifier with fixed bias using h-parameter model and
2 Derive the expression for Ri, Av, Ro,AI and Avs for CE amplifiers
3 Draw the equivalent circuit of a CE amplifier with un bypassed emitter resistor using
4 h- Parameter model and derive the equations for Zin, Zout, Av & Ai of CB configuration
5 Draw ac equivalent circuit for a CE Amplifier
(i) with bypassed emitter resistor and find AVS & AIS
(ii) with an un bypass emitter resistor and find RI & RO
6 A transistor with hie=1.2k,hfe=75,hre=200*10 -4,hoe=20microA/V is connected in CE
configuration given below. Calculate AI, AIS, AV, AVS, RI, RI1, RO, and RO by using below
figure.
VCC
12kOhm
3.5kOhm
Vo
1uF
37kOhm
1uF
Q1
2.5kOhm
1.2kOhm
BC107BP
1uF
V1
37kOhm
320 Ohm
1uF
Ri1
Ri
7. (a) For the circuit shown in figure1, estimate A i, Av, Ri & Ro using resonable

Page 135
Essay Questions
approximations. The h parameters for the transistor are given as h fe = 100, hie = 2k, hre is
negligible & hoe = 105 mhos
(b) Draw the ciruit diagram of Emitter follower and derive the equation for voltage
& current gains.
8. (a) Prove that the following two networks (a) & (b) shown in figure 6 have the
same currents if excited by same voltages.
(b) Draw the simplified hybrid model for the CC circuit and derive expressions
for input Resistance, output resistance voltage gain and current gain.
9. (a) When n-identical stages of amplifier are cascaded. Derive the expression for
lower and upper cutoff frequencies.
(b) Explain the effect of coupling capacitor in a CE amplifier on low frequency
response of amplifier.
10. (a) Obtain CC 'h' parameters interms of CE parameters.
(b) For a CE amplifier, calculate the voltage gain, input impedance, and output

Page 136
Essay Questions
Impedance, current gain. If R L = 10k, hie = 1.1k, hre = 2.5104, hfe = 50, hoe = 24A/V.
1. What are the different types of distortion in amplifiers and explain in detail.
2. Explain cascade amplifier and derive AI,Av,A&Ais Darlington pair and derivation.
3. Explain the effect of emitter bypass capacitor CE on low frequency response.
4. Calculate Darlington pair Ri,Ai,Av & Ro using hie=50, hre=2.510-4 , hoe=25A/v, Rs=3k &
RE=3k.
5. Explain the different types of coupling schemes
6. Compare emitter follower and Darlington emitter follower configurations in respect of.
(i) Current gain.
(ii) input impedance.
(iii) voltage gain.
(iv) Output impedance

7. (a) How the bandwidth is efected in multistage amplifier?
(b) What are the advantages of direct coupled amplifiers?
(c) What is the use of transformer coupling in the output stage of multi-stage amplifier?
8. (a) Write the equation for overall gain of a n - stage cascaded Amplifier.
(b) How does the frequency response an amplifier change with cascading of
amplifier stages?
(c) Explain the choice of configuration in a cascade of amplifiers.

1. (i) Discuss the effect of emitter bypass capacitor on low frequency response of BJT amplifiers.
(ii) For the CE amplifier, calculate the mid frequency voltage gain and lower 3-dB point. The
transistor has h-parameter of hfe=400 and hie=10k. The circuit details are Rs=600, RL=5k
RE=1k ,Vcc=12v,R1=15k , R2=2.2k, and CE=50f.
2. Derive the expression for the CE short-circuits current gain Ai with resistive load.
3. Derive the expression for fT and f of CE amplifier using high frequency model.
4. Derive the gain bandwidth product for voltage and gain bandwidth product of current.
5. A high frequency amplifier uses a transistor which is driven from a source with Rs=0.
Calculate value of fH, if RL=1k. Assume typical values of hybrid parameters
6. (a) Prove that hfe=gm rbe
(b) How does gm vary withIC ,VCE &T ?
(c) Draw the small-signal high frequency CE model of a transistor.
7. a) Define f and fT and also establish the relationship between ff and fT .
(b) Derive the expression for the CE short -circuit current gain as a function of
frequency.
8. (a) Explain why the upper 3-dB frequency for current gain is not the same as fH
for voltage gain.
(b) A Silicon PNP transistor has an f fT = 400MHz. What is the base thickness?
(c) In terms of what parameters is the high frequency response of a CE stage obtained?

Page 137
Essay Questions

1. Derive the expression for voltage gain for CS amplifier with resistive load.
2. Draw and explain the CS stage with diode connected load.
3. Draw and explain the source follower circuit.
4. Draw and explain the CG amplifier.
5. State the advantages and disadvantages of source follower circuit.
6. Explain the cascode amplifier with current source load
7. Draw and explain the folded cascade amplifier.
8. (a) Derive the equation for voltage gain of a Common Source FET amplifier.
(b) The amplifier shown in figure 2 uses an n - channel FET having IDSS = 2mA,
VP = -2V. If the quiscent drain to ground voltage is 10V, find R 1 and
the efective input impedance.
9. (a) Sketch the circuit of a CS amplifier. Derive the expression for the voltage gain
at low frequencies. What is the maximum value of voltage gain?
(b) The FET shown in figure 5 has the following parameters:
IDSS = 5.6mA & VP = -4V. If Vi = 10V find VO.
10.(a) Derive an expression for voltage gain of a common source FET amplifier with
and without source resistance included in the circuit
(b) Calculate the voltage gain of the FET amplifier shown in the figure 7, assuming
blocking capacitor to be large and4dgm= = 4mA/V and rd =5K[8

Page 138
Essay Questions
11. (a) Why a FET cannot be explained with h-parameters?

(b) Derive an expression for Trans - conductance using FET model.
(c) Draw and explain the FET high frequency model.

1. A) Classify the amplifiers based on feedback topology and give their block diagrams. How
input and output impedance are affected in each case?
B) What are the advantages and disadvantages of negative feedback?
2. A) Explain the concept of FB as applied to electronic amplifier circuits .what are the
advantages &disadvantages of positive and negative FB?
B) Calculate transistance gain, Rif, R0f of the shunt-shunt feedback
amplifier .the basic amplifier trans resistance Rmf=50k, hie=1.1k,
R0=40k,RL=4k,=0.1
3. Draw the circuit diagram of current shunt feedback and derive the
expressions for input and output resistance
4. A) Draw the circuit of a voltage shunt forward bias using BJT and derive expression for all
the parameters. B) An amplifier has voltage gain with feedback of 100.if the gain without
feedback changes by 20%, determine the values of open loop gain A and feedback ratio .
5. (a) Derive an expression for frequency of oscillation of a RC phase-shift oscillator
using a FET.
(b) In a Hartley oscillator L 2 = 0.04 mH and C = 0.004 F . If the frequency of
oscillation is 150 KHz, find L11. Neglect mutual inductance.
6. Derive an expression for the transfer gain of a feedback amplifier.
7. (a) What are the characteristics of an amplifier that are modified by negative
feedback?
(b) Draw the four types of feedback amplifiers naming them.
(c) Define sensitivity & Desensitivity factors in feedback Amplifiers.

Page 139
Essay Questions

1. Draw the circuit diagram of a RC phase shift oscillator using BJT .derive the expression for
frequency of oscillations.
2. What are the factors that affect the frequency stability of an Oscillator?
How frequency can be improved in oscillators?
3. A) Explain necessary condition for oscillators.
B) A FET phase shift oscillator has gm=5mhos and rd=50k. The
Feedback resistance is 100k and the capacitor value is
64.79PF.calculate the frequency of the oscillator and the value of Rd.
4. (i) Classify various oscillators based on output waveforms, circuit
Components, operating frequencies and feedback used. ii) A FET phase
shift oscillator has gm=5mhos and rd=50k. The feedback resistance is 100k and the
Capacitor value is 64.79PF.calculate the frequency of the oscillator and the value of Rd.
UNIT VII: LARGE SIGNAL AMPLIFIERS

1. Explain about class-A, class-B, class-C and class-AB operation of power amplifiers? B) A
single transistor operates as an ideal class-B amplifier .if D.C current drawn from the supply
is 2.5 mA; calculate the A.C power delivered to load for load resistance of 2k.
2. Explain how the overall distortion is reduced in a push-pull configuration through relevant
mathematicalexpressionsandcircuit diagrams. B) A transistors supplies 0.85w to a 4 k
load, the zero signal D.C collector current is 3 mA and the D.C collector current is 31 mA
and the D.C collector current with small signal is 34mA. Determine the second harmonic
distortion.
3. Derive the expression for maximum collector power dissipation Pd max in the case of class
b power amplifiers .what is its maximum efficiency?
4. Explain thermal stability and heat sinks. B) A silicon power transistors is operated with a
heat sink having thermal resistance sA=1.5 0 C/W the transistors rated at150w (250) has
Jc=0.50C/W and the mounting insulation has Jc=0.60C/W Calculate the maximum power
that can be dissipated if the ambient temperature is 400c and Tjmax=2000c?
5. (a) What is push-pull configuration and how does this circuit reduce the harmonic
distortion?
(b) For a class B amplifier providing a 20V peak signal to a 16 load operates on a power
supply of Vcc = 30V. Determine the input power, output power and circuit
efficiency.

Page 140
Essay Questions
6. a) What is a class B amplifier? Where is it employed? Give its circuits, design

equations, characteristics & limitations.
(b) A transformer coupled class A large signal amplifier has maximum and minimum values of collector to emitter voltage of 25V and 2.5V. Determine its
collector efciency.
7. (a) A transistor supplies 0.8W to a 5K load. The zero signal dc collector current
is 30mA, and the dc collector current with signal is 36mA. Determine the percent second harmonic distortion.
(b) Define conversion efciency. Determine the maximum value of conversion
efciency for a series - fed class A power amplifier.
UNIT-VIII: TUNED AMPLIFIERS

1. (i)Derive an expression for tuning frequency of a single tuned amplifier in terms of quality
factor and bandwidth of the amplifier. (ii) What is the need for stagger tuning in amplifiers?
Compare the frequency response characteristics of the single tuned and double tuned amplifier
with stagger tuned amplifier.
2. A) Explain the operation of a stagger tuned amplifier what is the effect of cascade in the tuned
amplifiers. B) Discuss elaborately in the stability of tuned amplifiers.
3. A) Explain in detail the effect of cascading single tuned amplifiers and hence derive the
expression for band width of n-stage amplifier.
B) The band width for single tuned amplifier is 20khz.calculate the bandwidth of such three
stages are cascaded .also calculate the bandwidth for 4 stages.
4. A) Draw the ideal and actual frequency response curves of a single tuned amplifier.
B) Derive the expression for Q-factor of a capacitor.
5. A) draw and explain the circuit diagram and equivalent circuit using high frequency hybrid
model of a single tuned capacitance coupled BJT amplifier
B) Also draw and explain the obtained modified high frequency equivalent circuit after applying
millers theorem
6. (a) Draw the equivalent circuit of a double tuned amplifier and derive the expression
for gain at resonance.
(b) Derive the expression for effective bandwidth of cascaded tuned amplifier
7. (a) Draw the equivalent circuit of a single tuned capacitive coupled ampifier and
derive the expression for gain at resonance.
(b) Draw the circuit diagram for tuned RF amplifier and explain its working.
8. (a) Draw the frequency response of tapped single tuned capacitance couplped
amplifier and derive the expression for L for maximum power transfer.

Page 141
Essay Questions
(b) Draw the circuit of double tuned amplifier and explain its working.
9. (a) Draw the electrical model of a piezoelectric crystal.
(b) Sketch the reactance Vs frequency function.
(c) Over what portion of the reactance curve do we desire oscillations to take place
when the crystal is used as part of a sinusoidal oscillator? Explain.

Page 142
ASSIGNMENT
QUESTIONS
1. Write short notes on transistor as amplifiers.
2. Explain the single stage CE amplifiers.
3. Explain the need of C1 and C2 in CE amplifiers.
4. Comment on h-parameters with operating point and list the benefits of h-parameters
5. Draw the small signal low frequency equivalent circuit of BJT and explain each parameter of
this circuit.
6. Draw ac equivalent circuit for a CE Amplifier
(i) with bypassed emitter resistor
(ii) with an un bypass emitter resistor
7. Using the approximate h-parameters mode .derive expressions for current gain, input
resistance, voltage gain and output admittance of a CE Amplifier with a resistor in emitter
circuit.
8. (a) Draw a typical CE amplifier and explain the functions of each component in it.
(b) For a CE amplifier ,what is the maximum values of Rs for which Ro differ by not more
than 10% of its value Rs=0; Given hie=1.1k, hfe=50, hre=2.5*104, hoe=25A/v
9. For the emitter follower with Rs=0.5k and RL=5K, calculate AI ,Ri, AV, AVs, and Ro assume
hfe=50,hie=1k,hoe=25A/v.
10. Calculate Ai,Ri,Av and Ro for the above CB Amplifier with
RL=5K,Rs=500
ohms, hfe=50,hie=1k,hoe=50k,Re=10k and Rc=10k.

11. (a) Discuss the classification of amplifiers based on frequency range, type of coupling,
power delivered and signal handled.
(b) For the common gate Amplifier, derive expression for voltage gain, input impedance, out
impedance.
12. Give the significance of Millers Theorem and Dual of Millers Theorem in the amplifier
circuit analysis.

1.
Explain the need for multi stage amplifiers.
2.
Draw and explain the block diagram of two stage cascaded amplifier.
3.
Explain the procedure to find out the 3db band width of the multi stage amplifier.
4.
Explain the procedure to find out the overall voltage gain, current gain, input and output
impedances of the multi stage amplifier.

Page 144

5.
Three identical non interacting amplifier stages in cascade have an overall gain of 1db
down at 30Hz compared to midband. Calculate the lower cut off frequency of the individual
stages.
6.
Draw the circuit of single stage RC coupled BJT amplifier. Discuss the effect of an emitter
bypass capacitor on low frequency response.
7.
Compare emitter follower and Darlington emitter follower configurations in respect of . i)

current gain ii) input impedance iii)voltage gain. Iv) Output impedance.
8.
Compare the three types of coupling methods used in multistage amplifiers.
9.
Discuss about different types of distortions that occur in amplifier circuits.
10. For the circuit shown in below figure, the transistors are identical with hfe=76, hie=1.5k and
hre=0. Calculate Avs and Ais.
VCC
-12V
R1
10kOhm
Q1
Q2
2N3702
R3
1kOhm
2N3702
R2
5kOhm

1. Draw the circuit diagram of single stage RC coupled BJT amplifier. Discuss the effect of an
emitter bypass capacitor on low frequency response.
2. Distinguish between the high frequency and the low frequency operation of BJT amplifiers
and give their analysis techniques.
3. In hybrid model of a transistor at high frequencies, show that gm is proportional to the
collector current.
4. Explain how the hybrid parameter varies with temperature.
5. What is the order of magnitude of each resistance in the hybrid- model?

Page 145
6. Draw the small signal equivalent circuit for an emitter follower stage at high frequencies and
explain the working of it.

1. Explain linear and non-linear systems.
2. Draw and explain the small signal model of MOS.
3. Draw and explain the common source stage of MOSFET amplifier.
4. Derive the expression for voltage gain for CS amplifier with resistive load.
5. Draw and explain the CS stage with diode connected load.
6. Draw and explain the source follower circuit.
7. Draw and explain the CG amplifier.
8. State the advantages and disadvantages of source follower circuit.
9. Explain the cascode amplifier with current source load
10. .Draw and explain the folded cascade amplifier.

1. With the help of general block diagram explain the term feedback.
2. What are the different types of feedback amplifiers? Give their equivalent circuits.
3. Draw the circuit diagram of voltage series feedback and derive expression for input resistance
and output resistance.
4. Draw the circuit diagram of voltage shunt feedback and derive expression for input resistance
5. Draw the circuit diagram of current series feedback and derive expression for input resistance
6. Draw the circuit diagram of current shunt feedback and derive expression for input resistance
7. State the transfer gain of each configuration and define feedback factor.
8. Draw the frequency response of an amplifier with and without feedback and show the
bandwidth for each case and how curves are related to gain bandwidth product.
9. Draw the practical circuit for current series feedback and find the voltage gain, input and
output impedance.
10. An amplifier has voltage gain with feedback is 100. If the gain without feedback changes by
20% and the gain with feedback should not vary by more than 2% , determine the values of
open loop gain and feedback ration .
11. An amplifier has a mid band gain of 125 and bandwidth of 250KHZ. I) if 4% negative
feedback is introduced, find the new bandwidth and gain. II) if the bandwidth is to be
restricted to 1MHZ. find the feedback ratio.

Page 146

1. Explain the concepts of feedback as applied to electronic amplifier circuits. What are the
advantages and disadvantages of positive and negative feedback amplifiers?
2. Classifies various oscillators based on output waveforms, circuit components, operating
frequencies and feedback used.
3. State and explain the barkhausen criterion.
4. Draw the circuit diagram of RC phase shift oscillator and explain its operation.
5. Explain the principal operation of a wien bridge oscillator?
6. Discuss and explain the basic tank circuit of LC oscillator and derive the condition for the
oscillatons.
7. Explain the operation of Hartley oscillator. Derive the formula for the frequency.
8. Explain the operation of Colpitts oscillator. State the formula for the frequency.
9. What is piezoelectric effect? Draw and explain a.c. equivalent circuit of a crystal.
10. What are the advantages of crystal oscillators?
11. What is frequency stability of Oscillator? What are the factor effecting the frequency
stability.
UNIT- VII: LARGE SIGNAL AMPLIFIERS

1. Mention the difference between Voltage amplifiers and power amplifiers.
2. Give the different analysis techniques to make the analysis of power amplifier.
3. Compare the various classes of operation of power amplifiers based on a) operating cycle b)
position of Q point c) efficiency.
4. Give the expression for the d.c. power input, a.c. power output and efficiency of a series fed,
directly coupled class A amplifiers.
5. With the help of a neat circuit diagram, explain the operation of a complementary Symmetry
configured class B power amplifier.
6. With the help of a neat circuit diagram, explain the operation of a push-pull configured class
B power amplifier.
7. Compare and contrast push-pull and complementary symmetry configurations for class B
power amplifiers.
8. What do you mean by harmonic distortion? How this distortion can be minimized in power
amplifier.
9. What is thermal resistance? What is the unit of thermal resistance?

Page 147
10. Write short notes on requirement and types of heat sinks for power dissipation in large
signal amplifiers.
11. In transformer coupled class A power amplifier, show that conversion efficiency is 50%..
12. Discuss in detail the cross over distortion. How do you avoid the cross over distortion in
power amplifier circuit? Discuss in detail.
13. Draw a simple series fed class A amplifier circuit and derive the relationship for output
power in terms of load resistance RL?
14. Sketch the output waveforms for class A, class B and class C with respect to conduction
angle.
UNIT-VIII: TUNED AMPLIFIERS

1. What do you mean by tuned amplifier?
2. What do you mean by unloaded Q and loaded Q?
3. Distinguish between the power amplifiers and the tuned amplifiers.
4. What are the requirements of tuned amplifier? Classify tuned amplifiers.
5. Draw the ideal and actual frequency response curves of a single tuned amplifier.
6. Derive an expression for tuning frequency of a single tuned amplifier in terms of quality
factor and bandwidth of the amplifier.
7. Derive the equation for the 3dB bandwidth capacitance coupled single tuned amplifier.
8. What is the effect of cascading single tuned amplifers on bandwidth? Derive expression for
it.
9. Distinguish between the single tuned and double tuned amplifiers.
10. What is the need for stagger tuning in amplifiers? Compare the frequency response
characteristics of the single tuned and double tuned amplifier with stagger tuned amplifier.
11. Explain the stabilization techniques used in tuned amplifiers.
12. Discuss advantages and disadvantages of tuned amplifiers.
****THE END****

Page 148
Electromagnetic theory
&transmission lines
Mr. V. PRAKASAM
Asst.Professor
&
Mr.P.upender
Asst.professor
COURSEFILE
Department of

NALGONDA (DISTRICT)-508284
Sponsored by
COURSE
OBJECTIVE
Electromagnetic Theory And Transmission Lines
Course Objective
COURSEOBJECTIVE
At low frequencies, an electrical circuit is completely characterized by the electrical parameters
like resistance, inductance etc. and the physical size of the electrical components plays no role in the
circuit analysis. As the frequency increases however, the size of the components becomes important,
that is to say that, the space starts playing a role in the performance of the circuit. The voltage and
currents exist in the form of waves. Even a change in the length of a simple connecting wire may alter
the behavior of the circuit. The circuit approach then has to be re-investigated with inclusion of the
space into the analysis. This approach is then called the transmission line approach.
One can then conveniently divide the subject of electromagnetic in two parts, the static
electromagnetic and the time varying electromagnetic. It will be clear subsequently, the time varying
electric and magnetic fields always constitute a wave phenomenon called the electromagnetic wave,
which is the prime subject of discussion. The phenomenon of electromagnetism in totality is governed
by the four Maxwell's equations, which can be derived from the physical laws like the Gauss Law, the
Ampere's law and the Faraday's low of electromagnetic induction.
The electromagnetic theory is the generalization of the circuit theory, or the circuit theory is
rather a special case of the electromagnetic theory. Although every phenomena of electricity and
magnetism can be analyzed in the frame work of electromagnetic theory, at low frequencies the circuit
approach is adequate. As the frequency increases the inadequacy of the circuit approach is felt and one
is forced to follow the electromagnetic field approach.
The primary objective of a transmission line is to carry electromagnetic energy efficiently from
one location to other; they find wide applications in high frequency circuit design. As the frequency
increases, any discontinuity in the circuit path leads to electromagnetic radiation. Also at high
frequencies, the transit time of the signals cannot be ignored. In the era of high speed computers, where
data rates are approaching to few Gb/sec, the phenomena related to the electromagnetic waves, like the
bit distortion, signal reflection, impedance matching play a vital role in high speed communication
networks.
An antenna is a device, which can launch and receive electromagnetic waves efficiently. But for
the large antennas, the communication between an earth station and a satellite is practically impossible.
The communication, which can be established with few watts of power, would need few MW of power
in the absence of proper antennas. However, antenna research is still very active. With recent advances
in mobile communication, design of compact, efficient, multi-frequency antennas have received a new
impetus in the last decade.

Page 151
Syllabus
Syllabus
SYLLABUS
UNIT-I: ELECTROSTATICS I
Coulombs law, electric field intensity-fields due to the different charge distributions, electric flux
density, gauss law and applications, electric potential, relations between E and V, Maxwells two
equations for electrostatic fields, energy density, illustrative problems
UNIT-II: ELECTROSTATICS- II
Convection and conduction currents, dielectric constant, isotropic and homogeneous dielectrics,
continuity equation, relaxation time, poissions and Laplaces equations; capacitance-parallel plate, coaxial, spherical capacitors, illustrative problems.
UNIT-III: MAGENTO STATICS
Biot-savarts law, amperes circuital law and applications, magnetic flux density, Maxwells two
equations for magneto static fields, magnetic scalar and vector potentials, forces due to magnetic fields,
amperes force law, inductances and magnetic energy, illustrative problems
UNIT-IV: MAXWELLS EQUATIONS (TIME VARYING FIELDS)
Faradays law and transformer emf, inconsistency of amperes law and displacement current density,
Maxwells equations in different final forms and word statements, conditions at a boundary surface:
dielectric-dielectric and dielectric-conductor interfaces, illustrative problems
UNIT-V: EM WAVE CHARACTERISTICS I
Wave equations for conducting and perfect dielectric media, uniform plane waves-definition, all
relations between E &H, sinusoidal variations, wave propagation in lossless and conducting media,
conductors and dielectrics-characterization, wave propagation in good conductors and good dielectrics,
polarization, illustrative problems
UNIT-VI: EM WAVE CHARACTERISTICS II
Reflection and refraction of plane waves-normal and oblique incidences, for both prefect conductor and
perfect dielectrics, Brewster angle, critical angle and total internal reflection, surface impedance,
poynting vector and poynting theorem-applications, power loss in a plane conductor, illustrative
problems
UNIT-VII: TRANSMISSION LINES I
Types, parameters, transmission line equations, primary & secondary constants, expressions for
characteristic impedance,propogation constant, phase and group velocities, infinite line concepts,
losslessness/low loss characterization, distortion-condition for distortion less ness and minimum
attenuation, loading types of loading, illustrative problems

Page 153
Syllabus
UNIT-VIII: TRANSMISSION LINES II

Input impedance relations, SC and OC lines ,reflection coefficient, CSWR,UHF lines as circuit
elements, significance of Zmin and Zmax smith chart-configuration and applications, single and double
stub matching, illustrative problems.
TEXTBOOKS:
1. Elements of electromagnetic-matthew N.O Sadiku,4th edition,2008,oxford univ.press
2. Electromagnetic waves and radiating systems-E.C Jordon and K.G Balmain,2ed.,2000,PHI
3. Transmission lines and networks Umesh sinha,satya prakashan, 2001,(Tech.India Publications),New
Delhi
REFERENCES:
1. Engineering electromagnetic-Nathan ida, 2 ed.,2005, springer(India) Pvt . Ltd.,New Delhi
2. Engineering electromagnetic- William H.Hayt Jr. and John A.B uck,7 ed.,2006,TMH
3. Networks, Lines and fields John D.Ryder,2 ed.,1999,PHI
WEBSITES
1. http://www.nptel.iitm.ac.in/courses
2. http://www.emtalk.com
3. http://www.enzim.hu/~szia/emanim/emanim.htm
JOURNALS
1. Journal of Electromagnetic Waves and Applications (JEMWA)
2. IEE Electromagnet Waves Ser. IEE, London

Page 154
STUDENT'S
SEMINAR
TOPICS
Seminar Topics

1. Electric field intensity due to infinite line charge
2. Electric field intensity due to infinite surface charge.
3. Electric potential.
4. Boundary conditions for electro statistics.
5. Gausss law applications.
6. Different types of capacitors.
7. Maxwell equations.
8. Amperes circuital law applications.
9. Uniform plane waves.
10. Reflection and refraction of electromagnetic waves.
11. Different characteristics of electromagnetic waves.
12. Poynting vector theorem.
13. Lorentz gauge force equation
14. Equations of transmission lines
15. Single and double stub matching.
16. Short circuit and open circuit transmission lines.

Page 156
LECTURE PLAN
Electromagnetic Theory And Transmission Line
Lecture Plan
LECTUREPLAN
S.No
NAMEOFTHETOPIC
MethodofTeaching
Textbooksreferred
UNIT-I:ELECTROSTATICS-I
1.
Introduction to vector algebra
2.
Co-ordinate systems-Cartesian ,cylindrical and spherical
Black boardand Chalk
3.
Electric charge, electrostatic law,coulombs law
Black boardand Chalk
4.
Electric Field Intensity,fields due to infinite line charge
Black board,and Chalk
5.
Fields due to infinite surface charge,volume charge
6.
Electric Flux Density, Gauss law
7.
Gauss Law Applications-E due to Infinite Line, Surface Charge

and Volume Charge
8.
Electric potential, relation between E and V
9.
Maxwells Two Equations for Electrostatic Fields
10.
Energy Density
11.
Boundary conditions
12.
Problems
Elements of Electromagnetics-Matthew
N.O.Sadiku,4ed.,2008,Oxford Univ.Press
UNIT-II:ELECTROSTATICS-II
13.
Convection and conduction currents
EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH
Page 158
14.
Different types Dielectrics-Isotropic And Homogeneous,

Dielectric Constant
15.
Continuity Equation, Relaxation Time
16.
Poissons and Laplaces Equations, Capacitance
17.
Different types of Capacitors- Parallel Plate Capacitor
18.
Coaxial Capacitor
19.
Spherical Capacitor
20.
Boundary conditions
21.
Related Problems
22.
Related Problems
23.
24.
25.
26.
27.
28.
29.
Lecture Plan


Black board and Chalk EngineeringElectromagneticsBio t-Sarvats Law ,Amperes Circuital Law
WilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH
Black board and Chalk EngineeringElectromagneticsAmperes Circuital Law Applications, Magnetic Flux Density
Black board and Chalk EngineeringElectromagneticsMaxwells Two Equations for Magnetostatic Fields
Black board and Chalk EngineeringElectromagneticsMagnetic Scalar And Vector Potentials
Black board and Chalk EngineeringElectromagneticsForces due to magnetic Fields, Lorentz Gauge Equation
Black board and Chalk EngineeringElectromagneticsAmperes Force Law
Black board and Chalk EngineeringElectromagneticsInductances And Magnetic Energy

Page 159
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
Lecture Plan
Black board and Chalk EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH

UNIT-IV:MAXWELLSEQUATIONS(TIMEVARYINGFIELDS)
Black board and Chalk ElementsofElectromagneticsFaradays Law and Transformer Emf
MatthewN.O.Sadiku,4ed.,2008,OxfordUniv.Press
Inconsistency Of Amperes Law And Displacement Current
Black board and Chalk ElementsofElectromagneticsDensity
Maxwells Equations in different final forms and Word
Black board and Chalk ElementsofElectromagneticsStatements.
Boundary conditions-Dielectric-Dielectric and DielectricBlack board and Chalk ElementsofElectromagneticsConductor Interfaces
ElementsofElectromagneticsproblems
UNIT-V:EMWAVECHARACTERISTICS-I
Black board and Chalk Electromagnetic Waves and Radiating SystemsWave Equations For Conducting And Perfect Dielectric Media
E.C.Jordan and K.G.Balmain, 2ed.2000, PHI
Black board and Chalk Electromagnetic Waves and Radiating SystemsDefinition of Uniform Plane Waves
Black board and Chalk Electromagnetic Waves and Radiating SystemsRelation between E&H, Sinusoidal Variations
Black board and Chalk Electromagnetic Waves and Radiating SystemsWave propagation in Lossless and Conducting Media
Wave propagation in Good Conductors and Good dielectric
Black board and Chalk Electromagnetic Waves and Radiating SystemsMedia
Black board and Chalk Electromagnetic Waves and Radiating Systemspolarization
Black board and Chalk Electromagnetic Waves and Radiating SystemsRelated problems
UNIT-VI:EMWAVECHARACTERISTICS-II
Black board and Chalk Electromagnetic Waves and Radiating SystemsReflection Of Plane Wave-Normal Incidence for perfect conductor
Black board and Chalk Electromagnetic Waves and Radiating SystemsReflection Of Plane Wave-Normal Incidence for perfect dielectric
problems

Page 160
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
Lecture Plan
Black board and Chalk Electromagnetic Waves and Radiating SystemsE.C.Jordan and K.G.Balmain, 2ed.2000, PHI
Black board and Chalk Electromagnetic Waves and Radiating SystemsReflectionOfPlaneWave--ObliqueIncidenceforperfectdielectric
Black board and Chalk Electromagnetic Waves and Radiating SystemsRefraction Of Plane Wave-Normal Incidence for perfect conductor
Black board and Chalk Electromagnetic Waves and Radiating SystemsRefraction Of Plane Wave-Normal Incidence for perfect dielectric
Black board and Chalk Electromagnetic Waves and Radiating SystemsRefraction Of Plane Wave-Oblique Incidence for perfect conductor
Refraction Of Plane WaveOblique Incidence for perfect
Black board and Chalk Electromagnetic Waves and Radiating Systemsdielectric
Black board and Chalk Electromagnetic Waves and Radiating SystemsBrewster Angle, Critical Angle and Total Internal Reflection
Black board and Chalk Electromagnetic Waves and Radiating SystemsSurface Impedance, pointing Vector
Black board and Chalk Electromagnetic Waves and Radiating SystemsPoynting Theorem- Applications
Black board and Chalk Electromagnetic Waves and Radiating SystemsPower loss in a plane conductor
Black board and Chalk Electromagnetic Waves and Radiating SystemsRelated problems
Black board and Chalk Transmission Lines and Networks-Umesh Sinha, Satya
Introduction To Transmission LinesTypes, Parameters
Prakasham,2001, (Tech. India Publications),
NewDelhi.
Transmission line equations, primary and secondary constants
NewDelhi.
Derivation of characteristic impedance
NewDelhi.
Propagation constant, phase and group velocities
Reflection Of Plane Wave-Oblique Incidence for perfect conductor

Page 161
60.
61.
62.
63.
64.
65.
66.
67.
68.
69.
Lecture Plan

NewDelhi.
Infinite And Finite Transmission Lines
NewDelhi.
Condition For Distortionlessness And Minimum Attenuation
NewDelhi.
Types of loading
NewDelhi.
problems
NewDelhi.
UNIT-VIII:TRANSMISSIONLINES-II
Short Circuit And Open Circuit Lines, Input Impedance Relations
NewDelhi.
Reflection coefficient, VSWR
NewDelhi.
/4 line impedance transformations
NewDelhi.
NewDelhi.
NewDelhi.
Significance if Zmin and Zmax
NewDelhi.

Page 162
70.
Configuration And Applications Of SMITH CHART
71.
Single stub matching
72.
Double stub matching
73.
Problems
74.
Revision
75.
Revision
76.
Revision
Lecture Plan
NewDelhi.
NewDelhi.
NewDelhi.
NewDelhi.
NewDelhi.
NewDelhi.
NewDelhi.

Page 163
LEARNING
OBJECTIVES
Learning Objective
LEARNINGOBJECTIVES
UNITI: ELECTROSTATICS-I
1. Explain the field theory.
2. Classify the charges.
3. Describe vector algebra and vector calculus.
4. Explain electrostatic law.
5. Explain columbs law.
6. Define electric field.
7. Define electric field intensity.
8. Derive an expression for the electric field intensity due to different charge distributions.
9. Define gausss law.
10. Explain the applications of gausss law.
11. Describe electric potential.
12. Deduce the relation between potential and electric field intensity.
13. Derive the Maxwells equations for electro statics fields.
14. Define energy density.
15. Solve the problems based on electrostatics.
UNITII: ELECTROSTATICS-II
1. Differentiate conduction current and convection current
2. Define dielectric constant.
3. Explain about isotropic and homogenous media.
4. Derive continuity equation.
5. Define relaxation time.
6. Deduce poissons and Laplace equations.
7. Explain the function of different types of capacitor.
UNIT III: MAGNETOSTATICS
1. Define magnetic field.
2. Explain magnetic flux.
3. State Biot-savarts Law.
4. Explain Amperes Circuital Law.
5. Derive magnetic field intensity due to different current elements.
6. Derive Maxwells equation for magnetostatics.
7. Describe boundary conditions for magnetic field.
8. Explain inductance.
9. Explain the magnetic energy.

Page 165
Learning Objective
UNIT IV: MAXWELLS EQUATIONS (TIME VARYING FIELDS)

1. Define Faradays Law
2. Explain Transformer emf.
3. Explain inconsistency of Amperes Law
4. Define displacement current density.
5. Derive Maxwells Equations in different Final Forms
6. Give the word statements of Maxwells Equations.
7. Analyze the conditions at aboundary surface
UNIT V: EM WAVE CHARACTERISTICS-I
1. Derive wave Equations for conducting and perfect dielectric media.
2. Define Uniform Plane Wave.
3. Derive relation between E&H.
4. Explain sinusoidal variations.
5. Explain wave propagation in lossless and conducting media.
6. Explain wave propagation good conductors and good dielectrics.
7. Define polarization.
UNIT VI: EM Wave Characteristics-II

1. Explain reflection of Plane Waves at normal and oblique incidences for both perfect and perfect
dielectrics.
2. Explain refraction of Plane Waves at normal and oblique incidences for both perfect and perfect
dielectrics.
3. Define Brewster Angle
4. State critical angle.
5. Explain total internal reflection.
6. Define surface impedance.
7. Define pointing vector
8. State pointing vector theorem.
9. Derive the power loss in plane conductor.
UNIT-VII: TRANSMISSION LINES-I
1.
2.
3.
4.
Define transmission line.

Derive transmission line equation.
Differentiate different types of transmission lines.
State primary and secondary constants of transmission lines.

Page 166
Learning Objective
5. Derive the expression for characteristic impedance, propagation constant, phase and group
velocities.
6. Explain infinite line concepts.
7. Define distortion.
8. Derive condition for distortion less ness and minimum Attenuation.
9. Explain loading.
UNIT-VIII: TRANSMISSION LINES-II
1 Derive input impedance relations
2 Explain short circuit and open circuit lines.
3 Define reflection coeffieient, VSWR
4 Explain UHF Lines As Circuit Elements- /4, /2, /8lines.
5 Derive impedance transformations.
6 Explain significance of Zmin and Zmax
7 Describe smith chart.
8 Explain applications of smith chart.
9 Explain single and double stub matching.

Page 167
OBJECTIVE
TYPE
QUESTIONS
OBJECTIVETYPEQUESTIONS
UNIT-I: ELECTROSTATICS I
1. Force of attraction or repulsion between two point charges is given by
a) Gausss Law
b) Amperes Law
c) Coulombs Law
d) Divergence Theorem
2. Potential difference between any two points is also written as

a) W/Q
b) Va.Edl
c) E.dl
b) (5/18) x10-3ar
c) (5/36) x10-3ar
b) Electric field intensity
c) Electric flux density
5. The statement Induced voltage acts to produce opposing flux is given by

a) Coulomb slaw b) Lenz slaw
d) (5/12) x10-3ar
4. Identify the scalar among the following

a) Force
[
d) Both a&c
3. Determine D at(4,0,3) if there is a point charge 5mC at(4,0,0) `

a) (5/9) x1 0-3ar
c) Maxwell
d) Potential
[
d) Gauss law
6.Four point charges of same magnitude Q are placed at four corners of a square .If the two charges on
the left side of the square are positive and on the right side are negative, the net force on a point
charge placed at the centre of the square is
(a) Zero
(b) 2E0
(c) 4E0
(d) 22E0
7. The E-field at a point R distance away from an infinite surface of charge density s along an unit
vector normal to the sheet is given by
(a) s20az
(b) s20an
[
(c) L.az20s
8. Identify in correct statement
(d) s.an20
[
(a)For symmetrical charge distributions, coulombs law the most provides convenient analysis
compared to Gauss slaw
(b)Gausss law is an alternative statement of coulombs law
(c)According to Gausss law, electrical flux due to any closed surface is equal to the charge
enclosed by the surface.
(d)Gausss law states that v=.D
9. Identify the in correct statement for two point charges Q1=1nC and Q2=2nC that are R distance apart
(a)IfapointchargeQ3=-3nC is placed equidistant from Q1 and Q2, the net force on Q3 is zero
(b)As the distance R increases the force on Q2 decreases
(c) The force on Q1 is same as that of force on Q2


Page 169
(d) the force on both Q1 and Q2 is along the line joining them
10. Value of proportionality constant of Coulomb slaw is
(a) 910-9F/m
(b) 9109m/F
(c) 136p109m/F
(d) 8.8541012F/m
11. A charge Q is uniformly distributed in a sphere of radius a1 the charge density, if the same charge Q is
made to occupy a sphere of Radius a2=a1/4 is
(a) 16timesmore
(b) 4timesmore
(c) 64timesmore
(d) 2timesmore
12. If a pointcharge,-4C is located at (2,-1, 3), the potential at a point (1, 0, 1) assuming zero potential
at infinity is
(a) 14.7mV
[
(b)-14.7kV
(c)-14.7mV
(d) 14.7v
13. Magnitude of Coulombs force between two point charges of 1Coulmb each, separated by 1m in
free space is
(a)136p109N
[
(b)910-9N
(c)9109N
(d)8.85410-12N
14. Point charges 30nC,-20nC and 10nC are located at (-1, 0, 2), (0, 0, 0) and (1, 5,-1) respectively.
The total flux leaving a cube of side 6m centered at the origin is
(a) 30nC
(b) 10nC
(c) 20nC
(b) 8010-10F/m
(c) 80only
16. Identify in correct statement
(d)-20nC
15. Sea water has r=80, the permittivity of sea water is

(a) 7.0710-10F/m
(d) 1/80
(a)For symmetrical charge distributions, coulombs law the most provides convenient analysis
compared to Gauss slaw
(b)Gausss law is an alternative statement of coulombs law
(c) According to Gausss law, electrical flux due to any closed surface is equal to the charge
enclosed by the surface
(d) Gausss law states that V=.D
17. Electro static field being conservative does not mean
(a) The work done inside a closed path inside the field is zero
(b) It is the gradient of a scalar potential
(c) The potential difference between any two points is zero
(d) Its circulation is identically zero
18. A capacitor and resistor are connected in a series with a batter and a switch. The instant after the
switch is closed
(a) the voltage across the resistor is equal to the emf of the battery

Page 170
(b)the voltage across the capacitor is equal to the emf of the battery
(c) the voltage across the resistor is equal to zero
(d)the current is equal to zero
19. Four charges are arranged on the corners of a square as shown below:
At which point (or points) is the electric field equal to zero?

(a)B and E
(b) D and A
(c). A and C
(d). A and B
20. The diagram shows the electric field lines of a negative point charge. The strength of the electric
field is
(a) The greatest at point P.

(b) The greatest at point Q.
(c) The greatest at point R.
(d) The same at the three points.
Answers
1. c
2.c
3.b
4.d
5.b
6.b
7.d
8.b
9.a
10.b
11. c
12.b
13.b
14.b
15.b
16.c
17.c
18.a
19.b
20.a
UNIT-II: ELECTROSTATICS- II
1. Electro static field being conservative does not mean
(a) Its circulation is identically zero

(b) The work done in side a closed path inside the field is zero
(c) The potential l difference between any two points is zero
(d) i t is the gradient of a scalar potential
2. Relaxation time of a dielectric material is given by
(a) /
(b) /
(c) /
(d) /
3. The capacitance of a co-axial cylinder of inner and outer diameters a and b respectively and of
length L is given by
(a) 2Llnba
[
(b) 41na-
(c) Q2Ln (b/a)
(d) 2Llnb/a

Page 171
4.The amount of work done W in moving a point charge Q to a point P where the potential is V is
given by
[
2
(b) Q.V
(a) (Q.V)/2
]
2
(c) Q.V
(d) 12Q.V
5. The dielectric strength of a material is defined as
(a) The maximum Electric field

(b)The maximum energy
(c)The permittivity of the dielectric material
(d)The amount of energy a dielectric can store with in itself
6. Metals have their conductivity "" _________.
(a) >>1
(b) <<1
(c) 0
(d) none of these
7. Insulators have their conductivity "" _________.

(a) >>1
(b) <<1
(c) 0
(d) none of these
8. Electrostatic field is _________ a perfect conductor.

(a) same inside
(b) infinite inside
(c) zero inside
(d) none of these
9. Potential is _________ a perfect conductor.

(a) same inside
(b) infinite inside
[
(c) zero inside
(d) none of these
10. As per Gauss' Law, charge density inside a perfect conductor is zero if E is _________.[
(a) positive
(b) negative
(c) unity
(b) high
(c) both a & b
(b) oxygen
(c) CO2
(b) contrary
(c) same
(b) area(c) volume
15. Capacitor stores energy in _________ field.

(d) none of these
14. Electric polarization of a material is electric dipole moment per unit _________.
(a) length
(d) olcohol
13. The direction of electric dipole moment is _________ applied electric field.
(a) orthogonal
[
(d) can not say
12. Which of the following is not a non-polar dielectric?

(a) water
(d) zero
11. Conductivity of dielectric is _________.

(a) low
(d) none of these

Page 172
(a) electric
(b) magnetic
(c) gravity
(d) none of these
16. Inductor stores energy in ________ field.

(a) electric
(b) magnetic
[
(c) gravity
(d) none of these
17. Which of the following is not an inductor?

(a) toroid
(b) transmission line (c) solenoid
(b) infinity
(c) constant
(b) a small
(c) not a
(b) zero
(d) none of these
20. For a medium to be a quasi-conductor, the dissipation factor should be _________.

(a) infinity
(d) none of these
19. A toroid is _________ solenoid.

(a) a long
(d) none of these
18. Magnetic field at any point inside a long solenoid is _________.

(a)zero
(c) unity
(d) none of these
Answers
1. d
2.b
3.a
4.b
5.c
6.a
7.b
8.c
9.a
10.d
11. a
12.b
13.c
14.b
15.a
16.b
17.d
18.c
19.a
20.c

1. Units of magnetic field intensity are
(a) Webers/meter
(b) Amperes/meter
(c) Amperes
(d)Webers
(c) Ampere/meter
(d) Weber
2. Vector Magnetic Potential has units of

(a)Amperes
(b) Weber/meter
3. Lorentz force equation describes an expression for force

(a) On a moving charge with a velocity v in a magnetic field
(b) On a moving charge in electric and magnetic fields
(c) On a stationary or moving electric charge in an electric field
(d) On a current element Idl in a magnetic field
4. Magnetic energy stored in an inductor (L) carrying current (I) and placed in a magnetic field of
intensity H is given by
[

Page 173

(a)W=12HI2
(b) w=12LH2
(c)W=12LI2
(d)W=12I2H2.
5. The relationship between electric field and time varying potential

(a)E=-V
(b) E=V
(c)E=-V/d
(d)E=V
6. J=E, describing Ohms law cannot be applied to

(a)Conduction currents
(b) Isotropic media
(c)Homogeneous media
(d) Convection currents
7. Identify a non-example of convection current

(a) Current flowing in copper rod
(b) electron beam in a TV tube
(c) Current flowing in vacuum
(d) current through inert gases
8. The capacitance of a capacitor filled with a dielectric material
(a)Is only dependent on the charge on the plates but is independent of the potential difference
between the plates
(b) Is independent of the charge on the plates but is dependent on the potential difference
between the plates
(c)Is independent of both charge on the plates and the potential difference between them
(d)Is dependent on the both charge on the plates and potential difference between them
9. An infinite current element of 10p, amperes is aligned along z-axis. Find the in correct statement
(a)H=-axA/mat(0,5,0)
(b)H=-0.8ax-0.6ayat(-3,4,0)
(c)H=-afA/ mat(5,p4,0)
(d)H=-af at(5,3p2,0)
10. Which of the following is true for electrostatics?

(b) =2 0V
(a) E V=
(c) Both (a) and (b)
(b) Negative
(c) Double
(b) Amperes circuit law
(d) Integral
12. Steady magnetic fields are governed by __________ law.

(a) Biot-Savart law
(d) None of these
11. __________ gradient of magnetic scalar potential gives magnetic field intensity.
(a) Positive
[
(c) both a & b
]
(d)
none of these
13. There will be force of attraction between two current-carrying conductors if the currents are in
__________ direction.
(a) same
(b) opposite
(c) none of these
(c) both a & b
15. Magnetic dipole moment is a product of __________.

(a) current and area
direction
(d) can not say
14. Lorentz force equation comprises __________ and __________ forces.

(a) electric, magnetic (b) mechanical, chemical
(b) area and its direction
(d) none of these

[
(c) current area and its
(d) none of these

Page 174
16. According to Faraday's __________ Law, as long as changes happen in magnetic flux, induced emf
persists.
(a) first
(b) second
(c) third
(b) Lenzs
(d) fourth
17. According to __________ Law, induced current acts to produce an opposing flux.
(a) Bio-savarts
(c) Amperes
(d) Faradays
18. BiotSavart's Law can be applied to __________ length current-carrying conductors. [

(a) large
(b) medium
(c) small
(d) very small
19. Ampere's Circuital Law is analogous to __________ Law in electrostatics.

(a) Lenzs
(b) Gausss
(c) Bio-savarts
(b) outside
(d) Faradays
20. Ampere's Circuital Law can be applied __________ the conductor.

(a) inside
(c) both a & b
(d) none of these
Answers :
1.b
2.b
3.b
4.c
5.a
6.a
7.c
8.d
9.c
10.d
11.b
12.c
13.a
14.a
15.c
16.a
17.b
18.d
19.b
20.c
UNIT-IV: MAXWELLS EQUATIONS (TIME VARYING FIELDS)

1. Identify the incorrect statement
(a)Magnetic force between two current elements is equal to the field produced by BiotSavartslaw
(b)Between two current elements, the force is dependent on the magnetic field based on
Biot-Savart'slaw.
(c)Force between two current carrying conductors is not given by Lorentz'sForceequation.
(d)Force on a current carrying conductor is dependent on the magnetic field in which it is
placed.
2. If the magnetic field H=10axA/m, the flux density in free space is
(a) 4axWb/m2
(b) 1.6axWb/m2
(c) 40axWb/m2
(d) 10axWb/m2
3.Magnetic field in a Toroid is

(a)NI2r
(b) Nil
(c) I2a2
(d) 12
4. Inductance of coil
(a)Induces a reverse voltage to oppose the flow of current due to an applied voltage
(b)Increases the flow of current when a reverse voltage is applied across it
(c)Is directly proportional to the current producing magnetic flux

Page 175
(d)Is inversely proportional to the magnetic flux produced

5. The constant of proportionality of Biot-Savart law is
(a)1/4
(b)1/4F/m
(c)9109F/m
(b) No units
(c) Amperes
(b)F=ILB
(c)F=evB
(d) Weber
7. Lorentz force equation is given by

(a)F=e(E+vB)
(d)1/4A/m
6. The unit of magnetic susceptibility is

(a)Henry/meter
(d)F=e
8. The magnetic field at a point distance away in the normal direction to an infinite current element is
given by
(a)H=I4 (cos2-cos1) a
(b) H=I4a
(c)H=I2a
(d) H=Idlsin42.a
9. Magnetic field intensity due to infinitely long co-axial transmission line at a radial distance, for
a, a being the inner conductors radius, is
(a)I2a2a
(b) 2aa
(c) Ia22a
(d) I22a2a
10. Value of permeability of free space is

(a)410-7H/m
(b)136107H/m
(c)4107H/m
(a)Any discontinuity
(b) Dielectric-Dielectric interface only
(c)Conductor-conductor interface only
(d) Dielectric-Conductor interface only
12. Magnetic vector potential for volume current is expressed as __________.

(b) 024 Jdvrs
(d)36107H/m
11. Normal component of B is continuous at
(a) 04Jdvrs
(c) 02 Jdvrs
(d) 022 Jdvr
13. Magnetization is given as __________.
(a) Volume Dipole moment
(b) Dipole moment Volume
(c) Dipole moment Volume
(d) None of these
14. Amperes Circuital Law is analogous to __________ Law in electrostatics.

(a) Lenzs
(b) Gausss
(d) Faradays
(c) BiotSavarts
15. Amperes Circuital Law can be applied __________ the conductor.

(a) Inside
(b) Outside
(d) None of these
16. Magnetic flux density is the same as __________.

(a) Magnetic induction
(b) Magnetic field strength
(d) None of these
17. Maxwell's equations shelter on __________ law(s).
(a) Faradays
(b) Gausss
(c) Amperes
(d) None of these
18. Conduction current through a wire is __________ displacement current in capacitor.

Page 176
(a) same as
(b) different from
(c) twice of
(d) None of these
19. In empty space, conduction current is __________.
(a) infinity
(b) unity
(c) zero
(d) None of these
20. emf is closed __________ integral of non-conservational electric field that is

generated by battery.
(a) line
(b) surface
(c) volume
(d) None of these
Answers :
1. c
2.a
3.c
4.a
5.b
6.b
7.a
8.b
9.b
10.a
11.b
12.a
13.c
14.b
15.b
16.a`
17.d
18.a
19.c
20.a
UNIT-V: EM WAVE CHARACTERISTICS I

1. Due to inconsistency of Amperes circuital law, the law changed as
a)xH=J+G
b)xH=J-G
c).H=J+G
d)none
2. Following Maxwells equation having following physical significance The total electric
displacement through the surface enclosing a volume is equal to the total charge within the volume
a)xH=J+
3. emf=
D
t
b)xE=-
B
t
c).D= v
d).B=0
d
is given by
dt
a) Amperes circuital law b) Faradays law
c) Coulombs law
a) Zero
b) Infinity.
c) Twice to that of the incident field
d) half to that of the incident field
6. At the Brewster angle, polarization ______________.

b) is reflected at 300. c) is reflected at 900
7. Wave number has units of____________.

b) meter
d). The E is half of the incident field
5. The magnitude of the E at the dielectric-conductor interface.
a) radians
[
b). The E is double of the incident field
c) The H is half of the incident field
a) can not be reflected
d) Gauss law
4. At the dielectric conductor interface

a) The H is double of the incident field.
d) none of these
[
c) radians/meter
d) none of these
Page 177
8. Wave speed in terms of frequency f and wavelength is expressed as _________.

a)f.
b) /f
c) f
b) 0
c) none of these
a) e
-x
+x
-x
b) e
[
d) can not say
10. Wave attenuation is given as ______________.

+x
d) +f
9. For a lossy dielectric medium, ____________.

a) = 0
c) e
d) e
11.In the case of a perfect dielectric medium, phase constant ______________ as conductivity
increases.
a) increse
b) decrese
c) remains unchanged
d) none of these
12. Phase velocity is given as _________.

a)
b) /
[
c) /
d) none of these
13. For a good conductor ________________.

a) [/] = 0
b) [/]<<1
c) [/]>>1
b) [/]<<1
c) [/]>>1
16. Poynting Vector

a) E . H
b) large
c) infinity
c) E - H
d) E X H
17. Power density has _________________.

a) a dc component
[
d) zero
is obtained as
b) E + H
d) [/] =
15. In good conductors, rate of attenuation is __________.

a) small
d) [/] =
14. For a good dielectric medium ____________.

a) [/] = 0
b) a second harmonic component
c) both a & b
d)
none of these
18. Reflection coefficient is __________.
a) 100
[
c) 1
b) =10
d) none of these
19. Standing wave consists of two travelling waves of ____________ amplitudes and _____________
is direction.
a)Unequal, same
b)Unequal, opposite
c)Equal, same d)Equal, opposite
20. SNR ranges from ______.

a) 0 to 1
[
b) 1 to 10
d) 1 to
c) 10 to 100
21.Electric and magnetic fields are related by the following equation

a)
E

H
b)
c)
d)E.H=

Page 178
22. In a good conductor,
23.Identify the region that satisfies the equation

<<1
a)
b)
a) Conductor
c)
b) Dielectric
d)
`[
c) BothA&B
d) none
24.Propagation constant 2 in time varying fields=

a) (
j )( j ) E
b) (
j )( j )
c) (
j )( j )
d) (
j )( j )
25.For a uniform plane wave traveling in Z direction, Ex and Ey having the same amplitude and differed
by a quadrature phase difference .Then the wave is said to have
[
a) Horizontal polarization
b) Circular polarization
c) Linear polarization
d) Elliptical polarization
26.In case of reflection by a perfect conductor, normal incidence, electric field strength
is.at the surface of the conductor and at multiples of half wavelengths from the
surface.
a) Minimum
b) Maximum
c) Zero
d) none
27.Perpendicular polarization is also known as

a)Horizontal polarization.
b) Vertical polarization
c) Both a&b
d) none.
28.Electric field vector is parallel to the boundary surface of perpendicular to the plane of incidence is
called
a) Horizontal polarization.
b) Vertical polarization
c) Both a&b
d) none.
29.The angle of incidence is equal to the angle of reflection is known as

a) Law of sines
b) Snells law
c) Botha&b
b) Etan. J s
Js
c) ETan
d)none
31.Power loss per unit area of a plane conductor is given by( in Watts/ Sq.m)
d) none
30.Surface impedance is defined by
E tan
a) J S

Page 179
a)I2R
2
c) J Seff
Rs
b)V2/R
d)none
32.One of the following gives the measure of the rate of energy flow per unit area at any point.
a)Stokes theorem
b) Poynting theorem
c) Brewster angle
d) Snells law
33. In dielectrics the ratio

a) Power factor
is also known as
b) Dissipation factor c) Phase shift constant d) Angular velocity
Answers:
1. c
2.c
3.b
4.a
5.a
6.a
7.c
8.c
9.b
10.d
11.a
12.c
13.c
14.b
15.c
16.d
17.c
18.c
19.d
20.d
21.c
22.d
23.b
24.a
25.b
26.b
27.a
28.b
29.c
30.a
31.d
32.b
33.b
UNIT-VI: EM WAVE CHARACTERISTICS II

1. The ideal conducting boundary is analogous to
a. The transmission line terminated with its characteristic impedance

b. Open circuit on the transmission line
C. Short circuit on the transmission line
d. The transmission line terminated any load.
2. For normal incidence of the wave on perfect conductor
a. Surface current doesn't exist
b. Surface current exist
c. Conduction current exist
d. Free charge exists on the surface
3. At the dielectric conductor interface the wave
a. Complete transmission takes place
b. Complete reflection takes place
c. Both reflection and transmission takes place
d. No transmission and no reflection take place.
4. At the dielectric conductor interface
a. The H is double of the incident field
b. The E is double of the incident field
c. The H is half of the incident field
d. The E is half of the incident field

Page 180
5. The magnitude of the E at the dielectric-conductor interface
a. Zero
b. Infinity
c. Twice to that of the incident field
d .Half to that of the incident field
6. The conductivity of an ideal conductor is

a. Zero
b. Unity
c. Infinity
d. Two
7. For normal incidence of a wave on dielectric-conductor interface the magnitude of reflection coefficient
is
a. Unity
b. Zero
c. Infinity
d. In between0and1
8. The electric field with in a conductor is

a. Infinity
b. Zero
c. Unity
d. Equal to surface current
9. A standing wave
a. Progresses with less than light velocity
b. Progresses with more than light velocity
c. Progresses with light velocity
d. Does not progress
10. The unit for surface current
a. Ampere
b. Ampere/m
c. Ampere/m2 d. ampere/m3
11. In the case of perpendicular polarization
a. The H is perpendicular to the plane of incidence and parallel to the reflecting surface
b. The E is perpendicular to the plane of incidence and parallel to the reflecting surface
c. The H is parallel to the plane of incidence and perpendicular to the reflecting surface
d. The E is parallel to the plane of incidence and perpendicular to the reflecting surface
12. As per the boundary condition
a. The normal components of E are continuous across the boundary.

b. The tangential components of E are continuous across the boundary.
c. The tangential components of Discontinuous across the boundary.
d. The normal components of H is continuous across the boundary
13. The absorption of power in propagation through the dielectric is
a. High
b. Low
c. Zero
d. Infinity
14. The dimension of a reflection coefficient is

a. A/m
b. V/m
c. No unit
d. V/A
15. The another name of Brewster angle is

a. Angle of reflection
b. polarizing angle

Page 181
c. Angle of transmission
d. Non polarizing angle
16. During total internal reflection wave under goes

a. A phase change
b. Polarization change
c. Magnitude change
d. No change in the phase
17. The Total internal reflection can take place
a. If the wave travels from Rarer to Denser medium

b. If the wave travels from Denser to Rarer medium
c. If the wave travels from Denser to Denser medium
d. If the wave travels from Rarer to Rarer medium
18. Under total internal reflection the reflection coefficient for both polarizations is
a. A real quantity
b. An imaginary quantity
c. A complex quantity
d. May be real or imaginary quantity
19. For total internal reflection the fields in the second medium
a. Vanish completely
b. Do not vanish
c. No change with angle of incidence d. Infinite at the interface

20. When incident angle is Brewster angle then
a. Complete reflection takes place
c.Partial reflection only takes place
b. No reflection takes place

d. Partial transmission only takes place
Answers:
1.c
11.b
2.b
12.b
3.b
13.b
4.a
14.c
5.a
15.c
6.c
16.b
7.a
17.a
8.b
18.b
9.d
19.c
10.b
20.b

1. The ideal conducting boundary is analogous to
(a). The transmission line terminated with its characteristic impedance

(b). Open circuit on the transmission line parallel to the reflecting surface
. Short circuit on the transmission line
(d). The transmission line terminated with any load.
2. In a transmission line the voltage and current standing waves are
(a) 00out of phase along the line
(b) 2700out of phase along the line
(c) 900out of phase along the line
(d) 1800 out of phase along the line
3. For a lossless line the characteristic impedance is

(a)Z0= Sqrt (LC)
(b) R0=Sqrt(1/LC)
[
(c)R0=Sqrt(L/C)
4. Hysteresis and eddy current losses in loading coils lead to

(d)Z0=Sqrt(C/L)
[

Page 182
(a)Decrease in R
(b) Decrease in L
(c) Increase in R
(d) Increase in L
5. A transmission line operating at 1GHz has L=1micro henry/m, C=1pF/m,R=G=0.Then its

characteristic admittance is
(a)10mhos
[
(b)0.001mhos
(c)0.1mhos
(d)0.01mhos
6. The SWR of a transmission line which is terminated with its characteristic impedances given by
(a)infinity
(b)zero
(c)1
(d)2
7. Which of the following is a one to one transformer?

(a) line
(b) /2line
(c) /8line
(d) /4line
8. The VSWR in a short circuited loss less transmission line equals

(a) Infinity
(b) unity
(c) zero
(d) none of above
9. The velocity factor of a transmission line
(a) is always greater than unity

(b) Depend upon the permittivity of the surrounding medium
(c) Is lease for air medium?
(d) Is governed by skin effect
10. In case the characteristic impedance of the line is equal to the load impedance [
(a) All the energy will pass to the earth

(b) All the energy will be lost in transmission losses
(c) The system will resonate badly
(d) All the energy sent will be absorbed by the load.
11. When a line is called as a flat line then standing wave ratio is
(a). Unity
(b). Zero
(c). Infinity
(d). Two
12. The unit for attenuation constant is

a. dB/m
b. Radian/m
c. Volt/m
d. Amp./m
13. The ratio of positively traveling voltage wave to positively traveling current wave at any point on
the transmission line is known as
a. Load impedance
b. Characteristic impedance
c. Line impedance
d. Source impedance
14. in a transmission line when termination impedance is equal to characteristic impedance of that line then
The reflection coefficient is
a. Unity
b. Infinity
c. Zero
d.Equal to transmission coefficient
15. For a low loss line the phase velocity is

a. Increases with frequency
b. Decreases with frequency

Page 183
c. Approximately constant
d. Increases with square of frequency
Answers:
1.c
2.c
3.a
4.b
5.b
6.b
7.b
9.b
10.b
11.a
12.a
13.b
14.c
15.c
8.c
UNIT-VIII: TRANSMISSION LINES II

1. Quarter wave transformer is
(a)Frequency sensitive device
(b) Current sensitive device
(c)Voltage sensitive device
(d) Power sensitive device
2. On a smith chart for x=0circles the center is at

(a)(0, )
(b)(1, 1)
[
(c)(1, 0)
(d)(1, )
3. In the single stub matching the location of the stub changes with
(a)Frequency
(b) Source impedance
(c)Characteristic impedance
(d) Load impedance
4. A certain low loss line has Z0=400ohms.ForZL=200ohms, the SWR is

(a) 4
(b) 2
(c)1/2
5. For a properly terminated line

(a) ZR=ZO
(b) Z/R > ZO
(c) ZR < ZO
6. For minimum attenuation

(a).C=LG/R
(d)1/3
(d) ZR =Z0 = 0.
[
(b).C=LR/G
(c).C=G/LR
7. In the single stub matching the location of the stub changes with
a. Load impedance
b. Source impedance
c. Characteristic impedance
d. Frequency
8. A stub with a short circuited load offers

a. Capacitive reactance
b. Inductive reactance
c. Pure resistance
d. Impedance
9. By connecting the stub at the load point
(d).C=R/LG
[
a. Matching cannot be obtained

b. Matching can be obtained
c. Matching can be obtained for a particular frequency
d. Matching cannot be obtained for a particular frequency

Page 184
10. A short circuited stub is ordinarily preferred to an open circuited stub because
a. It has lower loss of energy due to radiation
b. It has higher loss of energy due to radiation
C.It has complete loss of energy due to radiation
d. Its length is small.
11. A single stub matching is a
a. Narrow band system
b. Broad band system
c. Pass band system
d. Band reject system
12. A certain low loss line has=400ohms.For=200 ohms, the SWR is

a.1.
b.1/3
c.2
d.4
13. Two very long loss less cables of Characteristic impedances of 36ohms and
100ohms respectively are to be joined for Reflection less transmission.
a.25ohms
b.50ohms
c.75ohms
d.100ohms
Answers:
1.b
2.b
3.c
4.c
5.a
6.a
8.b
9.a
10.a
11.a
12.c
13.b
7.d

Page 185
ESSAY TYPE
QUESTIONS
Essay Questions
ESSAYTYPEQUESTIONS
UNITI:EECTROSTATICS-I
1. What are the properties of dielectric materials?
2. Define polarization, P
3. What are the magnitudes of electric flux densities and polarization for a dielectric material in
which E=150kV/m. Electric susceptibility of the dielectric material is 4.75.
4. Prove J=V from fundamentals.
5. Find out electric flux density in free space if the electric field, E=6ax-2ay+3az,V/m also find
V.
6. Define potential at a point and obtain its expression.
7. The potential at a point A is 10volts and at B is 15 volts. If a charge, Q=10 C is moved from A
to B, what is the work required to be done.
8. Determine the Electric Field "È' due to i. Point charge Q ii. Line charge l
iii. Surface charge" s at a point distance r' from the source.
9. Evaluate the Coulomb's force, Electric Field intensity and potential due to a Line charge ` l'
10. Explain about equipotential surfaces.
UNIT II: EECTROSTATICS- II

1. State equation of continuity and prove it.
2. What are the different types of current densities and define them.
3. Define the poisson's "and Laplace's" equation.
4. Obtain expression for the capacitance of
i. a parallel plate capacitor and
ii.a coaxial capacitor.
5. What is an isotropic and homogeneous medium?
6. What is a lossy and lossless medium?
7. Explain the term Conduction Current Density".
8. State and explain Boundary conditions for electric field at a boundary surface
Between a conductor and dielectric boundary.
9. A parallel plate capacitor with plate area of 5.0cm2 and plate separation of 3.0 mm has a voltage
50 sin103 t volts applied to its plate. Calculate the Displacement current assuming "r=2"
UNIT III: MAGNETOSTATICS

1. What is the inductance of a solenoid and write the expression for its inductance
And also for magnetic field in a solenoid.
2. A solenoid has 400turns with a length of 2m. It has a circular cross-section
Of 0.1m Find its inductance.
3. Define magnetic flux density in two different forms.

Page 187
ESSAY Questions
4. If magnetic field, H=3ax+2ay,A/m exists at a point in free space, what is

Magnetic flux density at the point.
5.
What is the inductance of a pair of transmission lines separated by1.868m, if the
diameter of the each wire is 0.01m and the medium between the lines has =2. The length of line is
10m.
6. Describe the characteristics of paramagnetic materials.

7.Anisotropic material has a magnetic susceptibility of 3 and the magnetic flux Density,
B=10yaxmwb/m2. Determine r, , Jb, J, M and H.
1. Verify whether the fields E=10sinsintay and H=10 coscostaz satisfy the Maxwells
equations.
2. If E=2cos(tz)ax and H=2cos(tz)ay, find in terms of o, 2o so that the fields satisfy
all Maxwells equation.
3. Differentiate conduction and displacement current densities.
4. In a medium, conduction current density given by J=3.0 sin(t-10z)ay+cos(t-10z)azmA/m2,
find volume charge density.
5. A plane wave with E=2.0V/m and has a frequency of 3 State boundary conditions in scalar
form.
6. In region1 (z<0) and region2 (z>0), 1=2=0.E1=1 ax+2ay+3az, and E2 and D2.r1=1 and
r2=2.
7. State and prove Boundary Conditions for electric field between a conductor and a dielectric.
8. State and explain Maxwell's equations obtained from Faraday's and Ampere's laws and their
Magnetic field concepts & relationship.
9. Write Maxwells equations for Time Varying fields in integral and difierential form. Discuss the
difierence between static fields and Time Varying fields.
UNITV: EM WAVE CHARACTERISTICS-I

1. A plane wave with E=2.0V/m and has a frequency of 300MHz. It is moving in free space
impinging on a thick copper sheet located perpendicularly to the direction of propagation.Find
(a)E and H at the plate surface
(b)Depth of penetration
(c)The surface impedance.
2. Derive the expression for surface impedance of a good conductor.
3. What is the frequency above which the materials cannot behave as a good conductor? If a plane
wave of 15MHz is incident on the material, upto what depth can the wave penetrate the material,
and what will be the wavelength of the wave in the material.
4. A uniform plane wave in empty space has the electric field E(z)=ax100e
-j0z
V/m.

Page 188
ESSAY Questions
Its frequency is 20MHz:

(a)What is its direction of travel and amplitude?
(b)Find B,H
(c)Express E,B, H in real-time form
UNIT VI : EM WAVE CHARACTERISTICS-II
1. Define intrinsic impedance of free space, and phase constant, .
2. List out propagation characteristics of EM waves in free space.
3. Explain the reflection of uniform plane waves with normal incidence at a plane dielectric
boundary.
4. What is a standing wave? Define standing wave ratio? What is its relationship with the
reflection coefficient?
5.
For a plane wave reflecting at perfect dielectric, with normal incident
6. Define complex Poynting vector and explain.
7. A plane wave of frequency=2MHz is incident upon a copper conductor normally.The wave has
an electric field amplitude of E=2mV/m. The copper has r=1,2 r=1 and =5.8107mho/m.
Find average power density absorbed by copper.
8. What is skin effect? What is skin Depth? What is its relation with attenuation constant,
conductivity and frequency? Derive the expression for skin depth.
9. Derive the Reflection coefficient for a parallel polarized wave at an angle of incidence between
two media (losslessand1=2=0)
10. Define Brewster's angle and obtain an expression for the same in terms of Medium parameters.
UNIT- VII: TRANSMISSION LINES-I

1. What is the difference between lumped parameters and distributed parameters? Discuss in detail.
2. Explain about the parameters of the open wire line at high frequencies?
3. List out the applications of transmission lines.
4. From the fundamental voltage & current equations of transmission line, derive expression for
input impedance Zin of the line. Modify the expression for lossy & lossless cases.
5. Prove that a finite line terminated in its characteristic impedance behaves as
An infinite line?

Page 189
ESSAY Questions
UNIT- VIII: TRANSMISSION LINES-II

1. Calculate the characteristic impedance, the attenuation constant and phase constant of a
transmission line if the following measurements have been made on the line ZOC=550 and
ZSC=660
2. Derive Zin for a lossless transmission line when it is terminated by a:
(a)ZL
(b)open
(c)short circuit.
Draw the suitable sketches.
3. Derive the condition form in attenuation with
(a)L variable and
(b)C variable.
4. Find the characteristic impedance of a line a 1600Hz if the following measurements have been
made on the line at1600Hz, ZOC=750 and ZSC=500.
5. Explain the designing of Double Stub?
6. Write short note on: (a) Lossless transmission line
(b)Distortion less line.
7. A transmission line of length 0.40 has a characteristic impedance of 100 and is terminated is a
load impedance of 200+j180. Find the:
(a)Voltage reflection coefficient(b)VSWR
(c)Input impedance of the line by using smith chart.
8. In a transmission line,name the types of distortions that occur and explain.
9. To avoid distortion, what is the condition for a Distortion less line" and derive
An expression for the same in terms of line parameters.
10. Explain the constructional features of Smith's chart and its importance.

Page 190
ASSIGNMENT
QUESTIONS
ASSIGNMENTQUESTIONS
UNITI:EECTROSTATICS-I
1. State and explain Gauss's law and prove that
v
2. Define Electric field Intensity" and` potential V' due to\ point charges" and line charges"
& explain.
3. Find the È' field intensity on the axis of a circular ring carrying a charge density
`Q'C/m.
4. What are Linear, Homogeneous and isotropic media?
Explain\Point charge",\ Line charge" and\ Surface charge" distributions and theÈ'&V'
expressions also to the above, given examples of their applications
UNIT II: EECTROSTATICS- II
1. Define the poisson's "and Laplace's" equation.
2. Obtain expression for the capacitance of
i. A parallel plate capacitor and
ii.
A coaxial capacitor.
3. What is an isotropic and homogeneous medium?

4. What is a lossy and loss less medium?
5. Explain the term Conduction Current Density
UNITIII:MAGNETOSTATICS
1. Define magnetic flux density in two different forms.
2. If magnetic field, H=3ax+2ay,A/m exists at a point in frees pace, what is
Magnetic flux density at the point.
3. What is the inductance of a pair of transmission lines separated by1.868m,
If the diameter of the each wire is 0.01m and the medium between the lines
Has =2m. The length of line is 10m.
4. Describe the characteristics of paramagnetic materials.
5. An isotropic material has a magnetic susceptibility of 3 and the magnetic flux
Density, B=10yax mwb/m2. Determine r, , Jb, J, M and H.
6. Find the electromagnetic field intensity atP(1,2,3) in Cartesian coordinates
Caused by a current filament carrying a current of 10Amp along Z-axis, if the
Filament extends from

Page 192
1. Find amplitude of the displacement current density, Jd adjacent to TV receiver when the
magnetic field of FM signal is H=2:0cos [3.12(3*108t-y)]ax A/m.
2. Find Jd in a metallic conductor at 50Hz if r=1,r=1,=5.8*107mho/m and
J=sin(377t-117z)axmA/m2. If E=2cos(tz)ax and H=2cos(tz)ay, find in terms
of o,2 o so that the fields satisfy all Maxwells equation.
3. Differentiate conduction and displacement current densities.
4. In a medium, conduction current density given by J=3.0sin(t-10z)ay+cos(t10z)azmA/m2, find volume charge density.
5. A plane wave with E=2.0V/m and has a frequency of 3 State boundary conditions in
scalar form.
6. In region1 (z<0) and region2 (z>0), 1=2=0.E1=1ax+2ay+3az, and E2 and D2. r1=1
and r2=2.
UNIT V:EM WAVE CHARACTERISTICS-I

1. Derive the expression for surface impedance of a good conductor.
2. What is the frequency above which the materials cannot behave as a good conductor? If
a plane wave of 15MHz is incident on the material, upto what depth can the wave
penetrate the material, and what will be the wavelength of the wave in the material.
3. A plane wave with E=2.0V/m and has a frequency of 300MHz. It is moving in free space
impinging on a thick copper sheet located perpendicularly to the direction of
propagation. Find
(a)E and H at the plate surface
(b)Depth of penetration
(c)The surface impedance
UNIT VI: EM WAVE CHARACTERISTICS-II
1. A wave is incident from A iron to a perfect conductor normally. Evaluate the reflection
coefficient.
2. What is surface impedance and explain the power loss between Air & a conductor
surface at normal Incidence.
3. Define Depth of propagation"

Page 193
4. Explain Reflection and Refraction "of plane waves.

5. Obtain an expression for the Reflection and Transmission coefficients of uniform waves
between two media for normal incidence.
6. What are the conditions to be satisfied for
i. Brewster's angle
ii.Critical angle. Explain in detail.
UNIT- VII: TRANSMISSION LINES-I
1. List out the applications of transmission lines.

2. From the fundamental voltage & current equations of transmission line, derive
expression for input impedance Zin of the line. Modify the expression for lossy &
lossless cases.
3. What is the difference between lumped parameters and distributed parameters? Discuss
in detail.
4. Explain about the parameters of the open wire line at high frequencies?
UNIT- VIII: TRANSMISSION LINES-II

1. A load Impedance of 90-j25 is to be matched to a 50 line using single stub matching.
Find the length and position of the stub.
2. Compare the impedance matching techniques such as
i. /4
ii. Single Stub
iii. Double Stub on transmission lines
****THE END***

Page 194
PRINCIPLES OF ELECTRICAL
ENGINEERING
Mr.Bhanu ganesh LUKKA
Asst. Professor
COURSEFILE
Department of

Sponsored by
COURSE
OBJECTIVE
PRINCIPLES OF ELECTRICAL ENGINEERING
Course Objective
COURSE OBJECTIVE
The course provides a comprehensive understanding of the basic theory of networks like Two
port parameters, filters, attenuators,transients, transformers and dc machines in main , besides covering
induction motors toward the end. Starting by explaining the fundamentals of transients like initial
conditions,response of series RL,RC,RLC under transient conditions, the course helps in developing the
understanding about filter networks, two port network networks, attenuators and construction and
operation of machines in detail and precise.
To understand the principles of operation, electrical characteristics and circuit models of the
most important electrical devices, and to be able to use this knowledge to analyze and design basic
electrical application circuits. To extend the understanding of how electrical circuits and their functions
fit into larger electrical systems in real time environment.
A review of machines is introduced in this course. An introduction to dc machines consisting
of both generators and motors which help to the construction, working and analysis of these devices
have been mentioned.
Apart from dc machines, ac machines like transformers and single phase induction motors have
also been introduced whose principle of operation is must to be studied by every engineer as we come
across or use these devices somehow in our routine life.
II Year B.Tech. 2nd semester

Page 197
Syllabus
Syllabus
SYLLABUS
UNIT-I: Transient Analysis( first and second order circuits)
Transient response of RL,RC series RLC circuits for DC excitation, initial conditions, solution
using differential equations approach and Laplace transform method.
UNIT-II: TWO PORT NETWORKS

Impedance parameters, Admittance parameters, Hybrid parameters, Transmission parameters,
conversion of one parameter to other, conditions for reciprocity and symmetry, interconnection of two
port networks in series, parallel and cascade configuration, image parameters, illustrative problems
UNIT III : FILTERS.

Classification of filters, filter networks , classification of pass band and stop band, characteristic
impedance in pass band and stop bands, constant k-low pass filter, high pass filter , m-derived Tsection, band pass filter and band elimination filter, illustrative problems.
UNIT-IV: SYMMETRICAL ATTENUATORS:

Symmetrical attenuators- T-Type , -type, bridged T type attenuator, lattice attenuator
UNIT V :DC MACHINES:
Principle of operation of DC Machines- EMF equation Types of generators Magnetization and load
characteristics of DC generators
UNITVI :D.C. MOTORS:

DC Motors Types of DC Motors Characteristics of DC motors 3-point starters for DC shunt motor
Losses and efficiency Swinburnes test Speed control of DC shunt motor Flux and Armature
voltage control methods.
UNITVII :TRANSFORMERS:
Principle of operation of single phase transformer types Constructional features Phasor diagram
on No Load and Load Equivalent circuit. Losses and Efficiency of transformer and Regulation OC
and SC tests Predetermination of efficiency and regulation

Page 199
Syllabus
UNITVIII:SINGLE PHASE INDUCTION MOTORS:

Principle of operation - Shaded pole motors Capacitor motors, AC servomotor, AC tachometers,
Synchros, Stepper Motors Characteristics
TEXT BOOKS:
1.
Circuit Theory by A. Chakrabarthy,Dhanpat rai &Co.(P) Ltd.
2.
Principles of Electrical Engineering by Sudhakar and Shyammohan Pillai,Tata McGraw Hill
publications
3.
Introduction to Electrical Engineering by Naidu and Kamakshaiah,
4.
Networks, Lines and Fields Jhon.D.Ryder, 2.ed208 (Reprint), PHI.
REFERENCE BOOKS:
1.
Network Analysis by N.C.Jagan, C. Lakshminarayana, BS Publications
2.
Engineering Circuit Analysis W.H.Hayt ad J.E Kemmerly and S.M. Durbin, 6 ed.., 2008,
TMH.
3.
Network Analysis and Synthesis C L Wadhwa, e ed 2007, New Age International

publishers.
4.
Electric Circuits Nilsson, Riedel, 8 ed PE.
STUDENT'S
SEMINAR
TOPICS
Seminar Topics

1.
Analysis of a series RC circuit during transient condition .
2.
Design of a two port network when any two two-port networks are in cascade.
3.
Design of a Band pass filter
4.
Design of a bridged T-attenuator.
5.
Construction of a DC machine.
6.
Characteristics of dc generators.
7.
Working principle of a dc motor.
8.
Characteristics of dc motors.
9.
Construction of a single phase transformer.
10.
Analysis of equivalent circuit of a single phase transformer.
11.
Phasor diagram of a Transformer under on-load.
12.
Construction of a stepper motor with characteristics.
13.
Equivalent circuit of a Transformer.

Page 202
LECTURE PLAN
Lecture Plan
LECTURE PLAN
S.No
1.
2.
3.
4.
5.
6.
NAME OF THE TOPIC
No of
Periods
Method of Teaching
Introduction to PEE
1
UNIT 1: TRANSIENT ANALYSIS
Transient response, initial conditions
1
Transient response of RL circuit using differential equations
1
Black board, Chalk
approach and Laplace transform method.
Problems on transient response of RL circuit.
1
Transient response of RC circuit using differential equations
approach and Laplace transform method.
Problems on transient response of RC circuit.
7.
Transient response of RLC circuit using differential equations

approach and Laplace transform method.,
8.
Problems on series RLC circuit.
UNIT 2: TWO PORT NETWORKS

Difference between a one port, two port network, Impedance
1
parameters, Admittance parameters
Text books referred
--Network analysis by N.C.Jagan- chapter 8

Principles of Electrical Engineering by
Sudhakar and ShyamMohan-chapter 1
12.
Problems on h , ABCD parameters
Black board, chalk,
13.
conditions for reciprocity and symmetry for Z,Y parameters.

conditions for reciprocity and symmetry for h, ABCD
parameters.
Inter relation ships between Z,Y, h,ABCD parameters
Inter relation ships between Z,Y, h,ABCD parameters

Previous question papers, Principles of
Electrical Engineering by Sudhakar and
ShyamMohan-chapter 2, Circuit Theory by
A.Chakraborthy-chapter-12
Previous question papers, Principles of
Electrical Engineering by Sudhakar and
ShyamMohan-chapter 2, Circuit Theory by
A.Chakraborthy-chapter-12
Circuit Theory by A.Chakraborthy- chapter 12
1
1


9.
10.
11.
14.
15.
16.
Problems on Z,Y parameters

Hybrid parameters, Transmission parameters
Black board, chalk,

Page 204
17.
18.
Lecture Plan
interconnection of two port networks in series, parallel

configuration, problems.
interconnection of two port networks in cascade configuration,
problems
19.
Image parameters
20.
Unit test-I,II
21.
Classification of filters, pass band and stop band, filter networks
22.
Expression of filter networks
23.
Classification of pass and stop bands
24.
constant k-low pass filter, problems
25.
constant k-high pass filter,problems
26.
constant k-band pass filter, problems
27.
constant k-low pass filter, problems
28.
m-derived filters
Black board, Chalk
1
UNIT-3: FILTERS

Sudhakar and ShyamMohan-chapter 2,
Principles of Electrical Engineering by Sudhakar
and ShyamMohan-chapter 2
UNIT-4 : ATTENUATORS
29.
Introduction,attenuation constant, Symmetrical T attenuator
Black board, Chalk
30.
Symmetrical attenuators- -Type,problems
Black board, Chalk
31.
bridged T type attenuator
Black board, Chalk
32.
lattice type attenuator
Black board, Chalk
33.
Problems on bridged T and lattice attenuators
Black board, Chalk
34.
UNIT-5 : DC MACHINES
Introduction, review on basic concepts, basic laws required for
1
Black board, Chalk
machines.
1
Principle of operation of DC Machines
35.

Introduction to Electrical engineering by Naidu
and Kamakshaiah

Page 205
Lecture Plan
36.
Construction of a dc machine
37.
single turn generator
LCD Projector
Black board and Chalk and
LCD Projector
LCD Projector
38.
EMF equation, problems
39.
Types of generators-derivations
40.
Problems on types of generators
41.
Problems on types of generators
42.
Characteristics of dc shunt generator
43.
Characteristics of dc series generator
44.
Characteristics of dc compound generator
and ShyamMohan-chapter 5,previous papers
UNIT 6: DC MOTORS
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
Principle of operation of DC Motors
Types of DC Motors
Black board and Chalk,

LCD Projector
Characteristics of DC motors
Problems on types of motors
Black board and chalk
3-point starters for DC shunt motor
Black board and chalk
Black board, Chalk
Losses in dc machines
efficiency calculations
Problems on efficiency calculations
Swinburnes test , problems
Flux and Armature voltage control methods


Page 206
55.
Problems on speed control methods
56.
Unit test in units 5,6
57.
58.
59.
Principle of operation of single phase transformer

Constructional features
Types of transformers
Emf equation of a single phase transformer, problems
Lecture Plan
1
UNIT 7 : TRANSFORMERS
1
LCD Projector
1
LCD Projector
board , Chalk, Projector,
1
Transformer models
Phasor diagram of a transformer on Load
Equivalent circuit. ,problems
Losses and Efficiency of transformer
OC and SC tests
68.
Problems on OC and SC tests
69.
UNIT-8 : SINGLE PHASE INDUCTION MOTORS

Principle of operation of single phase induction motors
Black board , Chalk, LCD
1
Projector
Shaded pole motors
1
60.
61.
62.
63.
64.
65.
66.
67.
70.
71.
72.
Phasor diagram of a Transformer on No Load
Regulation
Problems on efficiency and regulation
Capacitor motors, AC servomotor

AC tachometers, Synchros

Page 207
73.
74.
75.
76.
77.
Lecture Plan
Synchros, Stepper Motors

1
1
1
1

LCD Projector

Notes
Notes
Notes
Notes

Page 208
LEARNING
OBJECTIVES
Learning Objectives
LEARNING OBJECTIVES
UNIT-I: TRANSIENT ANALYSIS( first and second order circuits)
- Explain the meaning of transient response
- Explain the meaning of steady state response
- Derive the initial conditions for different circuits.
- Solve series RL,RC and RLC circuits to get transient response with dc excitation.
- Obtain the different differential equations for different combinations of circuits.
- Determine the time constant of the given circuit and its effect on transient response
- Difference between transient response and steady state response.
UNIT II:TWO PORT NETWORKS

- Explain the difference between one-port and two port networks.
- Define the different sets of two port parameters
- Explain the open circuit impedance parameters
- Explain the short circuit admittance parameters
- Explain the ABCD parameters.
- Explain the hybrid parameters of two port networks.
- Derive the conditions of reciprocity and symmetry.
- Determine the relationship between one set of parameters with other types of parameters
- Analyze the two port networks when connected in series.
- Analyze the two port networks when connected in parallel.
- Analyze the two port networks when connected in cascade.
- Derive the image parameters of a two port network when it is terminated.
UNIT 3: FILTERS.
- Explain the definitions of different types of filters- low pass, high pass and band pass filters
- Derive the expressions of characteristic impedance, propagation constant of filter networks.
- Design the constant K low pass filter
- Design the m-derived T and sections

Page 210
Learning Objectives
- Design the constant K high pass filter.

- Design the band elimination filter.
- Design the band pass filter.
UNIT-IV: SYMMETRICAL ATTENUATORS:

-Define an attenuator
-analyze the operation of T type attenuator
- analyze the operation of type attenuator
- analyze the working of a bridged T type attenuator
- analyze the operation of a lattice attenuator.
UNIT-V: DC MACHINES
- Identify the difference between generator & motor principle
-Explain the principle of operation of a dc machine
- Explain the basic laws defined behind the operating principle
- Explain the construction details of dc machine
- derive the expression of emf of a dc machine.
-analyze the difference between wave and lap windings
- Identify the types of generators
-analyze the equations governing the shunt , series and compound generators
-Explain the Characteristics of dc generators
UNIT-VI:DC MOTORS
- Explain the Principle of operation of a dc motor
- define the different laws used in explaining the principle of operation
- Explain types of dc motors
- Explain the characteristics of dc motors
- explain the starting of dc motors
- Define the various Losses in dc motors
- Define the efficiency in dc motors
-derive the condition for maximum efficiency in dc motors.

Page 211
Learning Objectives
-determine the efficiency under no load conditions.

- Explain the various speed control methods of a dc motor.
UNIT-VII: TRANSFORMERS
- Explain the operation of single phase transformer
-explain the difference between ideal and practical transformers.
- Define the types of single phase transformers
- Explain the phasor diagram of Ideal transformer on No Load and Load
- Explain the Equivalent circuit of a single phase transformer
- define the different types of Losses in a transformer
- Define the efficiency of a single phase Transformer
- Define the regulation of a single phase Transformer
- Explain the Phasor diagram on Load under lagging, leading and u.p.f power factors
-determine the parameters of a transformer by conducting open circuit test
-determine the parameters of a transformer by conducting short circuit test
UNIT-VIII : SINGLE PHASE INDUCTION MOTORS:

- Explain the Principle of operation of single phase induction motor
-Explain the difference between the shaded pole, capacitor start & capacitor run motor
- Explain the stepper motor characteristics
- Explain the Principle of operation of Shaded pole motor
- Explain the Principle of operation of Capacitor motors
- Explain the of operation of AC servomotor,
- Explain the Principle of operation of AC tachometers
- Explain the Principle of operation of Synchros
- Explain the applications of different types of motors.

Page 212
OBJECTIVE
TYPE
QUESTIONS
Objectives Type Questions

Unit I: Transient analysis
1. Capacitor acts like for the a.c. signal in the steady state
a) open b)closed c) not open not close d)none.

2. Double energy transient are produced in circuits consisting of
a) two or more resistors
b) resistance and inductance
c) resistance and capacitance
d) resistance ,inductance and capacitance
3. The transient current in a loss free L-C circuit when excited from an ac source is a /an -------sine
wave
a) over damped
b) under damped
c) un damped
b) R>2L/C
d) critically damped
4. The Transient current in an R-L-C circuit is oscillatory when

a) R=0
c) R<2L/C
d) R=2L/C
5. Which of the following does not have the same units as the others? The symbols have their usual
meanings
a) L/R
c) LC
b)RC
d) 1 / LC
6. A DC voltage source is connected across a series RLC circuit, under steady state conditions, the
applied DC voltage drops entirely across the
a) R only
b) L only
c) C only
d) R & L combinations
7. Consider a DC voltage source connected to a series RC circuit. When the steady state reaches, the
ratio of energy stored in the capacitor to the total energy supplied by the voltage source is equal to [
a) 0.362
b) 0.500
c) 0.632
d) 1.00
8. For a second order system, damping ratio is 0<<1, then the roots of the characteristic polynomial
are
a) real but not equal
b) real and equal
c) complex conjugates
9. The response of an LCR circuit to a step input is
d) imaginary
If the T F has
a) over damped
1) poles on ve real axis
b) critically damped
2) poles on imaginary axis
c) oscillatory
4) poles on +ve real axis
3) multiple poles on +ve real axis

abc
5) multiple poles on -ve real axis

a) 1 2 5 b) 1 5 2 c) 3 4 5 d) 1 5 4
10. A rectangular voltage pulse of magnitude V and duration T is applied to a series combination of R
,C. The max voltage developed across the capacitor is

Page 214
a) V(1-e-T/RC)
b) VT/RC
c) V
d) Ve-T/RC
11. An ideal voltage source will charge an ideal capacitor

a) in infinite time
b) exponentially
c) instantaneously
d) none
12. Energy stored in a capacitor over a cycle, when excited by an a.c source is
a) same as that due to a dc source of equivalent magnitude
b) half of that due to a dc source of equivalent magnitude
c) zero
d) none
13. An inductor at t=0 with initial current I0 acts as

a) Short b) open c) current source d) voltage source
14. An inductor L carries steady state current I0, suddenly at time t=0 the inductor is removed from
circuit and connected to a resistor R. The current through the inductor at time t is equal [ ]
a) I0e-Rt/L
b) I0 (1-e-Rt/L)
c) I0e+Rt/L
d) I0 (1-e+Rt/L)
15. Transient current in a circuit results from

a) voltage applied to the circuit
b) impedance of the circuit
c) changes in the stored energy in inductors and capacitors

d) resistance of the circuit
16. If an RL circuit having angle is switched in when the applied sinusoidal voltage wave is passing
through an angle , there will be no switching transient if
a) -=0
b) +=0
c) -=90
d) +=90
17. A series R C L circuit is driven by an ac voltage source. Then the voltage across the following
elements or the pair of elements cannot exceed the applied voltage
a) C
b)L
c) R
b) V
c) cant find
d) R and L
18. What is vc (o+ )?
a) 0
d) none

Page 215
19. When a current source of value 1 is suddenly connected across a two terminal relaxed RC network at
time t=0, the observed nature of the voltage across the current source is shown in the fig. The RC network is
[
a) a series combination of R and C

b) a parallel combination of R and C
c) A series combination of R and parallel combination of R and C
d) a pure capacitor
20. In the circuit shown, switch S is closed at time t=0. After some time when the current in the inductor was
6A, the rate of change of current through it was 4A/s. The value of the inductor is
a) Indeterminate
b) 1.5H
c) 1.0H
d) 0.5H
ANSWERS:
1 (c)
2 (d)
3 (c)
4 (c)
5 (c,d)
6 (c)
7 (b)
8 (c)
9 (b)
10 (a)
11 (c)
12 (c)
13 (c)
14 (a)
15 (c)
16 (a)
17 (c)
18 (b)
19 (c)
20 (d)

Page 216
UNIT II: Two port Networks

1. In a two port network, condition for reciprocity in terms of h-parameters is
(a) H12=h21
(b) h11=h22
(c) h11+h12=0
(d) h12=-h21
2. A two port network is defined by I1=2V1+V2, I2= 2V1+3V2. Then Z12 will be _____ ohms.[
(a)-2
(b) -1
(c) -0.5
(c) h11h22-h12h21=1 (d) Y11Y22-Y12Y21 =1
4. A two port network is a network inside a black box and has only _____ terminals
(a) 2
(d) -0.25
3. A two port network is symmetrical if

Z11-Z22=1 (b) AD-BC=1
(b) 2 pairs
(c) 2 pairs of ports
(d) 4 pairs of
5. Number of possible combinations generated by four variables taken two at a time in a two-port
network is
(a) 4
(b) 2
(c) 6
(b) 1/5
(d) 8
6. If Z11=2 , Z12=Z21= 1 , Z22=3, the determinant of admittance matrix is

(a) 5
(c) 1
(d) 2
7. Two port networks are connected in cascade. The combination is to be represented as a single twoport network. Parameters of the network are obtained by multiplying individual
(a) Z-parameter matrix
(b) AIBICIDI matrix
(c) h-parameter matrix
(d) ABCD matrix
8. Which one of the following pairs is correctly matched?

(a)Symmetrical two port network
(b) reciprocal two port network
: Z11=Z22
(c ) Inverse hybrid parameter
: A,B,C,D
(d) Hybrid parameter
: (V1,I2) = ( I1, V2)
AD-BC=1
9. The h-parameters h11,h22 are related to Z & Y parameters as

(a)H11=Z11, h22=1/Z22
(c) h11=1/Y11 ; h22=1/Z22
(b) h11=Z11 , h22=Y22

(d) h11=1/Y11 , h22 = Y22
10. With usual notations, a two port resistive network satisfies the condition A=D=3/2B=4/3C, Z11 of
the network is
(a) 5/3
(b) 4/3
(c ) 2/3
(d) 1/3
11. When a number of two port networks are connected in parallel, individual
(a) Z matrices are added
(b)Y matrices are added
(c) chain matrices are added
(d) h matrices are added
12. The short circuit admittance matrix of a two-port network is as shown

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The two-port network is

a) Non reciprocal & passive
b) Non-reciprocal & active
c) Reciprocal & passive
d) reciprocal & active.
13. A 2- port network is shown in fig. The parameter h21 for this network can be given by
a)
b) +1/2
c) 3/2
d) + 3/2
14. For the circuit shown identify the correct statement ,where Za is Z-parameters of top circuit , Zb is Z
parameters of bottom circuit and Z is the Z parameters of complete circuit
a) for any value of R1 and R2 Z = Za + Zb
b) If R1 = R2 =0 then only Z = Za + Zb
c) If R1 and R2 is equal to 1 ohm then only Z = Za + Zb
d) None
14. In respect of the 2-port network shown in the fig. The admittance parameters are: Y11 = 8mho, Y12 =
Y21 =6 mho and Y22 = 6 mho. The values of Ya,Yb, Yc (in units of mho) will be respectively [

Page 218
a) 2,6 and 6
b) 2,6 and 0
c) 2,0 and 6
d) 2,6 and 8
16.The h parameters of the circuit shown in fig are
17. The condition that a 2- port network is reciprocal can be expressed in terms of its ABCD
Parameters as __________________
18. Z parameters are also called _______
19. h11 and h12 are obtained by
(a) short circuiting output terminals
(b) opening input terminals
(c) shorting input terminals
(d) opening output terminals
20. For a two port bilateral network, three transmission parameters are A = 6/5 , B = 17/5 , C = 1/5 , then D = ?
(a) 1
(b) 1/5
(c) 7/5
(d) 1/3
ANSWERS:
1 (d)
2 (d)
3 (c)
4 (b)
5 (c)
6 (c)
7 (d)
8 (d)
9 (c)
10 (b)
11 (b)
12 (a)
13 (a)
14 (b)
15 (c)
16 (d)
17 AD-
18. open
19 (a)
20 (c)
BC = 1
circuit
impedance
parameters

Page 219
UNIT III: FILTERS

1. A low pass filter is
(a) Passes all low frequencies
(b) attenuates all high frequencies
(c) passes all frequencies upto cut off frequency and attenuates all other frequencies (d) none
2. A highpass filter is
(a)Passes all high frequencies
(b) attenuates low frequencies
(c) attenuates all frequencies below a designated cutoff frequency and passes all frequencies above cut
off frequency
(d) none
3. In a certain low-pass filter, fc = 3.5 kHz. Its passband is

(a)0 Hz to 3.5 kHz (b) 0Hz (c) 3.5KHz
(d) 7KHz
4. An ideal filter should have

(a)Zero attenuation in pass band
(b) infinite attenuation in stop band
(c) Zero attenuation in stop band
(d) all of the above
5. Propogation constant of symmetrical T and -sections are same
True/False
6. Attenuation is sharp in stop band for k-type filter
True/False
7. Attenuation is sharp in stop band for __________ filter

(a) Constant-k
(b) m-derived
(c) both a&b
(d) none
8. In m-derived low pass filters, resonant frequency is

(a)Above cut-off frequency
(b) below cut=off frequency
(c) a & b
(d) none
9. A band pass filter may be obtained by using a high pass filter followed by a low pass filter
True/False
10. A band elimination filter is one which
(a) attenuates all frequencies below a designated cutoff frequency

(b) attenuates all frequencies above a designated cutoff frequency
(c)frequencies between f1,f2 are attenuated and all other frequencies are passed
(d) frequencies between f1,f2 are passed and all other frequencies are attenuated (d) none
11. In m-derived high pass filter, resonant frequency is ____ frequency
(a) Above cut-off
(b) below cut-off
(c) a & b
(d) none
12. In a m-derived low pass filter, value of m is _______

13. Filters are constructed by using _________
14. Filters consists of ____ elements.
(a) Only reactive
(b) resistive
(c) inductive
(d) capacitive
15. Pass band of a typical filter network with Z1, Z2 as series and shunt arm impedances is ________

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16. iterative impedance of a T network is _____ of open and short circuit impedances
(a) Addition
(b) division
(c) subtraction
(b) m<-1
(d) geometric mean
17. The value of m in order to have a sharp attenuation is

(a) m > 1
(c) 0<m <1
(d) m=1
ANSWERS:
1 (c)
2 (c)
10 (c)
11 (b)
3 (a)
4 (a)
5 true
6 false
7 (b)
8 (a)
9 false
12 1-
13 symmetrical T
14 (a)
15 -1
16 (d)
17 (c)
(fc/f)2
or networks
<Z1/4Z2 <
0
UNIT IV: ATTENUATORS
1. An attenuator is used
(a) To reduce frequency
(b) to reduce signal
(b) To increase signal amplitude
(d) to increase frequency
2. Attenuation by a network in decibels is

(a) 10 log20 (P1/P2)
(b)20log(P1/P2)
(c) 10log10(P1/P2)
(a) R0(N-1)/N+1 (B) R0(N+1)/(N-1)
(c) N+1/N -1
(D) N -1/N+1
(B) R0(N-1)/N+1 (C) R0(N2-1)/N+1 (d) N2-1/N+1
5. Characteristic impedance of symmetrical network

(a)open circuit impedance
(b) geometric mean of open and short circuit impedance
(c) short circuit impedance
(d) average of input and output impedances
6. 1 Bell unit of power = ____- decibels of power

(a) (b) 5
4. The shunt arm of type attenuator is

(b) R0(e+1)/ e+1
(d)100loge(P1/P2)
3. The value of series arm of T type attenuator

2
(c) 10 (d) 20
7. The parameters of attenuator are ___________

8. If attenuation of an attenuator is 60db, then current ratio is
(a) 500
(b)1000
(c) 750
(d) 250
9. Application of attenuator is _______

10. General units of attenuation is
(a) Degrees (b) nepers
(c) radians
(d) all the above
11. For attenuators, there will not be any phase shift in the signal
true/False
ANSWERS:
1 (b)
2 (c)
3 (a)
4 (a)
5 (b)
7 resistors
8 (b)
9. used as volume control in radio
10 (b)
11. true
6 (c)
broadcasting stations

Page 221
Unit V: DC MACHINES
1.A dc generator is a machine that converts
2.
(a) Electrical to mechanical energy
(b) mechanical to electrical energy
(c) low currents to high currents
(d) all the above
Mechanical energy source to drive a dc generator is
(a)rotor (b) stator (c) prime mover (d) dc generator

3.
Brushes that carry current to load are made of

(a)carbon (b) mica (c) lead (d) graphite
4. In a dc generator ,emf is induced in

(a) field coils
(b) armature coils
(c) brushes (d) commutator
5. Type of compound generator used for obtaining a constant terminal voltage

(a) over compound
(b) under compound (c) flat compound (d) none
6. If flux per pole is , then the value of flux in yoke section will be
(a) (b) 0.5 (c) 1.2 (d) 1.1
7. Emf generated by a dc generator depends upon
(a) flux only (b) speed (c) flux and speed (d) terminal voltage
8. Commutator segments are insulated from each other by
(a) mica (b) paper (c) wood (d) glass

9. Series generator has a ____ haracteristics
(a) rising (b) constant (c) drooping (d) linear
10.Nature of current flowing in armature of dc machine
(a) dc (b) alternating (c) pulsating (d) none
11.For a wave winding armature, number of parallel paths are
(a) number of poles (b) 2 (c) speed (d) Eg
12. For a lap wound armature, number of parallel paths= ________
13. The principle of operation of a dc generator is based on ________
14. Fore finger incase of Flemings right rule gives
(a) direction of voltage
(c) direction of magnetic field
(b) direction of armature

(d) motion of the conductor
15. Central finger in case of Flemings right rule indicates ______

16. Yoke of a dc machine is made up of
(a) lead (b) cast steel (c) copper (d) paper

Page 222
17. Commutator inn a dc generator is used for

(a) reducing friction
(b) converting dc to ac
(c) collecting current from armature
(d) convertinf ac to dc
18. In Flemings right rule , thumb indicates _________

19._______ is the cause for building up of voltage in a self-excited generator
20. If speed of prime mover increases, generated emf
(a) decreases (b) constant (c) increases (d) zero
21. In a compound generator, fluxes due to series and shunt fields______ each other.
(a) add (b) oppose (c) do not depend on each other (d) none.
ANSWERS
l (b)
2 (c)
3 (a)
4 (b)
5 (c)
6 (b)
7 (c)
8 (a)
9 (a)
10 (b)
11 (b)
12 number
13 Faradays laws of
14 (c)
15 direction of induced
of poles
electro-magnetic induction
17 (d)
18 motion of the conductor
16 (b)
21 (a)
emf
19 residual
20 (c)
magnetism
UNIT VI: DC MOTORS:

1.
Hysteresis loss varies with frequency (f) as

(a) f
2.
(c) f
(d) f
2.6
Hysteresis loss varies with maximum flux density (B) as

(a) B
3.
(b) f
1.6
(b) B1.6
(c) B2
(d) B2.6.
The shaft of electric motors is generally supported in

(a) magnetic bearings
(b) bush bearings
(c) ball or roller bearings (d) cast iron bearings.

4. DC series motor application is to drive
(a) where constant operating speed is needed
(b) where load is intermittent (c) where load changes frequently (d) cranes, hoists,trains
5. A dc series motor should not be started at light or no-loads because it will
(a)draw a dangerously large current (b) stall (c) run at dangerously high speed (d) none
6. In a dc series motor the torque developed is 20N-m at 10A of load current.If the load current is
doubled, the new torque will be

Page 223
(a) 40 N-m (b) 60 N-m (c) 80 N-m (d) 100 N-m

7. A 440V shunt motor has an armature resistance of 0.4 ohm and a shunt field esistance of 220 ohms.
The armature current when the current taken from the supply is 20A is
(a) 20A (b) 1000A (c) 1.6A
(d) 18A
8. The direction of force produced by each conductor can be determined by _________

9. The induced emf in a motor is proportional to
(a)current (b) parallel path (c) speed (d) all of the above
10. Condition of maximum efficiency in a dc machine is _______
11. Which of the following tests is performed on no-load?
(a) brake test (b) Swinburne test (c) load test (d) hopkinsons test
12. The speed of a dc motor is ____ to flux of the machine
(a) same (b) directly proportional (c) inversely proportional (d) constant
13. An electrical motor converts ___ to ______ energy
(a) electrical,heat (b) electrical ,mechanical (c) mechanical,electrical (d) electrical, electrical
14. The torque which is available for doing useful work is
(a) driving (b) shaft (c) field (d) none

15. Field flux method is used for speeds required_____ the rated speed.
(a) below (b) same as (c) above (d) all of the above
16.
Armature voltage method is used for speeds required_____ the rated speed.
(a) below (b) same as (c) above (d) all of the above
17. In cumulative compound motors, the flux in series and shunt windings ___ to each other.[
(a) opposite (b) aid (c) both a& b (d) none

18. In differential compound motors, the flux in series and shunt windings ___ to each other. [ ]
(a) opposite (b) aid (c) both a& b (d) none
19. The torque in a dc series motor varies as ____ of the load current
(a) proportional to half (b) same as (c) less (d) proportional to square
20. The torque in a dc shunt motor varies as ____ to the load current
(a) half (b) proportional (c) less (d) square
ANSWERS:
1(a)
2 (b)
3 (c)
4 (d)
5 (c)
6 (c)
7 (d)
9 (c)
10
Flemings
variable
left hand
losses =
rule
constant
losses
11 (b)
12 (c)
13 (b)
14 (b)
15 (c)
l6 (a)
17 (b)
18 (a)
19 (d)
20 (b)

Page 224
UNIT- VII: TRANSFORMERS
1. Open circuit test on a transformer is conducted to obtain

(a) the leakage impedances
(b) the ohmic loss
(c) hysteresis loss only
(d) core loss only
(b) wrought iron
(c) silicon steel
(e) eddy current loss only.
2. Transformer-core laminations are made of

(a) cast iron
(d) cast steel.
3. Which component of the no load current of the transformer is opposite in phase to the induced emf ?
(a) magnetizing component
(b) core loss component
(c) both (A) and (B) above
(d) none of the above.
4. In transformers, the cylindrical winding with rectangular conductors is generally used for [ ]
(a) low voltage winding
(b) high voltage winding
(c) tertiary voltage winding
(d) any of the above.
5.
The percentage of silicon in the core steel is
(a) 1 to 2 percent
(b) 2 to 3 percent
(c) 4 to 6 percent
(d) 8 to 10 percent.
6. In an oil filled transformer, oil is provided for

(a) Cooling
(b) Insulation (c) Lubricating
(d) Both cooling and insulation
(e) Preventing accumulation of dust.

7.
The 'hum' in a transformer is due to
(a) vibrations in cooling oil
(b) vibration in laminations
(c) sinusoidal voltage waveform
(d) all of the above.
8. When load on a transformer is decreased _______ loss is decreased.

9. A transformer has negative voltage regulation when its load power factor is
(a) zero (b) unity (c) laeding (d) lagging
10. Open circuit test on a transformer is performed with
(a) direct current (b) indirect current (c) both (d) rated transformer voltage.
11. Transformer core is laminated in order to
(a) decrease iron loss (b prevent eddy current loss (c) increase iron loss (d) none
12. A 2KVA transformer has iron losses of 150W and full load copper losses of 250W. The maximum
efficiency of the transformer would occur when the total loss is
(a) 500W (b) 400W (c) 300W (d) 275W

13. The maximum efficiency of a transformer will occur when ______
14. An ideal transformer is one which

Page 225
(a) has no leakage reactance and no losses (b) does not work (c) same number of primary and
secondary windings (d) none
15. The ratinf of a transformer is usually in
(a) volts (b) amperes (c) KW (d) KVA

16. Transformer operates on the principle of _____
17. The induced emf in a transformer ____ flux by _____.
(a) lags, 180 (b) leads,90 (c) lags,90 (d) leads 180 degrees
18.
A transformer transforms
(a) frequency (b) voltage (c) current (d) both b &c

19.
Short circuit test on a transformer is conducted at
(a) rated current (b) rated voltage (c) half load (d) all of the above
20. A 1-phase, 2200/200V transformer takes 1A at the HV side on no-load at a p.f of 0.385 lag. Then
iron losses are
(a) 77W (b) 467W (c) 847W (d) 133.7W

21. In case CRGO steel is used instead of hot rolled steel in electrical machines, its efficiency will be
__________
ANSWERS:
l (d)
2 (c)
3 (b)
4 (a)
5 (c)
6 (d)
7 (b)
8.
9 (c)
10 (d)
20 (a)
21
11 (b)
copper
12
(c)
13
14 (a)
15 (d)
16
copper
mutual
losses
induction
17 (c)
18 (d) 19 (a)
higher
= iron
losses
UNIT-VIII: Single phase motors
1. A capacitor start single phase induction motor will usually have a power factor of
(a) unity
(b) 0.8 leading
(c) 0.6 leading
(d) 0.6 lagging.
2. A capacitor start, capacitor run single phase induction motor is basically a

(a) ac series motor
(b) dc series motor
(c) 2 phase induction motor
(d) 3 phase induction motor.

Page 226
3. The torque developed by a split phase motor is proportional to

(a) Sine of angle between lm and ls
(b) Cosine of angle between lm and Is
(c) Main winding current, Im
(d) Auxiliary winding current,Is
4. Which of the following is the most economical method of starting a single phase motor [
(a) Resistance start method
(b) Inductance start method
(c) Capacitance start method
(d) Split-phase method.
5. Which single phase ac motor will you select for record players and tape recorders ? [
(a) Hysteresis motor
(b) Shaded pole motor
(c) Reluctance motor
(d) Two value capacitor motor.
6. A universal motor is one
(a) which can run on any value of supply voltage

(b) which has infinitely varying speed
(c) which can operate on ac as well as dc voltage
(d) which can work as single phase or three phase motor.
7. For ceiling fans generally the single phase motor used is
(a) split phase type
(b) capacitor start type
(c) capacitor start and run type
(d) permanent capacitor type.
8. A motor generally used in toys is

(a) Hysteresis motor
(b) Shaded pole motor
(c) Two value capacitor motor
(d) Reluctance motor.
9. Single phase motors generally get over heated due to

(a) Overloading
(b) Short windings
(c) Bearing troubles
(d) Any of the above.
10. In a single phase capacitor motor the direction of rotation will be in the opposite direction to the
original when
(a) electrolytic capacitor is replaced by paper capacitor

(b) two capacitors of equal value are used
(c) capacitor is replaced by a resistance
(d) capacitor is replaced by an inductor.
11. In a shaded pole motor, shading coils are used to
(a) reduce windage losses
(b) reduce friction losses
(c) produce rotating magnetic field
(d) to protect against sparking.
12. If a single phase motor fails to start, the probable cause may be
(a) open in auxiliary winding
(b) open in main winding
(c) blown fuses
(d) any of the above.

Page 227
13. In a capacitor start motor, the capacitor is connected in series with

(a) starting winding
(b) running winding
(c) compensating winding
(d) none of the above.
14.
Single phase induction motor can be made self starting by
(a) adding series combination of a capacitor and auxiliary winding in parallel with the main winding
(b) adding an auxiliary winding in parallel with the main winding
(c) adding an auxiliary winding in series with a capacitor and the main winding.
(d) none
15. In shaded pole motors the shading coil is normally made of __________
16. In capacitor motors, the current is in ________ with that in the main winding.
17. In a shaded pole induction motor, the rotor runs from the
(a) shaded portion to the unshaded portion of the pole while the flux in the former leads that the latter.
(b) shaded portion to the unshaded portion of the pole while the flux in the former lags that the latter.
(c) unshaded portion to the shaded portion of the pole while the flux in the former leads that the latter.
(d) unshaded portion to the shaded portion of the pole while the flux in the former lags that the latter.
18. A linear ac servo motor must have
(a) high rotor reactance
(b) high rotor resistance
(c ) large air gap
(d) both high motor resistance and reactance
19. The principle of operation of a single phase induction motor depends upon rotating magnetic
fields. True/False
20. Which motor will make least noise ?
(a) Capacitor motor
(b) Universal motor
(c) Shaded pole motor
(d) Hysteresis motor.
ANSWERS
1 (d)
2 (b)
3 (a)
4 (c)
5 (a)
6 (c)
7 (d)
8 (b)
9 (d)
10 (d)
11 (c)
12 (d)
13 (a)
14 (a)
15.
16.
17. (c)
18. (b)
19. True
20. (d)
Copper
Quadrature

Page 228
ESSAY TYPE
QUESTIONS
ESSAY Questions

UNIT:1 DC TRANSIENT ANALYSIS
1.A dc voltage of 100V is applied in the circuit shown in fig below and the switch is kept
open. The switch K is closed at t=0 .find the complete expression for the current?
2.A dc voltage of 20V is applied in R-L circuit where R=5 and L=0.1H .Find
(i) Time constant (ii) maximum value of energy stored
3.Derive an expression for the current response in R-L series circuit with a dc source?
4.Derive an expression for the current response in R-C series circuit with a dc source?
5.Define time constant? What is the importance of it?
6.Draw the network in Laplace domain and find I(S)
7..Derive an expression for the current response in R-L-C series circuit with a dc source?
8..A dc voltage of 20V is applied in R-L circuit where R=5 and C=1F .Find

Page 230
ESSAY Questions
(i) Time constant (ii) maximum value of energy stored
9.Switch is opened at t = 0 in the below circuit . Then find the current i.
10.Transform the below circuit (Figure. 2) in to S domain and determine the Laplace transform
impedance.
11.For the below circuit (Figure.1), find the current in 20 when the switch is opened at t = 0.
12. In a series RL circuit with R = 3 ohm and L = 1 H, a DC voltage of E = 50 V is applied at t = 0.

Find the transient response of current and plot the response.
13. (a) In the circuit shown in Figure 4, the switch is closed on the position 1 at t = 0 there by
applying a D.C. voltage of 100V to series R-L circuit. At t = 500_sec, the switch is moved to
position 2. Obtain the expression for current i(t) in the both intervals sketch i(t).

Page 231
ESSAY Questions
(b) The switch S is closed at t = 0 (Figure 5). Find the initial conditions at t = 0+ for i1, i2, Vc,
di1/dt, di2/dt. [8+7
Figure 4:
Figure 5:
14. Derive the expression for i(t) of RC series circuit with zero initial conditions and
show the variation of i with time t .
UNIT II: TWO PORT NETWORKS
1.Find the Z parameters of the network shown in figure below?

Page 232
ESSAY Questions
2.Find the Y parameters of the network shown in figure below?
3. Obtain Z parameters of the below circuit (Figure. 3) and from there Z parameters derive h parameters.
4. For the two port network shown in the figure 6, the currents I1 and I2 entering at
port 1 and 2 respectively are given by the equations.
I1 = 0.5 V1 - 0.2 V2
I2 = -0.2V1 + V
Where V1 and V2 are the port voltages at port 1 and 2 respectively. Find the Y,
Z, ABCD parameters for the network. Also find its equivalent _ network.
5.Find the transmission parameters of the network shown in figure?
6.The Y parameters of a two port network are Y11=0.6 mho,Y22=1.2 mho and
Y12=-0.3 mho
Determine the (i) ABCD parameters and
(ii) Equivalent network

Page 233
ESSAY Questions
7.Find the h parameters of the network shown in figure below?
8.In a T network Z1=200 Z2=5-300and Z3=3900Find Z parameters and hence find

Y parameters ?
9. Derive Y parameters in terms of ABCD parameters?
10.Give the conditions for (i) symmetry (ii) reciprocity for
Z parameters , Y parameters, h parameters and ABCD parameters
11.Two networks shown in figures below are connected in series. Obtain the Z parameters of the
combination. Also verify by direct calculation?
12.Two identical sections of the network shown in figure below are connected in parallel.
Obtain the Y arameters of the combination?

Page 234
ESSAY Questions
13.Find Z, Y Parameters for the network.
14. (a) Define- Reciprocal and Symmetrical Networks.
(b) What is the condition for the given network to be reciprocal as well as Symmetrical in terms of
ABCD parameters.
(c) Find the ABCD parameters for network shown in Figure 1.
Figure 1
15.Obtain the input and output impedances of an amplifier having h11 = 2 ohm; h12 = 1; h21 = 5;
h22 = 2 mho, if it is driven by a source having an internal resistance of 4 ohm and is terminated
through a load which draws maximum power from the amplifier.
16.Determine the Z and Y- parameters of the network shown in Figure
Figure :

Page 235
ESSAY Questions
UNIT III: FILTERS

1.Define filter? Give the classification of filters?
2.Derive the expression for the characteristic impedance of a symmetrical T filter?
3.Derive the expression for the characteristic impedance of a symmetrical filter?
4.Design a high pass filter to have a design impedance of 500 and cut ff frequency of 1KHz?
5.Design a band elimination filter having a design impedance of 500 and cut off frequencies f1=1KHz
and f2=5KHz
6.Design a low pass T section filter having a cutoff frequency of 1.5KHz to operate with a terminal
load resistance of 600.
7.Design a low pass section filter having a cutoff frequency of 2 KHz to operate with a terminal
load resistance of 400.
8. Design a high pass section filter having a cutoff frequency of1 KHz to operate with a terminal load
resistance of 800.
9.Design a band elimination filter having design impedance of 600 and cutoff frequencies f1=2 KHz
and f2=6 KHz
10.Design a m derived high pass filter with a cut off frequency of 10KHz; design impedance of 5 and
m = 0.4
11.Derive the design parameters of a band pass filter.

12.Derive the design parameters of a low pass filter.
13.Derive the design parameters of a m-derived pass filter.
14.Explain m-derived low-pass T-section and -section in detail and the necessary design procedure.
15. What is a half section? What is its main characteristics? Why it is used? Derive expression for
impedances as seen from the two-ports of an m-derived half section.
UNIT IV: ATTENUATORS

1. Derive the design parameters of a symmetrical T attenuator.
2. Derive the design parameters of a symmetrical delta attenuator .
3. Derive the design parameters of a bridged T attenuator.
4. Obtain the parameters of a symmetrical T attenuator with attenuation =25db and design impedance
500 ohms.
5. Derive the design parameters of a lattice attenuator .

Page 236
ESSAY Questions
6. Obtain the parameters of a symmetrical attenuator with attenuation =20db to have a characteristic
impedance of 100 ohms.
7. Obtain the parameters of a symmetrical lattice attenuator with attenuation 25db and characteristic
impedance of 800 ohms.
8. Obtain the parameters of a bridged attenuator with attenuation 20db and terminated to a load of 400
ohms.
9.
An attenuator is composed of symmetrical T-section having series arm each of 420 ohms and shunt arm of
740 ohms. Derive expression for and calculate the characteristic impedance of this network and attenuation
per section. Draw the circuit diagram for symmetrical T-type attenuator.
10. (a) Explain symmetrical _T-type attenuator with necessary equations in detail.
(b) Design a symmetrical _ -type attenuator to give 20 db attenuation and to have a
characteristic impedance of 200 ohms. [10+5]
11. What is an Attenuator? Explain different types of symmetrical attenuators in detail?
12. (a) Design a T-type attenuator to have an attenuation of 40db and to work between source
impedance of 400 ohms and load impedance of 900 ohms.
(b) Design a -type attenuator to have an attenuation of 25db and to work between source
impedance of 600 ohms and load impedance of 1000 ohms.
Unit V: DC MACHINES
1. Explain the constructional features of a dc machine
2. Derive the emf equation of a dc machine
3. Explain the characteristics of a dc shunt generator
4. Explain the characteristics of a dc series generator
5. A shunt generator supplying a 200KW at 230V has a field circuit resistance of 150 ohms and an
armature resistance of 0.25 ohms. Calculate a) full load current b) armature current c) generated
emf d) field current. Assume brush voltage per brush as 1V
6. The emf generated by a 4 pole wave connected dc generator is 500V on load at a speed of
1000rpm. Calculate the flux per pole, if the armature has 144 slots with two coil sides per slot,
each coil side consisting of 4 turns.
7. Explain the types of dc generators.
8. Find the number of conductors required for a 4 pole wave wound generator to generate an induced
emf of 220V, the flux per pole is 0.01 Wb and the speed of the machine is 1200 rpm

Page 237
ESSAY Questions
9. A 220KW, 240V separately excited generator is delivering rated load at rated voltage, armature
resistance is 0.05 ohms, field resistrance is 100 ohms. The field is excited by 150V dc supply.
Find a) field current b) armature current
c) load current and d) generated emf. Assume 1V
drop per brush

10. A long shunt compound generator supplies a load current of 75A at 440V, the resistance of
armature, series field and shunt field are 0.02,0.01 and 150 ohms respectively. Calculate the
generated emf.
11. The wave connected armature of a four pole dc generator is required to generate an emf of
520V when driven at 600 rev/min. Calculate the flux per pole required if the armature has 144
slots with two coil sides per slot, each coil consisting of 3 turns.
12. (a) Name the main parts of a DC machine and state the materials of which each part is made of
and explain clearly the reasons to select these materials.

(b)A Certain wave wound DC generator running at a speed of 300rpm is to generate an induced
emf of about 535V, the ux per pole being 0.055 Wb.Determine the number of poles, if the
number of conductors is 650.
13. (a) What is a DC generator? Explain its constructional details.
(b) Draw the circuit model of a DC shunt generator and write the relationship of currents and
voltages.
14. Compare DC generator and DC motor from principle of operation point of view and mention the
application of each machine?
UNIT VI: DC MOTORS
1. Derive the torque equation of a dc motor.

2. Explain the characteristics of dc motors.
3. Explain the principle of operation of a dc motor.
4. Explain the power flow diagram of a) dc motor b) dc generator
5. A dc shunt motor rotating at 1500 rpm is supplied from a 250V the line current is 62 A,
resistance of field and armature windings are 125 and 0.2 ohms respectively. Determine a)
armature current b) back emf c) power developed by the armature if the rotational losses are
200 W
6. Explain the various speed control methods of a dc motor

7. Derive the condition for maximum efficiency of a dc machine

Page 238
ESSAY Questions
8. In Swinburnes test, a dc shunt motor takes 4A at 220V, the armature and field resistances are
0.4 and 220 ohms respectively. Determine a) the constant losses b) the full load efficiency
when running as motor, taking 40A c) running as generator delivering 40A at 220V.
9. A 220V dc shunt motor has an armature resistance and shunt field resistances of 0.5, 220 ohms
respectively. It takes a no load current of 40a at 1000 rpm. If the full load current is 28A, there is
a 5% reduction of flux under full load due to armature reaction. Find a) speed at full load b)
speed regulation. Assume a total brush drop of 2V
10. Classify the different types of losses of a dc machine.

11.A 220V series motor runs at 800 rpm, when taking a current of 15 A. Themotor has Ra = 0.3 and Rf = 0.2
. Find the resistance to be connected inseries with armature if it has to take the same current at the
same voltage at600 rpm. Assume flux is proportional to current.
12.(a) Explain why Swinburnes test cannot be used to determine the effciency of DC series motor?
(b) A 4 pole series motor has 944 wave-connected armature conductors at a certain load. The
flux per pole is 34.6 mWb and the total mechanical torque developed is 209 N-m. Calculate the
line current taken by the motor and the speed at which it will run. The applied voltage is 500 V
and total motor resistance is 3.
13.
(a) All general requirements of the electric traction are fulfilled by DC series motors compared to
other DC motors". Justify with related equations and characteristics.

(b) A 250V, 4-pole wave wound DC series motor has 888 conductors on its armature. It has
armature and field resistance of 0.88ohms .The motor takes a current of 80A. Determine i) Speed
ii) Gross torque developed if it has a flux per pole of 28 mwb.
14. (a) A series wound motor runs normally. The field coils are all connected in series. Estimate the
speed and current taken by the motor, if the coils are reconnected in two parallel groups of two in series.
The load torque increases as the square of the speed. Assume that flux is directly proportional to the
current and ignore the losses.
(b) A 220V motor has an armature circuit resistance of 0.6. If the full load armature current is 20A and
the no load armature current is 5A, find the change in back e.m.f from no-load to full-load.
15. (a) With a neat sketch, explain how the direction of rotation of DC motor can be reversed?
(b) Derive the standard torque equation of DC motor from first principles.
UNIT- VII: TRANSFORMERS
1. Explain the constructional details of a single phase transformer

2. Explain the principle of operation of a single phase transformer

Page 239
ESSAY Questions
3. The core cross section of a single phase transformer is 40cm2 that has N1= 80 and N2 = 40 and
V1 = 220V at 50Hz. Calculate the current in the primary winding of the transformer. Find the
flux density and secondary induced emf
4. A 75KVA,2200/220V, single phase 50Hz transformer full load copper and iron losses are
1800W and 1000W. Find efficiency at a) full load unity power factor b) full load 0.8 power
factor lagging c) at three fourth 0.8 power factor lagging.
5. Derive the equivalent circuit of a single phase transformer
6. A 200KVA single phase 2200/1100 V, 50Hz transformer recorded the following readings
during SC and OC tests:
OC test data on HV side :
2200V
1700W
2.8A
SC test data on LV side :
20V
1000W
200A
Obtain the equivalent circuit as referred to primary side

7. Explain the operation of an ideal transformer under no load conditions along with necessary
phasor diagrams.
8. Explain the operation of an practical transformer under load conditions along with necessary
phasor diagrams for lagging and leading power factors.
9. Derive the condition for maximum efficiency of a single phase transformer.
10. Derive the expression of voltage regulation of a single phase transformer.
11. The maximum flux density in the core of 240/2400V, 50Hz, single phase transformer is
1.0Wb/sq.m. If the emf per turn is 8 Volts, determine:
i. the primary and secondary turns and
ii. area of the core.
12. A 100 kVA transformer has iron losses of 1.2 kW and full load copper lossesof 1.5kW. Find
a) the kVA for maximum efficiency
b)
maximum efficiency.
13. The primary winding of a 50Hz single phase transformer has 500 turns and is supplied from
3300V supply. The secondary winding has 50 turns. Find peak value of the flux in the core and
the secondary voltage.
14. (a) From the fundamentals, derive the expression for the EMF equation of a single phase
transformer.
(b) A 40 KVA, single phase transformer has 400 turns on the primary and 100turns on the
secondary. The primary is connected to 2000V, 50 Hz supply. Determine:i. The
secondary voltage and ii. The maximum value of flux. [7+8]

Page 240
15.
ESSAY Questions
(a) What is regulation? How can it be obtained from equivalent circuit parameters?
(b) The readings obtained from tests on 10 KVA, 450/120V, 50Hz transformer are
O.C. Test (LV Side) : 120V,4.2A, 80W
S.C. Test (HV Side): 9.65V,22.2A,120W Compute:
i. The equivalent circuit constants.
ii. The efficiency at half load and 80% lagging power factor.
16.
(a) What are the different losses in a transformer? Derive the condition for maximum effciency of a
single phase transformer.

(b) The primary and secondary winding resistances of a 30 KVA, 6600/250 V.1-phase transformer are 8
ohm and 0.015 ohm respectively. The equivalent leakage reactance as referred to the primary winding is
30 Ohm. Find the full load regulation for load power factors of: i. Unity
ii. 0.8 lagging and
iii. 0.8 leading.

17.
(a) What is transformer regulation? How it can be obtained from equivalent circuit parameters?
(b) The primary and secondary resistance of a 1100/220 V transformer are 0.3 ohm and 0.02 ohm
respectively. If iron loss amounts to 260 W, determine the secondary current at which the maximum
effciency occurs and the maximum effciency at 0.8 power factor.
UNIT-VIII: SINGLE PHASE INDUCTION MOTORS

1. Explain the operation of a single phase induction motor according to double field revolving
theory
2. Explain the torque-slip characteristics of a single phase induction motor along with the relevant
equivalent circuit
3. Explain the working of a capacitor start motor
4. Describe the working of shaded pole motors
5. Explain the characteristics of ac servo motor along with its transfer function
6. Describe the types of tachometers with their working
7. Explain the principle of operation of synchros
8. Explain the principle of operation of stepper motors including its characteristics
9. Explain the following:
a) Hybrid motors
b) Permanent magnet stepper motor
10. Explain the operation of a single phase induction motor according to cross field revolving
theory

Page 241
ESSAY Questions
11. Discuss why single phase induction motor is not self starting? Explain different techniques for
starting of 1-phase induction motor.
12. Explain the concept of split-phase induction motor along with its characteristics.

Page 242
ASSIGNMENT
QUESTIONS
UNIT I: Transient Analysis
1. For the below circuit (Figure. 1), find the current equation i(t), when the switch is opened at t
= 0.
2. Transform the below circuit (Figure.2) in to S domain and determine the laplace impedance.
3. Determine the current i for t 0 if initial current i(0) = 1 for the below circuit
4. For the circuit shown below Figure. 1, find the current equation when switch S is opened at t
= 0.

Page 244
UNIT II: Two port networks

1. Find Y parameters and hence find h parameters for the network
a.
2. Determine the transmission parameter and hence determine the short circuit admittance
parameters for the below circuit
a.
3. Express Z parameters in terms of Y parameters?
4. Express ABCD parameters in terms of h parameters?
5.
Two identical sections of the network shown in figure below are connected in cascaded

Page 245
Obtain the ABCD parameters of the combination?
UNIT III: Filters

1. Design a band elimination filter having a design impedance of 500 and cut off frequencies
f = 1.25 KHz and f = 6 KHZ.
1
2. Derive the design parameters of a high pass filter.

3. Classify pass band and stop band when the impedances are of opposite type
4. Derive the resonant frequency of a m derived high pass filter.
UNIT IV:Attenuators
1. Explain the lattice attenuator and also design a lattice attenuator to have a characteristic
impedance of 800 and attenuation of 20 dB.
2. Explain type attenuator and also design it to give 20db attenuation and to have
characteristic impedance of 100.
3. Explain Bridged T attenuator and also design it with an attenuation of 20 dB and
terminated in a load of 500.
4. Explain T type attenuator and also design a T type attenuator to give an attenuation
of 60dB and to work in a line of 500 impedance.
Unit V: DC Machines
1. What are the different types of dc generators? Show the connection diagrams and load
characteristics of each type.

2. State the principle of operation of a dc generator and derive the expression for the emf
generated.
3. A 6 pole dc shunt generator with a wave wound armature has 960 conductors. It runs at

Page 246
a speed of 500 rpm. A load of 20 is connected to the generator at a terminal voltage of

240V. The armature and field resistances are 0.3 and 240 respectively. Find the armature
current, the induced emf and flux per pole.
4. A Series generator having combined armature and field resistance of 0.4 is

5. running at 1000 rpm and delivering 5.5kW at a terminal voltage of 110V. If
6. the speed is raised to 1500 rpm and load is adjusted to 10kW, find the new current and
terminal voltage.
7. A 4 pole generator has 48 slots and 8 conductors per slot. The useful flux per pole is 30mWb
and speed is 800 rpm. Find the generated emf, if the machine is wave connected.
UNIT VI: DC Motors

1.
A 4 pole, 500V dc shunt motor has 700 wave connected armature conductors. The full load
armature current is 60 A and the flux per pole is 30mWb. Calculate the full load speed if the
motor armature resistance is 0.2 and brush drop is 1V per brush.
2.
Derive the torque equation of a dc motor.
3. Explain why a dc series motor should never run unloaded.

4. A 200V, 14.92kW, dc shunt motor when tested by Swinburnes method gave the following test
results.
Running light: Armature current of 6.5 A and field current = 2.2A
With armature locked: I =70A when potential difference of 3V was applied to the brusher.
a
Estimate efficiency of motor when working under full load.
UNIT- VII: Transformers

1. A 10 KVA 2500/250 Volts single phase transformer gave the following test results
Open circuit test : 250 V, 0.8 A, 50 W
Short circuit test: 60V 3A 45 W
2. Calculate the efficiency and voltage regulation at full load 0.8 power factor lag
3. A 50Hz, 1, 100 KVA transformer has full load copper loss of 1200W and its iron loss is
960W. Calculate:
i. The efficiency at full load, unity power factor.
ii.
The efficiency at half load, 0.8 power factor.

Page 247

iii.
The efficiency at 7.5% of full load, 0.7 power factor.
4. Draw the phasor diagram of a single phase transformer under load conditions for lagging,
leading and unity power factors.
5. Open circuit and short circuit tests on a 5 KVA, 220/400V, 50 Hz, single phase transformer
gave the following results:
OC Test: 220V, 2A, 100W (lv side)
SC Test: 40V, 11.4A, 200W ( hv side)
6. Determine the efficiency and approximate regulation at full load, 0.9 power factor lagging.
7. Derive the expression for the induced emf of a transformer.
8. A 125 KVA transformer having primary voltage of 2000V at 50 Hz has 182 primary and 40
secondary turns. Neglecting losses, calculate:
i) The full load primary and secondary currents.
ii) The no-load secondary induced emf.
iii)
Maximum flux in the core.
9. A 200/400V, 50Hz, 1- transformer has the following test data

10. O.C. Test: 200V 0.7A 70 W -on L.V.Side
11. S.C Test: 15V 10A 85 W -on H.V.Side
12. Calculate the secondary voltage when delivering 5kW at 0.8lag. V1=200V.
13. 8.The maximum flux density in the core of 240/2400V, 50Hz, 1- transformer
14. is 1.0Wb/sq.m. If the EMF per turn is 16 volts, determine:
i. the primary & secondary turns and
ii.
area of the core.
15. A 20 kVA transformer has its maximum efficiency of 0.98 at 15 kVA at upf. The iron
loss is 350W. Calculate the efficiency at full load, for 0.8 p.f lag and upf.
16. The primary winding of a 50Hz, 1- transformer has 500 turns and is supplied from
3300V supply. The secondary winding has 50 turns. Find the peak value of the flux in
the core and the secondary voltage.
17. A 25 kVA, 2500/250V, 1- transformer gave the following test figures:
i) O.C Test (LV Side): 250V 1.4A 105W
ii) S.C Test (HV Side): 105V 8A 320W

Page 248
iii) Compute the equivalent circuit parameters referred to LV side and HV side. Also
obtain percentage regulation at full load with 0.8 p.f lagging.
UNIT-VIII: Single phase induction motors

1. Draw the circuit diagram of capacitor start, capacitor run single phase induction
motor and explain its working. Where this type of motor is commonly used?
2. Write a short note on the following:
a) Stepper motor.
b) AC tachometers.
3. Explain the principle of operation of a single phase induction motor based on double
field revolving theory
****THE END***

Page 249
Pulse & digital circuit

laboratory
Ms.b. vijaya laxmi
Assoc. Professor
&
mrs.p.padmaja
asst.professor
Lab Schedule
Department of

Sponsored by
PULSE &DIGITAL CIRCUITS LAB
S.NO Name Of The Experiment
LABORATORY SHEDULE
Linear Wave shaping
Regular Experiment*/
Additional Experiment+
Regular Experiment
Non Linear Wave shaping - Clippers
Regular Experiment
Non Linear Wave shaping - Clampers
Regular Experiment
Transistor as a switch
Regular Experiment
Bistable Multivibrator
Regular Experiment
Monostable Multivibrator
Regular Experiment
Astable Multivibrator
Regular Experiment
Schmitt Trigger
Regular Experiment
UJT Relaxation Oscillator
Regular Experiment
10
Bootstrap sweep circuit
Regular Experiment
11
Study of Logic Gates and some Applications
Regular Experiment
12
Study of Flip-Flops and some application
Regular Experiment
Remarks

Page 251
ELECTRONIC CIRCUIT
ANALYSIS labaratory
Mrs.P.A.Harshavardini
AssT. Professor
&
mr.n.hathiram
asst.professor
Lab Schedule
Department of

Sponsored by
ELECTRONIC CIRCUIT ANALYSIS LAB

S.NO
Name Of The Experiment
LABORATORY SHEDULE
Regular Experiment*/
Remarks
Additional Experiment+
1.
Simulation of Common Emitter
Regular Experiment
amplifier
2.
Common Emitter amplifier
Regular Experiment
3.
Simulation of Common Source
Regular Experiment
amplifier
4.
Common Source amplifier
Regular Experiment
5.
Simulation of Two Stage RC Coupled
Regular Experiment
Amplifier
6.
Two Stage RC Coupled Amplifier
Regular Experiment
7.
Simulation of Single Tuned Voltage
Regular Experiment
Amplifier
8.
RC Phase Shift Oscillator using
Regular Experiment
Transistors
9.
Simulation of Wien Bridge Oscillator
Regular Experiment
using Transistors
10. Hartley & Colpitts Oscillators
Regular Experiment
11. Simulation of Cascode Amplifier
Regular Experiment
12. MOSFET amplifier
Regular Experiment
13. Simulation of High Frequency

Additional Experiment
Page 253
ELECTRONIC CIRCUIT ANALYSIS LAB
LABORATORY SHEDULE
Common Base (Bjt)/Common Gate

(JFET) Amplifier
14. High Frequency Common Base
Additional Experiment
(Bjt)/Common Gate (Jfet) Amplifier

Page 254
ELECTRICAL ENGINEERING
laboratory
Mrs. G.sravanthi
AssT. Professor
Lab Schedule
Department of

Sponsored by
ELECTRICAL ENGINEERING LAB
LABAROTARY SHEDULE
S.NO Name Of The Experiment
1
2
3
4
5
6
7
8
9
10
11
12
VERIFICATION OF KVL AND

KCL
SERIES AND PARALLEL
RESONANCE
TIME RESPONSE OF RC SERIES
CIRCUIT
TWO PORT NETWORK
PARAMETERS-Z,Y
TWO PORT NETWORK
PARAMETERS-ABCD AND H
VERIFICATION OF
SUPERPOSITION AND
RECIPROCITY THEOREMS
VERIFICATION OF MAXIMUM
POWER TRANSFER THEOREMS
THEVININS AND NORTONS
THEOREM
MAGNETISATION
CHARACTRISTICS OF DC
SHUNT GENERATOR
SWINBURNES TEST ON DC
SHUNT MOTOR
BRAKE TEST ON DC SHUNT
MOTOR
OC & SC TEST ON SINGLE
PHASE TRANSFORMER
*Regular experiment ----according to the syllabus/
Regular
Experiment*/
Additional
Experiment+
Remarks
REGULAR
REGULAR
REGULAR
REGULAR
REGULAR
REGULAR
REGULAR
REGULAR
REGULAR
REGULAR
REGULAR
REGULAR
+ Additional Experiments Experiments other than syllabus

Page 256
***The End***

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CONTENT

Pulse & Digital Circuits

Switching Theory & Logic Design

Electronic Circuit Analysis

Electromagnetic Theory & Transmission Lines

Principles Of Electrical Engineering

Pulse & Digital Circuits Laboratory

Electronic Circuit Analysis Laboratory

Electrical Engineering Laboratory

DEPARTMENT ACADEMIC CALENDAR

Submission of abstracts of main project by IV years

Spell for Unit VII Instructions for II &IV years

Spell for UNIT VII Instructions for III year

Assignment-II / Unit test on Vth & VIth Units

25. Submission of results & week students list to Dept

27. Spell for Unit- VIII Instructions for III year

28. Thanks giving party

32. University II-Mid-Exam- III Year

33. Practical Examinations for II Year

34. Final Project demo and draft copy submission

35. Practical Examinations for III Year

36. EXTERNAL PROJECT VIVA (IV years)

37. End Semester Examination

38. Commencement of next semester

ELECTRONICS AND COMMUNICATION ENGINEERING

VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE

Pulse and Digital Circuits

Vignan Institute of Technology & Science

II Year B.Tech. 2nd Semester

Pulse and Digital Circuits

miller time base generator,

Transistor Bootstrap time base generator, Current time base generators.

UNIT-VIII: REALIZATION OF LOGIC GATES USING DIODES & TRANSISTORS:

II Year B.Tech. 2nd Semester

Pulse and Digital Circuits

IEEE Transaction on Electronic Devices (ISSN: 0018-9383)

Vignan Institute of Technology & Science

II Year B.Tech. 2nd Semester

Pulse and Digital Circuits

STUDENTS SEMINAR TOPICS

Vignan Institute of Technology & Science

II Year B.Tech. 2nd Semester

Pulse and Digital Circuits

UNIT I:LINEAR WAVESHAPING

LINEAR WAVESHAPING: Introduction

Black board and Chalk

Different types of inputs

Black board, Chalk and LCD Projector

Black board and Chalk

Step and Pulse input

Black board and Chalk

Black board and Chalk

Black board and Chalk

Black board and Chalk

Applications of attenuators in CRO probe

Black board and Chalk

Response of RL circuits for step input

Black board, Chalk and LCD Projector

Response of RLC circuit for step input

Black board and Chalk

Black board and Chalk

Black board and Chalk