EE1003 Introductions to signals and communications

Lab 3

Lab sheet for Lab 3

Objective:

To understand the function of an all-digital phase-lock loop (ADPLL) and

implementing an application circuit.

Warm-up question:
1. Why phase lock loops are needed in communication systems?

Requirements:
1.
2.
3.
4.
5.

Include your answer for above warm-up question in your lab report.
Two students work as a group and each of you will submit a report.
Your work on the circuits and your report will be assessed.
Each group should prepare a copy of datasheets for 74HC297 and 74HC04.
Make sure the power source outputs right voltage (+5V) and the signal amplitudes from
the signal generator are correct before you connect them to the breadboard.

Equipment to be used:
1. Oscilloscope and two signal generators for each group.
2. A DC power source.
3. An experiment board, Breadboards and 74HC297, 74HC04.

In-lab activities:
1. Build the ADPLL circuit and debug.
a. Build the ADPLL circuit using the 74HC297 on the given breadboard as Figure 1.
VCC is 5V.
b. Output a TTL signal (low at 0 and high at 5V square waveform, duty cycle 50%)
of 32K Hz from a signal generator as the input signal to your ADPLL circuits.
(This input signal emulates a data sequence of alternative 0 and 1 with data rate
64Kbps.)
c. Output a TTL signal of 32.768M Hz from another signal generator as the high
speed clock.
d. Use of the provided experiment board as the external divide-by-N frequency
divider. Set the DIP switch 1 on and the DIP switch 2 off. (If they are set
correctly, the red LED will be lighted up and the green led will be off.) Refer to
Figure 1 for the connections of the ADPLL circuits and refer to Figure 2 for the
frequency divider circuits.
e. Check that the output signal, which is the signal from P5 of the experiment
board, is 32K Hz. Check the signal from P4 is 64K Hz.

EE1003 Introductions to signals and communications

Lab 3

f.

Fine tune the high speed clock frequency such that your output is locked with
the input signal. Observe both the input signal and the output signal and using
the input signal to trigger. If they are locked, you should see two stable
waveforms.
2. Observe the phase differences between the input and output.
a. Slowly increase the high speed clock frequency and record the phase difference
1 between the input signal and output signal right before your ADPLL is
unlocked.
b. Slowly decrease the high speed clock frequency and record the phase difference
2 between the input signal and output signal right before you ADPLL is
unlocked.
c. Indicate the value of 1 2 . This value given the range of phase difference you
can achieve with the ADPLL.
3. Measure the hold range of your circuit.
a. Fine tune the high speed clock frequency such that the input signal and output
signal are locked. (You may skip this step if your ADPLL is locked after
previous step.)
b. Slowly increase the input signal frequency with small step size. Record the
maximal input signal frequency 1 when the ADPLL circuit stays in locking
state.
c. Slowly decrease the input signal frequency with small step size. Record the
minimal frequency 2 when the ADPLL circuit stays in locking state.
d. The frequency range [ 2 , 1] is the frequency range your ADPLL can tolerate
with the given setting. That is your ADPLL still can manage to lock when the
input signal frequency can vary in this range. If the input signal frequency is
beyond this range, your ADPLL cannot trace it anymore.

Questions:
1. The experiment board is actually a frequency divider with the given DIP switch setting,
which divides the frequency of the input TTL signal at P0 by 256 and outputs from P4.
Its schematic is shown in Figure 2. Can you obtain a synchronized square waveform of
2.048 MHz from any pin in Figure 2? Indicate the corresponding pin if yes.
2. Let N = (frequency of signal at P0)/(frequency of signal at P5). The high speed clock is
32.768 MHz. What is the N value if the input signal in Fig. 1 is a 64 KHz TTL signal?

EE1003 Introductions to signals and communications

Lab 3

Figure 1. All digital phase lock loop schematics.

Figure 2. Divide-by-N schematics (Signal inputs from P0 will be divide by N and outputs from P5. In this
example N = 512.)