Design and Implementation of a High Switching

Frequency Digital Controlled SMPS

Shu WANG
Cellular Communication Division
STMicroelectronics
12, rue Jules Horowitz - B.P 217
F-38019 GRENOBLE Cedex FRANCE
Email: shu.wang@st.com

Yves LEMBEYE, Jean-Paul FERRIEUX

Grenoble Electrical Engineering Laboratory
G2Elab ENSIEG
BP 46
38402 Saint MARTIN d'HERES cedex - FRANCE

Abstract - This paper describes design and implementation

of a high switching frequency digitally controlled boost
converter. A mixed control approach is applied to reach a
high performance. An FPGA based implementation with
1MHz switching frequency is build to verify the control
methodology, and two controllers with 1MHZ and 10MHz
switching frequency is applied on silicon. The raising
edge of Vout to drive four LEDs is less than 100us.

I.

INTRODUCTION

The digital controller for voltage of power supply, [1]-[3],

such as DSP, FPGA, and other ASIC were reduced quite fast
in recent years. With the development of microelectronics,
the requirement of regulation range is going smaller while the
current of load is increasing. This makes the design of
controller to be difficult, high load current and fast current
change made the voltage drop quick and sudden, and even
hard to meet the reference. Therefore, a digital controller
with high switching frequency is implemented to meet with
this stringent requirement.
In the last decade, lots of attentions were received by
digital controlled DC/DC converter. A great deal of digital
controlled SMPS were developed based on micro-processor,
digital signal processor [4]-[11], [19], or programmable logic
device [12] [16]. In these kinds of applications, the methods
of control were often very complex, the switching

for the current changing situation.

Recently, with the improvement in ASIC and FPGA
speed , some high switching frequency digital control method
were developed, most of them can reach more than 100 kHz,
and can be implemented both on ASIC or on FPGA. Due to
the smaller part count, better reliability, and not sensitive to
the environmental influence [1], [3], compare with analog
controller, and with the decrease of the cost of digital
integrated circuit, the digital controlled DC/DC converter has
a widespread adoption in applications for handle devices,
Mobil-phones, and computers.
In this paper, a new mixed control approach is provided to
realize a step-up voltage supply. This control method
incorporates several Z-transfer controllers and a dither
controller in order to get the speed, stability and precision. A
look-up table is used to store the pre-calculated Z transfer
function results to simplify the design and increase the
switching frequency. An Altera FPGA based prototype is
implemented to verify the simulation results. A full
integrated implementation is applied by STMicroelectronics.
In detail, this paper is organized as follows.
II.

DIGITAL CONTROLLED STEP-UP SWITCHING-MODE

POWER SUPPLY APPLICATION

The point-to-load switching-mode power supply is usually

used to provide a low, tightly regulated DC voltage output to
a microelectronic component from an intermediate DC input
voltage (battery) and is wildly used in the portable devices.
Fig.1 illustrates a diagram of a typical digital controlled
point-to-load (POL) supply based on boost (step-up)
switching converter. The logic part is used to realize some
simple logic such as limit the current in the coil and convert
the PWM signal to switcher drive signal. The buffer here is
use to amplify the digital output signal from logic part to a
strong enough level to drive the MOSFET switcher.

Fig. 1: Digital controlled point-to-load DC-DC converter

frequencies were really low (10 kHz) [2] and also can not fit

1-4244-0655-2/07/$20.002007 IEEE

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A typical digital control stage was formed by 3 blocks: A/D

converter, digital controller, and Digital Pulse Width
Modulation (DPWM). The output voltage Vs is sampled and

A/D converted into digital signal E. A discrete controller

computes the binary code duty-cycle command D with
certain kind of algorithm and a digital pulse-width modulator
(DPWM) converts this digital command into a pulse-width
signal at a desired switching frequency to drive the switcher.
In order to reach the fast dynamic response, the sample rate
for the output voltage of A/D must be faster than the
switching frequency. With a 1 MHz switching frequency
converter, the A/D conversion time should be less than 200ns
to give the controller enough time to compute. Moreover, the
resolution of the A/D must be high enough to achieve the
regulation range of output voltage specification. For example,
a 1% regulation range at Vs=15V is 0.15V, considering the
A/D input range is 30V, an 8 bits, 5 MSPS A/D was required.
A calibrated delay-line A/D or a non-linear A/D could be a
good solution for this problem. This question will be
discussed after the silicon implementation.

boundary conditions are set to separate voltage feedback

scale into 3 ranges. These boundary conditions are related
with the reference voltage. The definitions of the boundary
conditions are illustrated in (1).
Different control algorithms are applied for each range in
order to get the stability, speed and accuracy.
(i) If the output voltage is located in range 1, the
feedback is far away from the reference voltage, a high
speed algorithm is applied (Z-transfer or Fuzzy).
(ii) If the output voltage is located in range 2, the
feedback is close to the reference voltage, an algorithm
with good stability and precision (dither) is applied.
(iii) If the output voltage is located in range 3, the output
voltage is higher than the reference. An algorithm with
only consideration of speed is applied here to protect the
following devices.

Therefore, the duty cycle command must be computed

under the remaining 800ns and transfer to the cache inside
Digital Pulse-Width Modulation (DPWM). For example, a
control algorithm composed by 100 steps computing needs a
controller running faster than 125MHz. However, it can be
easily implemented with CMOS technology but the power
consumption may not be accepted by a portable device
(Mobil phone, pocket pc). Hence, a loop-up table is used
instead of real time computing. For an 8 bits A/D resolution,
a 4kB memory is sufficient for the Z-transfer-Dither based or
Fuzzy-Dither based controller and the chip area is acceptable.
Fig. 3: scheme of mixed approach controller

Fig.3 shows the scheme of the mixed approach controller.

Several control algorithms are integrated inside. Once a
voltage feedback signal arrives in the controller, a logic cell
decides which control algorithm will be started depending on
which range the feedback signal is located.
A. Dither controller
Four comparators were proposed here to evaluate the
output voltage.
Fig. 2: Mixed approach principle

III.

MIXED CONTROL METHOD

Lot of control algorithms were built in the last decade for

digital controlled voltage converter. However, with the
increase of the switching frequency, it is hard to find an
algorithm which has high speed and good stability at the
same time. Therefore, a control method with several
algorithms mixed is developed here.
Fig.2 shows the principle of the mixed approach. 2

Vub

Vlb

Vref * Cub
Vref * Clb

(1)

Fig. 4: Principle of dither controller

As shown in Fig 4, two comparators with decision level of

large range (typically, 5%) above or below the reference
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voltage for the fast recovery are applied by an other control

method, like for instance a look-up table based controller.
The two internal levels are set to the maximum possible
ripple voltage (typically, 1%). These two internal levels
generate three states, dither_up, dither_down and continue.
When the output is located in dither_up area, the digital
error signal will grow up for 1 step each three switching
cycles. Since the duty cycle increment is limited versus
switching frequency, a much better stability is achieved. The
digital error signal will decrease 1 step for each three
switching cycles if the output voltage is located in
dither_down range and 1 step per cycle for discontinue range.

IV.

SIMULATION AND IMPLEMENTATION VERIFICATION

Design verification is in process for testing the

functionality and performance of the design. There are two
complementary methods to verify the design: simulation and
FPGA based implementation verification (silicon based
implementation verification is coming soon).
A. Simulation
Several VHDL-AMS based models are built and simulated
under Advanced MS to compare the performances of mixed
and non-mixed approach.

In the continuous range, a 16 steps dither is applied to

increase the precision of the DPWM output. For example, the
result of duty cycle steps computed by controller is 73.3, the
dither controller will output 73 steps, 73 steps, 74 steps in
three clock cycle instead of one output of 73. In this way,
with a 16 steps dither, the precision of DPWM will be
increase from 8 bits to 12 bits.

(a)

Non-mixed approach

(b) Mixed approach

Another stability controller is also applied in the dither_up

and dither_dwon areas to increase the stability of the system.
The digitalized voltage feedback is compared with the
previous one. If E(n) E(n-1) is too high, that means the
raising speed of Vout is too fast, and it is dangerous for the
stability. In this condition, the duty cycle will be decreased by
the stability controller. For the same reason, if E(n) E(n-1)
is too low, a certain number will be added to the duty cycle.
B. Z-transfer controller
Z transfer with look-up table controller was presented in
[20]-[25]. The controller can be reprogrammed to perform
different control laws simply by programming the entries in
the look-up tables.

Fig. 5: Comparison of two approaches in the same conditions

Fig 5 shows the comparison between mixed and

non-mixed simulation results. The upper fig is based on
Z-tranfer controller without mixed approach. Overshot and
stability problem can be found here. Lower figure shows the
result based on the same transfer function but with mixed
approach, here, we can see that the result is much better.
B. FPGA Based Implementation and Verification

The function of that applied is:

d(n + 1) = d(n) + (e(n)) + (e(n-1)) + (e(n-2))
Where (), () and () are linear or nonlinear functions
of the digital error signal. A variety of control laws can be
implemented. For example,
d(n + 1) = d(n) + ae(n) + be(n-1) + ce(n-2)
Where a, b, and c are constants, corresponds to the basic
PID controller. In the controller design, once the coefficients
a, b and c are selected, the products (a e), (b e), and (c e)
are pre-computed for all possible values of the digital
feedback form A/D, and pre-programmed into the look-up
tables from an external memory.

Fig. 6: Block diagram of FPGA based implementation

A block diagram of the complete FPGA based

implementation is shown in Figure 6. The switching
controller and the digital pulse-width modulation are
accomplished using an FPGA based board. The system
includes a synchronous boost converter, a digital controller,
an A/D converter and 6 comparators. The FPGA control
board includes the Altera Cyclone (EP1C20 chip). The signal
Vb obtained from the output voltage rescaled by two high
resistances, and is used as the feed back to be sent to A/D. An
8 bits bus is used to transfer the digitalized feed back signal
from A/D to FPGA and the PWM signal is transferred back to

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the power stage board by a cable.

Power on

Start up
Reset

Vout
Enable

Fig. 9: layout of controller

Fig. 7: start up sequence of FPGA implementation

The filter inductor L = 10 H and the capacitor C = 1 F

are selected so that the running mode is kept at CCM. Figure
7 shows the start up sequence and Figure 8 shows the
experimental ripple waveforms in the DC-DC converter
operating in CCM. Fig 7 shows that when there is an enable
signal, the output voltage is raising fast and quickly to be
stable. Fig 8 shows the ripple is less than 30mV when output
voltage is at 10V. Considering the background noise of the
test bench, this result is match with the simulation expected.

Dimming is a technology to control the LED backlight. A

PWM signal is used to command the SMPS to power on and
off. Because a high frequency (ex: 300 Hz) flash can not
Vout
Command

Zoom of
Start-up

Fig. 10: dimming

sense by human, with the increase or decrease of duty cycle,

what we can find is the change of brightness. Figure 10
shows the performance of SMPS under dimming condition.
Four LEDs are drive by this step-up SMPS. Here the
command signal is a 300 Hz PWM signal with 50% duty
cycle. We can find that the start-up edge of output voltage is
less then 100us.

Fig. 8: delta Vout in CCM mode

C. Silicon Implementation
A full intergraded prototype with controller and power
stage include is applied by STMicroelectronics. Figure 9
shows the layout. In which there are two digital boost
controllers inside with 1 MHz switching frequency and 10
MHz switching frequency.
The digital controller is described in VHDL, Synopsys
synthesis and timing verification tools were used for design.
Some additional control methods were added in controller to
provide a faster start-up speed.

V.

CONCLUSION

This paper describes the design and implementation of a

high switching frequency boost DC-DC converter. A new
control method, mixed approach is applied and implemented
on the FPGA and silicon. Simulation and implementation
results show that the stability and performance of the
converter based on this mixed approach are improved.
Another advantage of this method is that the output accuracy

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is also increased to 10 bits with a 8 bits digital PWM.

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