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Description
The CS4334 family members are complete, stereo digital-to-analog output systems including interpolation, 1-bit
D/A conversion and output analog filtering in an 8-pin
package. The CS4334/5/6/7/8/9 support all major audio
data interface formats, and the individual devices differ
only in the supported interface format.
LRCK
SDATA
DEM/SCLK
2
AGND
6
VA
Serial Input
Interface
De-emphasis
Voltage Reference
Interpolator
Modulator
DAC
Analog
Low-Pass
Filter
Interpolator
Modulator
DAC
Analog
Low-Pass
Filter
3
1
AOUTL
AOUTR
4
MCLK
SEP 99
DS248PP3
1
CS4334/5/6/7/8/9
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS ...................................................... 4
ANALOG CHARACTERISTICS................................................................... 4
POWER AND THERMAL CHARACTERISTICS ......................................... 6
DIGITAL CHARACTERISTICS.................................................................... 7
ABSOLUTE MAXIMUM RATINGS .............................................................. 7
RECOMMENDED OPERATING CONDITIONS .......................................... 7
SWITCHING CHARACTERISTICS ............................................................. 8
2. TYPICAL CONNECTION DIAGRAM ........................................................... 10
3. GENERAL DESCRIPTION .......................................................................... 11
3.1 Digital Interpolation Filter ................................................................... 11
3.2 Delta-Sigma Modulator ...................................................................... 11
3.3 Switched-Capacitor DAC ................................................................... 11
3.4 Analog Low-Pass Filter ...................................................................... 11
4. SYSTEM DESIGN ........................................................................................ 12
4.1 Master Clock ...................................................................................... 12
4.2 Serial Clock ........................................................................................ 12
4.2.1 External Serial Clock Mode ...................................................... 12
4.2.2 Internal Serial Clock Mode ....................................................... 12
4.3 De-Emphasis ..................................................................................... 12
4.4 Initialization and Power-Down ........................................................... 12
4.5 Output Transient Control ................................................................... 13
4.6 Grounding and Power Supply Decoupling ......................................... 13
4.7 Analog Output and Filtering ............................................................... 13
4.8 Overall Base-Rate Frequency Response .......................................... 17
4.9 Overall High-Rate Frequency Response ........................................... 18
4.10 Base Rate Mode Performance Plots ............................................... 19
4.11 High Rate Mode Performance Plots ................................................ 20
5. PIN DESCRIPTIONS ................................................................................... 21
6. PARAMETER DEFINITIONS ....................................................................... 22
7. REFERENCES ............................................................................................. 22
8. ORDERING INFORMATION: ...................................................................... 23
9. FUNCTIONAL COMPATIBILITY ................................................................. 23
10. PACKAGE DIMENSIONS .......................................................................... 24
DS248PP3
CS4334/5/6/7/8/9
LIST OF FIGURES
Figure 1.Output Test Load .................................................................................... 6
Figure 2.Maximum Loading................................................................................... 6
Figure 3.Power vs. Sample Rate .......................................................................... 6
Figure 4.External Serial Mode Input Timing.......................................................... 9
Figure 5.Internal Serial Mode Input Timing ........................................................... 9
Figure 6. Internal Serial Clock Generation ............................................................ 9
Figure 7.Recommended Connection Diagram.................................................... 10
Figure 8.System Block Diagram.......................................................................... 11
Figure 9.De-Emphasis Curve (Fs = 44.1kHz) ..................................................... 13
Figure 10.CS4334 Data Format (I2S).................................................................. 14
Figure 11.CS4335 Data Format .......................................................................... 14
Figure 12.CS4336 Data Format .......................................................................... 14
Figure 13.CS4337 Data Format .......................................................................... 15
Figure 14.CS4338 Data Format .......................................................................... 15
Figure 15.CS4339 Data Format .......................................................................... 15
Figure 16.CS4334/5/6/7/8/9 Initialization and Power-Down Sequence .............. 16
Figure 17.Stopband Rejection............................................................................. 17
Figure 18.Transition Band................................................................................... 17
Figure 19.Transition Band................................................................................... 17
Figure 20.Passband Ripple................................................................................. 17
Figure 21.Stopband Rejection............................................................................. 18
Figure 22.Transition Band................................................................................... 18
Figure 23.Transition Band................................................................................... 18
Figure 24.Passband Ripple................................................................................. 18
Figure 25.0 dBFS FFT (BRM) ............................................................................. 19
Figure 26. -60 dBFS FFT (BRM)......................................................................... 19
Figure 27.Idle Channel Noise FFT (BRM)........................................................... 19
Figure 28.Twin Tone IMD FFT (BRM)................................................................. 19
Figure 29.THD+N vs. Amplitude (BRM) .............................................................. 19
Figure 30.THD+N vs. Frequency (BRM) ............................................................. 19
Figure 31.0 dBFS FFT (HRM)............................................................................. 20
Figure 32. -60 dBFS FFT (HRM)......................................................................... 20
Figure 33.Idle Channel Noise FFT (HRM) .......................................................... 20
Figure 34.Twin Tone IMD FFT (HRM) ................................................................ 20
Figure 35.THD+N vs. Amplitude (HRM).............................................................. 20
Figure 36. THD+N vs. Frequency (HRM)............................................................ 20
DS248PP3
CS4334/5/6/7/8/9
1. CHARACTERISTICS/SPECIFICATIONS
High-Rate Mode
Min
Typ
Max
Min
Typ
Max
Unit
-10
70
-10
70
88
91
86
89
93
96
91
94
91
89
90
96
88
94
dB
dB
dB
dB
-88
-73
-33
-86
-71
-31
-83
-68
-28
-81
-66
-26
-88
-70
-30
-86
-68
-28
-83
-65
-25
-81
-63
-23
dB
dB
dB
dB
dB
dB
94
95
dB
-40
85
-40
85
85
88
83
86
93
96
91
94
88
86
90
96
88
94
dB
dB
dB
dB
-88
-73
-33
-86
-71
-31
-82
-65
-25
-70
-63
-23
-88
-70
-30
-86
-68
-28
-82
-62
-22
-80
-60
-20
dB
dB
dB
dB
dB
dB
94
95
dB
DS248PP3
CS4334/5/6/7/8/9
ANALOG CHARACTERISTICS (Continued)
Base-rate Mode
Parameter
Symbol
Min
Typ
Max
High-Rate Mode
Min
Typ
Max Unit
Passband
Parameters
dc Accuracy
Interchannel Gain Mismatch
Gain Error
Gain Drift
Analog Output
Full Scale Output Voltage
Quiescent Voltage
Max AC-Load Resistance
Max Load Capacitance
Symbol
(Note 6)
(Note 6)
VQ
RL
CL
Fs
Fs
Fs
dB
dB
Fs
dB
s
s
s
dB
dB
dB
Min
Typ
Max
Units
0.1
5
100
0.4
-
dB
%
ppm/C
3.25
-
3.5
2.2
3
100
3.75
-
Vpp
VDC
k
pF
DS248PP3
CS4334/5/6/7/8/9
POWER AND THERMAL CHARACTERISTICS
Parameters
Power Supplies
Power Supply Current
normal operation
power-down state
(Note 7)
normal operation
power-down
Power Dissipation
(1 kHz)
Symbol
Min
Typ
Max
Units
IA
IA
15
40
19
-
mA
A
JA
PSRR
75
0.2
110
79
104
-
mW
mW
C/Watt
dB
10 F
V
out
AOUTx
R
AGND
100
70
75
Safe Operating
Region
50
25
2.5
3
65
HR
60
55
10
15
75
BR
125
Power (mW)
20
50
30
40
50
60
70
80
Sample Rate (kHz)
90
100
DS248PP3
CS4334/5/6/7/8/9
DIGITAL CHARACTERISTICS (TA = 25C; VA = 4.75V - 5.5V)
Parameters
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Input Capacitance
(Note 8)
Symbol
VIH
VIL
Iin
Min
2.0
-
Typ
8
Max
0.8
10
-
Units
V
V
A
pF
ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.)
Parameters
DC Power Supply
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
VA
Iin
VIND
TA
Tstg
Min
-0.3
-0.3
-55
-65
Max
6.0
10
VA+0.4
125
150
Units
V
mA
V
C
C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)
Parameters
DC Power Supply
DS248PP3
Symbol
VA
Min
4.75
Typ
5.0
Max
5.5
Units
V
CS4334/5/6/7/8/9
SWITCHING CHARACTERISTICS (TA = -40 to 85C; VA = 4.75V - 5.5V; Inputs: Logic 0 = 0V,
Logic 1 = VA, CL = 20pF)
Parameters
Symbol
Fs
Min
Typ
Max
Units
100
kHz
MCLK/LRCK = 512
10
1000
ns
MCLK/LRCK = 512
10
1000
ns
21
1000
ns
21
1000
ns
31
1000
ns
31
1000
ns
40
50
60
tsclkl
20
ns
tsclkh
20
ns
tsclkw
1
---------------------( 128 )Fs
ns
tsclkw
1
------------------( 64 )Fs
ns
tslrd
20
ns
tslrs
20
ns
tsdlrs
20
ns
tsdh
20
ns
50
ns
ns
ns
ns
(Note 9)
(Note 10)
tsclkw
tsclkr
tsdlrs
tsdh
tsdh
1
----------------SCLK
1
---------------------- + 10
( 512 )Fs
1
---------------------- + 15
( 512 )Fs
1
---------------------- + 15
( 384 )Fs
tsclkw
-----------------2
Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% +/ 1/2 MCLK Period.
10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK
ratio. (See figures 10-15)
DS248PP3
CS4334/5/6/7/8/9
LRCK
t sclkh
t slrs
t slrd
t sclkl
SCLK
t sdh
t sdlrs
SDATA
LRCK
t sclkr
SDATA
t sclkw
t sdlrs
t sdh
*INTERNAL SCLK
LRCK
MCLK
1
N
2
*INTERNAL SCLK
SDATA
DS248PP3
CS4334/5/6/7/8/9
2. TYPICAL CONNECTION DIAGRAM
+5V
+
7
0.1 F
1 F
VA
1
Audio
Data
Processor
2
3
SDATA
8
DEM/SCLK
AOUTL
LRCK
3.3 F
560
Left Audio
Output
+
267 k
10 k
RL
CS4334
CS4335
CS4336
CS4337
CS4338
CS4339
3.3 F
AOUTR
External Clock
MCLK
560
Right Audio
Output
+
267 k
10 k
AGND
C=
RL
R L + 560
4Fs(R L560)
10
DS248PP3
CS4334/5/6/7/8/9
3. GENERAL DESCRIPTION
The CS4334 family of devices offers a complete
stereo digital-to-analog system including digital interpolation, fourth-order delta-sigma digital-to-analog conversion, digital de-emphasis and analog
filtering, as shown in Figure 8. This architecture
provides a high tolerance to clock jitter.
The primary purpose of using delta-sigma modulation techniques is to avoid the limitations of resistive laser trimmed digital-to-analog converter
architectures by using an inherently linear 1-bit
digital-to-analog converter. The advantages of a 1bit digital-to-analog converter include: ideal differential linearity, no distortion mechanisms due to resistor matching errors and no linearity drift over
time and temperature due to variations in resistor
values.
filter eliminates images of the baseband audio signal which exist at multiples of the input sample
rate. The resulting frequency spectrum has images
of the input signal at multiples of 4 Fs. These images are easily removed by the on-chip analog lowpass filter and a simple external analog filter (see
Figure 7).
The delta-sigma modulator is followed by a digitalto-analog converter which translates the 1-bit data
into a series of charge packets. The magnitude of
the charge in each packet is determined by sampling of a voltage reference onto a switched capacitor, where the polarity of each packet is controlled
by the 1-bit data. This technique greatly reduces the
sensitivity to clock jitter and provides low-pass filtering of the output.
Digital
Input
Interpolator
Delta-Sigma
Modulator
DAC
Analog
Low-Pass
Filter
Analog
Output
DS248PP3
11
CS4334/5/6/7/8/9
4. SYSTEM DESIGN
MCLK (MHz)
HRM
BRM
128x
192x
256x
384x
512x
4.0960 6.1440 8.1920 12.2880 16.3840
5.6448 8.4672 11.2896 16.9344 22.5792
6.1440 9.2160 12.2880 18.4320 24.5760
8.1920 12.2880
11.2896 16.9344
12.2880 18.4320
Table 1. Common Clock Frequencies
12
4.3 De-Emphasis
The CS4334 family includes on-chip digital de-emphasis. Figure 9 shows the de-emphasis curve for
Fs equal to 44.1 kHz. The frequency response of
the de-emphasis curve will scale proportionally
with changes in sample rate, Fs.
The de-emphasis filter is active (inactive) if the
DEM/SCLK pin is low (high) for 5 consecutive
falling edges of LRCK. This function is available
only in the internal serial clock mode.
DS248PP3
CS4334/5/6/7/8/9
capacitor to charge to VQ, effectively blocking the
quiescent DC voltage.
Gain
dB
T1=50 s
0dB
T2 = 15 s
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
The interpolation filters and delta-sigma modulators are reset, and the internal voltage reference,
one-bit digital-to-analog converters and switchedcapacitor low-pass filters are powered down. The
device will remain in the Power-Down mode until
MCLK and LRCK are present. Once MCLK and
LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the
MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Finally, power is applied to the D/A converters and switchedcapacitor filters, and the analog outputs will ramp to
the quiescent voltage, VQ.
CS4334/5/6/7/8/9
Left Channel
LRCK
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
I2
I2
S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Left Channel
LRCK
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
LRCK
Right Channel
Left Channel
SCLK
SDATA
23 22 21 20 19 18
23 22 21 20 19 18
32 clocks
14
DS248PP3
CS4334/5/6/7/8/9
LRCK
Right Channel
Left Channel
SCLK
SDATA
1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
LRCK
Right Channel
Left Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
LRCK
Right Channel
Left Channel
SCLK
SDATA
1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
DS248PP3
15
CS4334/5/6/7/8/9
16
DS248PP3
CS4334/5/6/7/8/9
4.8 Overall Base-Rate Frequency Response
0.1
0.08
Amplitude dB
0.06
0.04
0.02
0.02
0
DS248PP3
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Frequency (normalized to Fs)
0.4
0.45
17
CS4334/5/6/7/8/9
4.9 Overall High-Rate Frequency Response
0.25
0.2
Amplitude dB
0.15
0.1
0.05
0
0.05
0.1
0.15
0
18
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Frequency (normalized to Fs)
0.4
0.45
DS248PP3
CS4334/5/6/7/8/9
4.10 Base Rate Mode Performance Plots
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
dBr
A
dBr A
d
B
r
A
-40
-40
-40
-50
-50
-50
-60
-60
-60
dBr
A
dBr A
-40
-40
-40
-50
-50
-50
-60
-60
-60
d
B
r
-70
-70
-70
-80
-80
-80
-90
-90
-90
-70
-70
-70
-80
-80
-80
-90
-90
-90
-100
-100
-100
-110
-110
-110
-100
-100
-100
-110
-110
-110
-120
-120
-120
-130
-130
-130
-120
-120
-120
-130
-130
-130
-140
-140
-140
2k
2k
2k
4k
4k
4k
6k
6k
6k
8k
8k
8k
10k
10k
10k
Hz
Hz
Hz
12k
12k
12k
14k
14k
14k
16k
16k
16k
18k
18k
18k
-140
-140
-140
20k
20k
20k
20k
8k
8k
8k
10k
10k
10k
Hz
Hz
Hz
12k
12k
12k
14k
14k
14k
16k
16k
16k
18k
18k
18k
20k
20k
20k
18k
20k
20k
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
-40
-40
-40
dBr
dBr A
A
dBr
A
dBr A
-50
-50
-50
d
B
r
-70
-70
-70
-80
-80
-80
-90
-90
-90
-60
-60
-60
-70
-70
-70
-80
-80
-80
-90
-90
-90
-100
-100
-100
-100
-100
-100
-110
-110
-110
-110
-110
-110
-120
-120
-120
-130
-130
-130
-140
-140
-140
6k
6k
6k
-40
-40
-40
-50
-50
-50
-60
-60
-60
4k
4k
4k
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
d
B
r
2k
2k
2k
-120
-120
-120
-130
-130
-130
2k
2k
2k
4k
4k
4k
6k
6k
6k
8k
8k
8k
10k
10k
10k
Hz
Hz
Hz
12k
12k
12k
14k
14k
14k
16k
16k
16k
18k
18k
18k
20k
20k
20k
-140
-140
-140
2k
2k
2k
4k
4k
4k
6k
6k
6k
8k
8k
8k
10k
10k
10k
Hz
Hz
Hz
12k
12k
12k
14k
14k
14k
1 6k
16k
16k
18k
18k
20k
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)
-60
-60
+0
+0
+0
-10
-10
-10
-20
-20
-20
-70
-70
-30
-30
-30
-90
-90
-40
-40
-40
dBr
dBrAA
dBr A
d
B
r
-80
-80
d
B
r
A
-50
-50
-50
-60
-60
-60
-70
-70
-70
-80
-80
-80
-100
-100
-90
-90
-90
-100
-100
-100
-110
-110
-60
-60
-50
-50
-40
-40
-30
-30
-20
-20
-10
-10
+0
+0
dBFS
dBFS
-110
-110
-110
20
20
20
50
50
50
100
100
100
200
200
200
500
500
500
Hz
Hz
Hz
1k
1k
1k
2k
2k
2k
5k
5k
5k
10k
10k
10k
20k
20k
20k
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain
System Two Cascade.
DS248PP3
19
CS4334/5/6/7/8/9
4.11 High Rate Mode Performance Plots
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
-40
-40
-40
-50
-50
-50
-60
-60
-60
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
dBr
A
dBr A
dBr
A
dBr A
d
B
r
d
B
r
-70
-70
-70
-80
-80
-80
-90
-90
-90
-40
-40
-40
-50
-50
-50
-60
-60
-60
-70
-70
-70
-80
-80
-80
-90
-90
-90
-100
-100
-100
-110
-110
-110
-100
-100
-100
-110
-110
-110
-120
-120
-120
-130
-130
-130
-120
-120
-120
-130
-130
-130
-140
-140
-140
2k
2k
2k
4k
4k
4k
6k
6k
6k
8k
8k
8k
10k
10k
10k
Hz
Hz
Hz
12k
12k
12k
14k
14k
14k
16k
16k
16k
18k
18k
18k
-140
-140
-140
20k
20k
20k
2k
2k
2k
4k
4k
4k
12k
12k
12k
14k
14k
14k
16k
16k
16k
18k
18k
18k
20k
20k
20k
0 8 /0 5 /9 9 1 1 :1 1 :3 6
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
-40
-40
-40
-40
-40
-40
-50
-50
-50
-60
-60
-60
dBr
A
dBr A
dBr
A
dBr A
-50
-50
-50
d
B
r
-70
-70
-70
-80
-80
-80
-90
-90
-90
-60
-60
-60
-70
-70
-70
-80
-80
-80
-90
-90
-90
-100
-100
-100
-110
-110
-110
-100
-100
-100
-110
-110
-110
-120
-120
-120
-130
-130
-130
-140
-140
-140
10k
10k
10k
Hz
Hz
Hz
A ud io P re c is io n
8k
8k
8k
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
d
B
r
6k
6k
6k
-120
-120
-120
-130
-130
-130
2k
2k
4k
4k
4k
2k
6k
6k
6k
8k
8k
8k
10k
10k
10k
Hz
12k
12k
12k
14k
14k
14k
16k
16k
16k
18k
18k
18k
-140
-140
-140
20k
20k
20k
2k
2k
2k
Hz
Hz
4k
4k
4k
6k
6k
6k
8k
8k
8k
10k
10k
10k
Hz
HzHz
12k
12k
12k
14k
14k
14k
16k
16k
16k
18k
18k
18k
20k
20k
20k
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)
-60
-60
+0
+0
+0
-10
-10
-10
-20
-20
-20
-70
-70
-30
-30
-30
-90
-90
d
B
r
-40
-40
-40
dBrdBrAA
-80
-80
dBr A
d
B
r
-50
-50
-50
-60
-60
-60
A
-70
-70
-70
-80
-80
-80
-100
-100
-90
-90
-90
-100
-100
-100
-110
-110
-60
-60
-50
-50
-40
-40
-30
-30
-20
-20
-10
-10
+0
+0
dBFS
dBFS
-110
-110
-110
20
20
20
50
50
100
100
100
200
200
200
500
500
Hz
Hz
Hz
1k
1k
2k
2k
5k
5k
10k
10k
10k
20k
20k
20k
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain
System Two Cascade.
20
DS248PP3
CS4334/5/6/7/8/9
5. PIN DESCRIPTIONS
SERIAL DATA INPUT
SDATA
AOUTL
DE-EMPHASIS / SCLK
DEM/SCLK
VA
ANALOG POWER
LRCK
AGND
ANALOG GROUND
MASTER CLOCK
MCLK
AOUTR
No.
1
Pin Name
SDATA
DEM/SCLK
LRCK
MCLK
5
6
7
8
AOUTR
AGND
VA
AOUTL
DS248PP3
I/O
Pin Function and Description
I Serial Audio Data Input - twos complement MSB-first serial data is input on this pin.
The data is clocked into the CS4334/5/6/7/8/9 via internal or external SCLK, and the
channel is determined by LRCK.
I De-Emphasis/External Serial Clock Input - used for de-emphasis filter control or external serial clock input.
I Left/Right Clock - determines which channel is currently being input on the Audio Serial
Data Input pin, SDATA.
I Master Clock - frequency must be 256x, 384x, or 512x the input sample rate in BRM and
either 128x or 192x the input sample rate in HRM.
O Analog Right Channel Output - typically 3.5 Vp-p for a full-scale input signal.
I Analog Ground - analog ground reference is 0V.
I Analog Power - analog power supply is nominally +5V.
O Analog Left Channel Output - typically 3.5 Vp-p for a full-scale input signal.
21
CS4334/5/6/7/8/9
6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)- The ratio of the rms value of the signal to the
rms sum of all other spectral components over the specified bandwidth (typically 10Hz to
20kHz), including distortion components. Expressed in decibels.
Dynamic Range - The ratio of the full scale rms value of the signal to the rms sum of all other
spectral components over the specified bandwidth. Dynamic range is a signal-to-noise
measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added
to the resulting measurement to refer the measurement to full scale. This technique ensures that
the distortion components are below the noise level and do not effect the measurement. This
measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and
the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured
for each channel at the converters output with all zeros to the input under test and a full-scale
signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch - The gain difference between left and right channels. Units in
decibels.
Gain Error - The deviation from the nominal full scale analog output for a full scale digital
input.
Gain Drift - The change in gain value with temperature. Units in ppm/C.
7. REFERENCES
1) "How to Achieve Optimum Performance from
Delta-Sigma A/D & D/A Converters" by
Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2) CDB4334/5/6/7/8/9 Evaluation Board Datasheet
22
DS248PP3
CS4334/5/6/7/8/9
8. ORDERING INFORMATION:
Model
CS4334-KS
CS4335-KS
CS4336-KS
CS4337-KS
CS4338-KS
CS4339-KS
CS4334-BS
CS4335-BS
CS4336-BS
CS4337-BS
CS4338-BS
CS4339-BS
Temperature
-10 to +70 C
-10 to +70 C
-10 to +70 C
-10 to +70 C
-10 to +70 C
-10 to +70 C
-40 to +85 C
-40 to +85 C
-40 to +85 C
-40 to +85 C
-40 to +85 C
-40 to +85 C
Package
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
Serial Interface
16 to 24-bit, I2S
16 to 24-bit, left justified
24-bit, right justified
20-bit, right justified
16-bit, right justified
18-bit, right justified, 32 Fs Internal SCLK mode
16 to 24-bit, I2S
16 to 24-bit, left justified
24-bit, right justified
20-bit, right justified
16-bit, right justified
18-bit, right justified, 32 Fs Internal SCLK mode
9. FUNCTIONAL COMPATIBILITY
CS4330-KS CS4339-KS
CS4331-KS CS4334-KS
CS4333-KS CS4338-KS
CS4330-BS CS4339-BS
CS4331-BS CS4334-BS
CS4333-BS CS4338-BS
DS248PP3
23
CS4334/5/6/7/8/9
10. PACKAGE DIMENSIONS
1
b
c
D
SEATING
PLANE
A
L
e
A1
INCHES
DIM
A
A1
B
C
D
E
e
H
L
MIN
0.053
0.004
0.013
0.007
0.189
0.150
0.040
0.228
0.016
0
MAX
0.069
0.010
0.020
0.010
0.197
0.157
0.060
0.244
0.050
8
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.02
1.52
5.80
6.20
0.40
1.27
0
8
JEDEC # : MS-012
24
DS248PP3
Notes