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Detailed Solutions A- 09
JUNE 2003
JUNE 2003
Q1. a.
b.
AB and BC .
AB + BC .
Thus, the output Y = A + AB + BC + C .
c.
d.
e.
0 1 Va 1 2 1
+
+
= 0 , or Va = 0V .
2K
2K
2K
Also, KCL at the ve terminal of second Op Amp gives
0 2 1 2 Vo 2
+
+
= 0 , or Vo = 8V .
2K
1K
1K
f.
g.
h.
PART I
Q2. a. By virtual ground the voltage at the ve terminals of the two OpAmps are
Vo
and
8
1V respectively. Assume that Va is the voltage at output of the first OpAmp Then,
KCL at the ve terminal of first OpAmp gives
Vo
V
Va o
8 +
8 = 0 , or V = 3Vo 1 .
a
1K
2K
8
Vo 1 V a 1
3 Vo
+
= 0 , or Va =
.
8K
4K
2
Eliminating Va from the two equations,
b.
c.
Vo =
20
volts.
7
Q3.
Q4.a.
V
Ia = a
R
V a (1 + 2sCR )
1 + 1 + 2sCR = 2 + 2sCR .
I1 = I a [1 + 2 sCR ] =
Va
.
2 + 2 sCR
Similarly, the current going towards ve terminal of the OpAmp from the second
T-network can be written as
I2 =
Rs 2 C 2Va
.
2 + 2 sCR
Vi V p
R1
Vp
R2
+ (V p Vo ) sC + V p sC
and
V p sC =
Vo
R3
Vo
(1 R1C ) s
= 2
Va s + (2 R3C ) s + 1 R ' R3C 2
(4b.1)
Vo
A ( Q ) s
= 2 0 0
,
Va s + ( 0 Q ) s + 02
(4b.2)
2Q
1
,
R' = 2
0C
0 R3C 2
40
-7
. Choosing C=10 F, gives
From the data given, 0 = 4000 , A0 = 20 , Q =
3
4
6
R R'
10
10
1
,
,
R1 =
R3 =
R2 = 1 ' =
6
15
0.3994
R1 R
R1 =
Q5.a.
b.
Q
,
A0 0 C
R3 =
12
12
11
=
volts, Weightage of MSB = 2 , and
12
4096
2
12
,
Input voltage corresponding to all 1 s at the output = 12 1 2
11.997 volts.
Resolution =
Q6.a.
The gain of the RC network of the given oscillator circuit can be obtained as
Gain( s ) =
R
1
3R +
+ R 2 sC
sC
R'
R1 +
R
R'
LG ( s ) = 1 + Gain( s ) =
R
1
3R +
+ R 2 sC
sC
0 =
1
RC
0 , LG ( j 0 ) = 10 o , which gives
and
R'
R1 +
R
= 1 or R ' = 2 R
3R
b. Refer to Section 8.8 [3] for derivation of the propagation delay time given by
t PHL =
Cload
kN
V DD VGS + VT
1.15
+
2
(VGS + VT )
(VGS + VT )
= 0.175s .
PART II
Q7.a.
F ( A, B, C , D ) = 0,2,5,6,13,14 + 8,9
AB
00
01
11
10
00
01
11
10
CD
F ( A, B, C , D ) = A B D + B C D + B C D
which can be realized using four 3- input NAND gates as
b.
From the figure of the counter, the required table can be written as
Q0
0
1
0
0
1
0
PS
Q1 Q2
0 0
0 0
1 0
0 1
0 1
1 1
Q0
1
0
0
1
0
0
NS
Q1 Q2
0 0
1 0
0 1
0 1
1 1
0 0
J0
1
1
0
1
1
0
K0
1
1
1
1
1
1
J1
0
1
0
0
1
1
K1
1
1
1
1
1
1
J2
0
0
1
0
0
1
K2
0
0
1
0
0
1
Cin
Cin
Cin
Cin
Sum
B
Q8.b.
C in
C in
Cout
To implement F1, F2, F3 using a ROM requires the ROM to have three outputs.
4
Since the functions are of four variables, the ROM is required to have 2 =16
Locations. Thus, the size of the ROM is 16x3. The data in the ROM is as per the
Truth-table of the functions as shown below, where x means 0 or 1.
ABCD
0000
0001
0010
0011
Q9.a.
F 1F 2 F 3
1 0 0
0 0 0
0 0 0
0 0 x
ABCD
0100
0101
0110
0111
F 1F 2 F 3
0 1 0
0 1 x
0 1 0
0 1 x
ABCD
1000
1001
1010
1011
F1 F2 F3
0 1 0
0 1 0
0 1 0
0 1 0
ABCD
1100
1101
1110
1111
F1 F2 F3
0 0 0
0 0 1
0 1 0
1 1 1
Assuming that the input impedance of the CMOS gate is infinite and that the gate
delays are zero, the waveforms at various points in the given monostable circuit are as
given below with V1 as the waveform at the output of first NOR gate.
Vi
V1
Vo
VR
A sudden change in Vo is transferred to the resistance R. The capacitor C discharges till
VR equals the threshold voltage of the driver transistor of the NOR gate (assume it to be
0.5VDD). At this time, V1 suddenly switches to VDD and Vo to zero. This change is also
transferred to R and the capacitor then charges asymptotically to zero. Thus, during the
time when Vo = VDD (logic 1),
V R = V DD 1 e t / RC
3
b.
-6
-6
where RC=(50x10 )x(0.01x10 )=5x10 s. The time period T of the output pulse will end
-6
when VR = 0.5VDD. For this condition, T can be evaluated as 7.2x10 s.
The truth-table and the excitation table of the flipflop are as given below
X Y
Qn+1
Exc.
X Y
0 0
Qn
00
1 x
0 1
1 0
1 1
1
0
01
10
11
0 x
x 0
x 1
Qn
Logic
Y
The truth table for this logic can be written as
X Y Qn
0
0
0
0
0
0
1
1
0
1
0
1
Qn +1
1
0
1
1
J K
X Y Qn
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
1
0
1
Qn +1
0
0
0
1
J K
0
0
0
0
1
1
0
0
J = X and K = Y .
Q10.a. For 4-bit 2s complement adder/subtracter, refer to Sections 7.2, 7.3 [2].
b. For a TTL to CMOS interface, refer to Section 8.12 [3] and for a TTL to ECL
interface, refer to Section7.12 [3]
Q11.
(i)
(ii)
(iii)
(iv)
(v)
(vi)
DEC2003
Q1.a.
b.
1
where f = 10KHz and
fC
C = 1 .5 F .
6
c.
d.
e.
f.
g.
H ( s) =
h.
s
s+ 1
, which is proportional to s if
RC
1
>> f .
RC
PART I
Q2. a. For biquadratic transfer functions, refer to Table 12.16 [1]
b.
With finite gain A, the negative input terminal of the Opamp will be at
Vo .
A
Vo
Vo
Vo
1
1
1
A = A
+ R1 +
, or Vin R2 = Vo R2 + R1 +
R2
A
sC 0
sC 0
R1 + 1
sC 0
Vin
Substituting for
A0 p
A =
s
function as
Vo
=
Vin
sR2 (A0 p )
1 A0 p
s + s A0 p R1 +
+
C
C0
0
Q3.a.
The figure below shows the circuit of noninverting amplifier. The Opamp has an
input impedance of Rin and the current flowing through it develops a small
voltage V with the polarity shown in the figure. The KCL equation at negative
terminal of Opamp can be written as
Vs V Vs V V0
V
+
=
= I in
R1
R2
Rin
Vs V0
=
+ 1(R1 R2 ) + Rin
I in R2 I in
For details of the given logarithmic amplifier, refer to Section 16.13 [2].
The conditions are required for the circuit to be a logarithmic amplifier are:
(i)
(ii)
v BE 2 = VT ln iC 2 .
(iii)
The base voltage of Q2 be very small compared to VREF.
b. For Sample and Hold circuits, refer to Section 16.2 [2].
Q5.a.
b.
Q6.
(i)
(ii)
(iii)
(iv)
PART II
Q7.a. For Transfer Characteristics of TTL, refer to Sections 6.5, 6.6, 6.7 [3].
b. For TTL-CMOS interfacing, refer to Section 8.12 [3].
Q8.a.
b. For PROM, refer to Section 11.6 [1]. For PAL and PLA, refer to Sections 7.14 and 7.15 [2].
Q9.a. For rule of CMOS gate formation, refer to Section 10.3 [1]. Using this rule, the following
circuit for the given function results.
b. A circuit for a 3-digit display using using only one decoder is shown below. The
data to be displayed by the three displays comes in to the display decoder serially.
The displays are also turned ON serially (one at a time) by mutually exclusive
waveforms applied to the displays as shown in the figure. Thus, a single BCD to
7-segment decoder can be multiplexed to turn ON the three displays.
Sum = A B C
C out = AB + BC + CA
The implementation using two 4:1 multiplexers is shown in the figure.
Cin
Cin
Cin
Cin
Sum
B
Q11.
(i)
(ii)
(iii)
(iv)
C in
C in
Cout
For comparison between TTL and ECL, refer to Section 7.1 [3].
For Shift Registers, refer to Section 8.5 [2].
For Memory Organization, refer to Sections 12.16,12.17 [3].
For Synchronous and Asynchronous counters, refer to Sections 8.6,8.7 [2].
Q1.a.
b.
Vo
(R2 R1 ) . Its Bode
=
Vi s CR2 + 1
d.
e.
f.
After 16 pulses the counter will come back to the state it started
with (1001). Another 7 pulses will take it to 0000.
h.
h.
The time taken for the input pulse to ripple through all the N flipflops will be 12N nsec. Thus, the maximum speed of operation of
-9
the counter is 1/(12x10 N).
3 ( 3)
= 24 volts s .
0.25 x10 6
1
10 x10 6
9
12 x10 N
N
PART I
Q2. a. Refer to Sections 2.1, 2.2 [1].
Gain at corner frequency is equal to Open loop gain (in dB) 3dB. If the open
5
5
loop gain is 10 , then gain at corner frequency = 20log1010 3 = 97 dB.
b. Compensating capacitor avoids oscillations in an amplifier by reducing its gain at a
0
frequency at which the phase shift is 180 . Such compensating capacitor introduces an
additional pole at a frequency much lower than the frequencies of the natural poles of the
amplifier. As such, the gain of the amplifier drops to unity at a smaller frequency.
If the slew rate is 1V s , the smallest duration in which the output can change by 10V
is 10 s .
slew rate
10 6
=
= 15915 Hz
2 Vmax
2 10
c. For 10 degree change in temperature, the offset voltage will be 300 V while the
Maximum frequency of sine wave =
offset current will be 3nA. Thus, the Op-Amp inverter with input voltage, offset
voltage and offset current is as shown in the figure below. The output voltage is
obtained by writing KCL at the inverting terminal as
Vo 0.3mV Vi 0.3mV
+
= 3nA .
100 K
1K
Thus,
Q3.a.
c.
Q4.
max = 10 log10 1 + 2
Thus,
= 10 (
max
10 )
N CH
).
A = 10
min
20
, as
0.122
=
=
= 3 .4
1
1 S
cosh
[
2
]
cosh
P
The order must be an integer. Thus NCH = 4. Similarly, the order NBW of the Butterworth
filter having same specifications can be obtained from the following equation as
N CH
0
.
122
=
= 5 .5 ,
S
log
[
2
]
10
log10
P
or NBW = 6, which is 2 higher than the order used for Chebyshev filter.
Q5.a.
The flash analog to digital converter is the fastest conversion method. A 4-bit
4
flash converter uses 2 -1=15 comparators. The analog input Va is applied to the
positive terminal of each comparator. The negative terminal of the comparators
is supplied with equally spaced reference voltages obtained from a potential
4
10 20 30
150
, , , .......,
.
16 16 16
16
Inputs
W 15 W 14 W 13 W 12 W 11 W 10 W 9 W 8 W 7 W 6 W 5 W 4 W 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The logic for the priority encoder can be obtained as per the following truth table.
W2
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
W1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Y3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
If time taken for comparison is 50ns and that for priority encoder is 35ns, then total time for
conversion is 85ns. Thus, the maximum possible conversion rate is
1
= 11.8MHz .
85ns
The output Y3Y2Y1Y0 for inputs 0V, 5.1V and 10V will be, respectively, 0000, 1010 and 1111.
b. For IC power amplifiers, refer to Section 14.8 [1]
Q6.
Q7.a.
The truth table for BCD to Excess-3 code is shown in the truth table given below.
ROM Address
W4 W3 W2
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
W1
0
1
0
1
0
1
0
1
0
1
ROM Outputs
Y3 Y2 Y1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
Y0
0
1
0
1
0
1
0
1
0
1
The table also shows the excess-3 outputs of the ROM for different BCD inputs
given as ROM address. The data stored in the ROM for remaining inputs is dont
care.
b. For truth table of Gray to binary converter, refer to Section 7.9 [2]. The corresponding
Boolean functions can be obtained from this table as
Y3 = W3
Y2 = Y3 W2
Y1 = Y2 W1
Y0 = Y1 W0
Outputs
Y2 Y1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
Y0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
B
0
0
C
0
0
D
0
1
f
0
0
0
1
1
1
1
0
0
0
1
0
1
0
0
0
1
1
1
1
0
1
1
1
b. The state diagram for the problem and the state table along with D inputs of the two
flipflops are as shown below.
PS
Q 1Q 0
0 0
0 1
1 0
Q9.a.
X=0
0 1
0 0
0 0
NS
X=1
1 0
1 0
1 0
D1
0
0
0
0
1
1
0
0
D0
0
1
1
1
1
0
0
0
The given circuit is a modulo-6 twisted ring (Johnson) counter, whose outputs Q0, Q1, Q2
are fed to an inverting summer amplifier. Count sequence of the counter is
000,100,110,111,011,001. Therefore, the output of the Opamp will be a repeating
sequence 0V, -1V, -2V, -3V, -2V, -1V changing at every falling edge of the clock. as
shown in the figure.
b.
(i)
(ii)
(iii)
(iv)
(v)
10
(5/1024) MHz, assuming a ripple counter.
1024
2060=1024+1024+12. Hence, counter will hold 12.
Yes, in case of a ripple counter. In a synchronous counter, the clock is applied
simultaneously to all flipflops and thus, the maximum frequency of operation
does not depend on the modulus of the counter.
Q10.a. A 2 D organized 16X1 memory is using two 2-4 decoders is shown in the figure below.
b. For programmable arrays, refer to Sections 7.14, 7.15 [2].
c.
Q11.
a.
b.
c.
d.
f.
When inputs are 00, both outputs are 1. Switching the input to 11
makes one of the outputs race to 0 .
g.
h.
PART I
Q2.a.
With Opamp replaced by its equivalent circuit, the given amplifier can be drawn as shown
in the figure where Vi = -2.1V. The node equations at negative and positive terminals of
the Opamp may be respectively written as
V V A V AV
V
+
=0
1K
11K
1M
and
V B V+
V
V
=
+ +
1K
1M 11K
VB V A = 2.1V gives
b. Same figure can be used to obtain the gain. Neglecting current through 1M input
impedance of the Opamp, the node equations can be written as
V A V V AV
=
1K
11K
and
V B V+
V
= +
1K
11K
Which give AV = 11(V B V A ) . Further, the following equations may be written for
currents through the three 1K resistances.
V A V = V+ V B = Vo AV
These two equations can be solved to get
gives
c.
Same figure can be used to obtain the gain. Writing KVL for the loop containing the
source, we get
VB VS V A VB V V A
+
=0
RS
2K
where
or
VB V A =
VS V VS
+
3 3
3
VS is the source voltage and RS =1K is the source resistance. Using the result of
Q2c gives
Vo = 10.5(V B V A ) = 10.5
VS
.
3
(i)
sp =
a b 2 4ac
a b 2 4ac
and s z =
2
2
Thus, the poles are at mirror image locations of the zeros as shown in the
figure.
(ii)
The magnitude of this allpass filter is K. For plots of magnitude and phase, refer
to p.1105 [1].
(iii)
(iv)
With
a=
H ( s) =
Or,
0
Q
K 2( 0 Q )s
Y ( s)
=K 2
X (s)
s + ( 0 Q )s + 02
Y ( s ) = ( 0 s )[2 X ( s ) + Y ( s )]
1 02
Y (s)
Q s2
Q4.
212
= 4.096ms = t1 .
10 6
= t1
Vin
Vref
t1+t2 = 6.144ms.
Q5.a.
For electron density distribution and explanation, refer to Section 1.20 [3].
(i)
(ii)
(iii)
(iv)
PART II
Q7.a.
-5
k p (12 Vi VT ) 2 = k n (Vi VT ) 2
Solving with kp=kn and VT = 2 volts, gives Vi = 6 volts.
PMOS will be in saturation if Vo - Vi < VT , or Vo < 8 volts. Also, NMOS will be in
saturation if Vi - Vo < VT , or Vo > 4 volts. The range when both transistors are in
saturation is 4< Vo <8.
Q8.a.
It is easily seen that for AB equal to 00, 01, 10, 11, the output of multiplexer will
0, 1, 1, 1, respectively. Thus f = A+B.
B
x
x
0
0
1
1
0
0
1
1
C
x
x
0
1
0
1
0
1
0
1
D E
0 x
0 x
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
O0
0
0
1
0
0
0
0
0
0
0
O1 O2 O3 O4 O5 O6 O7
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
1 0 0 0 0 0 0
0 1 0 0 0 0 0
0 0 1 0 0 0 0
0 0 0 1 0 0 0
0 0 0 0 1 0 0
0 0 0 0 0 1 0
0 0 0 0 0 0 1
Q9.a.
For an explanation of Master-Slave JK flipflop and its advantages, refer to Section 8.4 [2].
A NAND flipflop will take 2 gate delays to stabilize the output after the inuts are applied.
Thus, both Master and Slave sections of the flipflop require 3 gate delays. Add 1 gate
delay for the gate used for complementing the clock. Thus the delay required after the
positive edge of the clock is 4 gate delays or 20ns.
b.
A sequence generator is a shift register whose first flipflop gets its D-input from the
present state of the shift register through a combinational logic as shown in the figure
below. The output of a flipflop in this circuit is a delayed version of its predecessor flipflop.
This makes the truth table of the logic block as shown below. From the truth table the
Boolean function for the sequence generator can be found to be D = Q0 Q2 .
Q0
0
0
0
0
1
1
1
1
Q1
0
0
1
1
0
0
1
1
Q2
0
1
0
1
0
1
0
1
f
0
0
0
0
0
0
0
0
The following table derives the operational sequence of the counter, assuming K2 = 1
and J2 = Q0.
PS
Q0
0
1
0
0
1
0
Q1 Q2
0 0
1 0
0 1
1 0
0 0
1 1
J0 K0
1 1
1 1
0 1
1 1
1 1
0 1
J1 K1
1 1
1 1
1 1
1 1
1 1
1 1
J2 K2
0 1
1 1
0 1
0 1
1 1
0 1
NS
Q0 Q1 Q2
1 1 0
0 0 1
0 1 0
1 0 0
0 1 1
0 0 0
(i)
(ii)
(iii)
(iv)