PDP TELEVISION

SERVICE MANUAL
MODEL NO. H-PDP4201

Hyundai

Please read this manual carefully before service.

CONTENTS
Part:PP06 Chassis Features and Circuit
Part:Introduction on Circuit Functions of PT4206
Part:Analysis on Signal Process of PT4206
Part:Typical Defectives and Repair of PT4206
Annex:

1Main Assembly Drawing& of PT4206

2Wire Connecting Drawing of PT4206

Part:PP06 Chassis Features and CBU Contents

1.1PP06 Chassis Technical Specifications
1.1.1 PT4206 Panel Datas
PT4206 is the most typical model using PP06 chassis; therefore we take PT4206 as an example.

8523(RGB)480
16,777,216
1.095mm(H)1.110mm(V)
High brightness
High contrast
20000 Hours
U/D160 / L/R160
933mmH533mm(V)
Remarks: Brightness and contrast may vary because of different panels being used.
PDP Panel Resolution
Colors
Dot Pitch
Brightness
Contrast
Lifespan of Panel
Viewing Angle
Response Time

PT4206 mainly uses SAMSUNG SDI panel model S42SD-YD04 or S42SD-YD05

1.1.2 Specification Sheet

640480/60Hz
800600/60Hz

Recommended Input Format

PC

Unsupportable
Input
Indication
Color Temp. Adjust.
Quick Plug-In & Use

Format

Yes
Yes
Yes
Yes

Picture Location Adjust.

HD Signal
YPbPr

Compatible with

HD Signal
DVI

Compatible with

Video
Including
S-Video

Audio

Input Voltage
Rating
Consumption
Standby
Consumption

480P576P720P 1080i
480P576P720P
1080i and HDTV
PAL/NTSC/SECAM
D/K I B/G M
Yes
Yes

Picture System
Sound System
Digital Comb Filter
3D Comb Filter NTSC
Movement Compensation Function
Output Voltage
Audio Effect
NICAM/IGR
Video/YpbPr Audio Input
PC/DVI Audio Input
220V~, 50Hz
400W

Yes
2 5W
W OW
Yes
Audio L/R
Audio L/R

3W

1.2Main Features
1.2.1 Terminals
RF Input
1Rear
S Terminal Input
1Rear
A/V Input
RCA1Rear
YCbCr
RCA1Rear
DTV YPbPr
RCA1Rear
VGA/SVGA Input
Hi-Density D-SUB 15 pin connector1Rear
DVI Input
1 Rear
A/V Output
RCA Rear
Remarks: PT4206 is equipped with a service terminal, which service people can connect with
PC RS232 terminal to upgrade the software.
1.2.2 Working Condition Requirement:
Working Condition Requirement

Temperature

040

Humidity

2070

Altitude

02000m

1.2.3 Others
Tuning System

FS Tuning236 Programs

NICAM Demodulation
Audio Effect Process
Picture Freeze
On Screen Display
Blue Background without Signal
Power Saving

Yes
AV stereoSRS WOW5 Bands Equalizer
TV/AV/S-VIDEO/YcbCr Only
Chinese/English, Menu Location movable by user.
Yes
When TV is connected with PC input, while there is
no signal from PC, after 60 seconds, TV will be
automatically off and enter into Power Saving Mode.
Press any key on TV or R/C, or there is signal from
PC again, TV will be switched on automatically.
When this function is on, pictures will move on
regularly to protect the screen.
When this function is on, the screen will be
completely white to clear up slight shadowsplease
see the instruction manual for more details
Users can choose between 15 minutes auto-off without
signal or 3 hours auto-off without operationplease
see the instruction manual for more details

Pixel Movement
White Screen Display

Home/Commercial Mode Optional

1.3CBU Content
1.3.1 PDP Inside Drawing:

rial No.

Name

Front Cabinet

Filter Glass

Shelve Bar

PDP Panel Module

Down Cover Module etc.

Back Cabinet

Remarks: This drawing is for references only, please see the main assembly diagram
and wire-connecting diagram for details.
1.3.2 Circuit Content

The main content of PP06 circuit include: Power Regulating Circuit, RF Circuit, VGA,
Analog Video, Digital Video Signal Processing Circuit, System Control Circuit, Button Control
Circuit. Reference drawing as below:

Part:Introduction on Circuit Functions of PT4206

2.1 Changhong PDP TV PT4206 main IC functions

NO.

NAME

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

N901
N601
U705
U701
N902
U1
U6
U11
U16
U17
U22
U20
U7
U9/U13
U71
U8
U19
U4
U5
U3

Function

TYPE

Unify tuner
Sound disposal
sound amplifier
NTSC 3D comb filter
AV video switch
Digital video disposal
A/D converter
DVI signal disposal
Format transform and MCU
FLASH ROM
Difference transmit
RS-232 signal disposal
EPROMdisplay parameter information
Suffer amplifier
Sync. face lifting enlarge
EPROMDVI parameter information
EPROMuser control information
SDRAM
RGB/YpbPr switch
IP transform and picture improve

TDQ-6F7-FM2W
MSP3410G-C12-100
TA2024
uPD64083GF-3BA
TEA6425D
VPC3230D-QA-B3
MST9885
SiI161BCT100
PW113-20Q
AM29LV800BT-90
DS90C383AMTD
ST232CD
24LC21A/SN
SN74LVC126AD
74LV32D
24LC21A/SN
24LC32A/SN
IS42S16400(A)-7T
PI5V330(Q)
PW1235

2.2Changhong PDP TV PT4206 main IC functions introduction

2.2.1 A/D converter MST9885 General
The MST9885 is a fully integrated analog interface for digitizing high-resolution RGB
graphics signals from PCs and workstations. With a sampling rate capability of up to 140 MHz,
it can accurately support display resolutions up to 1280x1024 (SXGA) at 75 Hz. The clamped
input circuits provide sufficient bandwidth to accurately digitize each pixel.
The MST9885B provides a high performance highly integrated solution to support the
digitization process, including the ADCs, a voltage reference, a PLL to generate the pixel
sampling clock from HSYNC, clamping
circuits, and programmable offset and gain circuits to provide brightness and contrast controls.
When the COAST signal is asserted, the PLL will maintain its output frequency when HSYNC
pulses are absent, such as during the VSYNC period in some systems.
A 32-step programmable phase adjustment control (0-360 deg) is provided for the pixel
sampling clock to adjust for the difference between the HSYNC edge and RGB pixel edge
timing.
The MST9885B can send output data through one 24-bit port at the pixel clock rate.
The MST9885B can also support R, G, B to Y, U, V conversion.
The MST9885B has internal programmable pattern generator for testing.
The MST9885B can accept either standard TTL, CMOS levels or sawtooth vertical deflection
signals for VSYNC input.

MST9885 Pin Function Descriptions

Pin(s)
7077
29
1219
67
66
65
64
37
58
31
30
43
49
48
54
29
38
55
56
57
33
262739
424546
515259
62
112223
697879
3435
11020
212425
283236
404144
475053
606163
6880

name
RED0RED7
GREEN0GREEN7
BLUE0BLUE7
DATACK
HSOUT
SOGOUT
VSOUT
MIDSCV
REFBYP
VSYNC
HSYNC
BAIN
SOGIN
GAIN
RAIN
COAST
CLAMP
A0
SCL
SDA
FILT
AVDD

Function
Red output data
Green output data
Blue output data
Output data clock
HSYNC output
Sync-on- Green Slicer output
VSYNC output
Internal mid-scale voltage bypass
Internal reference bypass
Vertical SYNC input
Horizontal SYNC input
Blue analog input
Sync-on- Green analog input
Green analog input
Red analog input
Hold PLL frequency and do not track HSYNC
External clamp input(we connect it to ground
Serial interface address pin
I2C busclock
I2C busdata
PLL connect to external filter
Analog power

V33

Digital output power

PVDD
GND

PLL power
ground

MST9885 Block Diagram

2.2.2VPC3230 General
VPC3230 Pin Function Descriptions
Pin No.
13
46
76430
111225
356577
465168
80
8
9
102936
4552
596976
13
14
15
16
17
18
1923
24
27
28
3134

Pin Name
R1G1B1IN
R2G2B2IN
GND

Short Description
RGB Analog Component Input 1
RGB Analog Component Input 2
GND

NC
VSUPCAP
V33

NC
Supply Voltage, Digital Decoupling Circuitry
Supply Voltage, Digital Circuitry

AVCC
SCL
SDA
RESQ
TEST
VGAV
YCOEQ
FFIE
CLK20
LLC2
LLC1
Y0Y7

Analog Voltage
I2C Bus Clock
I2C Bus Data
Reset Input
Test Pin
VGAV Input
Y/C Output Enable Input
NC
Main Clock Output
Clock Output
NC
YUV signal output (Digital ITU-R656 format)
10

3740
4144
4750
53
54
55
56
57
58
60
61
62
63
66
67
70
71
72
73
74
78
79

C0C7

Digital chromatic signal output

INTLC
AVO
FSY/HC
MSY/HS
VS
FPDAT
CLK5
NC
XTAL1
XTAL2
VRT
I2CSEL
VOUT
CIN
VIN1
VIN2
VIN3
VREF
FB1IN

Interlace scan control output (0-odd,1-even)

Active Video Output
NC
Horizontal Sync Pulse output
Vertical Sync Pulse
NC
5 MHz Clock Output
NC
20.25M Analog Crystal Input
20.25M Analog Crystal Output
Reference Voltage Top, Analog
I2C Bus Address Select
Analog Video Output
Chroma / Analog Video 5 Input
Video 1 Analog Input
Video 2 Analog Input
Video 3 Analog Input
Reference Voltage Top
Fast Blank Input

VPC3230 Block Diagram

11

2.2.3PW113 General
The PW113 integrates an industry-leading scaler, an advanced OSD engine, a flexible input
port system, system memory, and a powerful 80186-based horizontal and vertical image scaler
swith intelligent Auto Image Optimization circuitryThe Image Processor supports NTSC or PAL
video data with a 4:3 aspect ratio and 16:9 aspect ratio sources, such as DVD or HDTV. Video
Input formats can be in either YUV4:4:4 (24 bit) or YUV4:2:2 (16 bit) input modesThe PW113
uses an integrated PLL to synchronize the display interface timing to the input timingAn
integrated OSD controller supports sophisticated bit-mapped based OSDs The OSD controller
supports transparent, translucent, and fade-in/ fade-out functions.

Pin Function Descriptions

Pin(s)

name

Video Port Pin Descriptions

71
VCLK
74
VVS
75
VHS
69
VFIELD
70
VPEN
4756
YUV0YUV7

Graphics Port Pin Descriptions

31
GCLK
32
GVS
33
GHSSOG
34
GPEN
35
GFBK
2027
GRE0GRE7
10151819 GGE0GGE7
29
GBE0GBE7

Function
VPort Pixel Clock input
VPort Vertical Sync input
VPort Horizontal Sync input
VGPort Field Input
VPort Pixel Enable
VGPort ITUR656 Pixel Data.I/O port
We use 47 MUTE mute control 48 PW1230E
PW1235output enable49 VGASEL VGA/YpbPr select
50 S1 sound system control51 DVIPD DVI interface
standby54 STANDBY power standby control56 RST1
peripheral IC reset
GPort Pixel Clock input
GPort Vertical Sync input
GPort Horizontal Sync/GPort Sync- on-Green input
GPort Pixel Enable input
GPort PLL Feedback / Line Advance Input
GPort Red Pixel Data input
GPort Green Pixel Data input
GPort Blue Pixel Data input

Display/Graphics Port Pin Descriptions

129136
DGPort Red Pixel Data(odd outputs)
DGR0DGR7
119122
DGPort Green Pixel Data(odd outputs)
DGG0DGG7
125128

111118
DGB0DGB7
Display Port Pin Descriptions
106
DCLK
108
DVS
109
DHS
110
DEN
96103
DR0DR7
8895
DR0DR7
7683
DB0DB7

DGPort Blue Pixel Data(odd outputs)

DPort Pixel Clock output
DPort Vertical Sync output
DPort Horizontal Sync output
DPort Pixel Enable output
DPort Red Pixel Data(even outputs)
DPort Green Pixel Data(even outputs)
DPort Blue Pixel Data(even outputs)
12

Microprocessor Interface Pin Descriptions

194
WR
Write Enable low indicates a write to external RAM or other
devices
195
RD
Read Enable low indicates a read to external RAM or other
devices
196
ROMOE
ROM Output Enable low output indi cates a read from
external ROM.
197
ROMWE
ROM Write Enable low indicates a write to external ROM.
198
CS0
Chip select signal
199
CS1
Chip select signal
193
NMI
Non-maskable Interrupt
Microprocessor address bus output bits
164173 A1A19
184187
192
Microprocessor 16-bit bidirectional data bus
148163
D0D15
Peripheral Interface Pin Descriptions
207
PORTA0
DISPEN signal output(PDP display control)
206
PORTA1
READY signal inputPDP display ready
205
PORTA2
SDA
204
PORTA3
SCL
203
PORTA4
IR receive signal input
201
PORTA6
DVI digital interface select control
203
PORTA4
IR receive signal input
575860 PORTB0
Key control input
PORTB7
64
39
PORTC0
MA-EN enable control
40
PORTC1
480ISEL 480I anti-copy control
41
PORTC2
RST-1235 PW1235 reset
42
PORTC3
DIGSEL DVI digital interface select
43
PORTC4
LVDSON LVDS enable control
44
PORTC5
S0 sound system control
4546
PORTC6
LED control
PORTC7
67
RXD
Serial Receive Data
68
TXD
Serial Transmit Data
Miscellaneous Pin Descriptions
142
TEST
Test mode enable
139
RESET
Bidirectional reset pin
169
XI
Crystal input
170
XO
Crystal output
Power and Ground Pin Descriptions
VDD1
1.8V digital core power.
16376584137185
VSS
Digital core ground
17386685138186
3.3V digital I/O power.
29527286104123 VDDQ3
140171208
Digital I/O ground.
130537387105124 VSSQ
141172
165
VDDPA2 1.8V analog clock generator power.
166
VSSPA2
Clock generator analog ground.
167
VDDPA1 1.8V analog clock generator power.
168
VSSPA1
Clock generator analog ground.

13

PW113

Block Diagram

14

2.2.4PW1235 General
PW1235 supports standard digital video signal incorporates deinterlacing
scaling .the PW1235 is able to effectively deinterlace video input by creating motion vectors that
follow frame-to-frame movement, and provide clear, progressive output in both analog and digital
formats. The PW1235 integrates input interfaceMEMORY control circuitpicture improve
output interface circuitI2C bus interface and so onall the function are controlled by I2C bus
Pin Function Descriptions
Pin(s)
Name
Video Port Pin Descriptions
27
PVVS
28
PVHS
25
PVCLK
26
CREF
12
SVVS
11
SVHS
13
SVCLK
30333538 VR0VR7
15182023 VG0VG7
1469
VB0VB7
Digital/Graphics (DG) Port Pins
68
DGCLK
67
DGVS

Function
Primary Video (PV) Port vertical sync input.
Port horizontal sync input
Port pixel clock input
Video input clock reference
Port (ITU-R BT656 format) vertical sync input
Port (ITU-R BT656 format) horizontal sync input
Port (ITU-R BT656 format) pixel clock input
Video port red data input
Video port green data input
Video port blue data input
Digital/Graphics (DG) port pixel clock

Digital/Graphics (DG) port vertical sync.

66
DGHS
Digital/Graphics (DG) port horizontal sync
Digital/Graphics
(DG) port red data
91929495 DGR0DGR7
97100
81848689 DGG0DGG7 Digital/Graphics (DG) port green data.
7073,7576 DGB0DGB7 Digital/Graphics (DG) port blue data
7879
Analog Display Port Pin Descriptions
156
ADR
Analog display port red (V/Pr) data
153
ADG
Analog display port green (Y/Y) data
150
ADB
Analog display port blue (U/Pb) data
161
VREFIN
Reference voltage input.
162
VREFOUT
Reference voltage output.
159
RSET
Full-Scale adjust resistor
160
COMP
Compensation pin
Digital Display Output Port Pin Descriptions
102
DCLK
Digital display output port pixel clock
103
DVS
Digital display output port vertical sync
104
DHS
Digital display output port horizontal sync.
108
DENR
Display pixel enable red/Vertical blanking period
(VBLANK)
106
DENG
Display pixel enable green
107
DENB
Display pixel enable blue/Horizontal blanking period
(HBLANK)
145
DEN
Digital display output port output enable
Digital display output port red data
132 133 DR0DR7
135 136
138 139
15

141142
121 122 DG0DG7
124 125
127130
110 111 DB0DB7
113 114
116119
Memory Pin Descriptions
229
MCLK
223
MCLKFB
225
MRAS
226
MCAS
227
MWE
213210207204 MA0

203206209211 MA13
214217215220
221218
255252248245 MD0

MD15
242239236232
231234238241
244247250254
Host Interface Pin Descriptions
47
2WDAT
45
2WCLK
43
2WA1
44
2WA2
178179181186 MCUD0
MCUD7
168170172 PORTB1
174176177
190
MCUCS
191
MCUWR
192
MCUCMD
188
MCURDY
Miscellaneous Pin Descriptions
56
TEST
144
TESTCLK
55
RESETn
40
XTALI
41
XTALO
146
CGMS
201
MVE
62, 63, 194,195
NC
System Power Pin Descriptions
5, 34, 93, 123,140, VDD
175,205, 235
19, 49, 77, 112,
VSS
134, 187, 219, 251

Digital display output port green data.

Digital display output port blue data.

SDRAM clock
SDRAM clock feedback
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
SDRAM address bus

SDRAM data bus

SDA
SCL
Programmable two-wire serial bus address bit 1
Programmable two-wire serial bus address bit 2
MCU data bus
MCU address bus
Chip select
MCUR/W signal
MCU command signal
MCU Ready signal
Test mode
Used for testing, can be used to supply display clock
Hardware asynchronous reset.
Crystal oscillator input
Crystal oscillator output
CGMS Enable
Macrovision write protected enable

Digital core power (2.5V).

Digital core ground.

16

14, 29, 42, 54, 64,

69, 80, 90, 101,
109, 120, 131, 143,
165, 180, 200, 208,
216, 224, 230, 237,
243, 249, 256

PVDD

Digital I/O power (3.3V).

10, 24, 39, 46, 57,

65, 74, 85, 96, 105,
115, 126, 137, 147,
171, 189, 193, 202,
212, 222, 228, 233,
240, 246, 253
60
61
58
59
197
196
199
198
157
154
151
158
155
152
163
164
149
148
166
167

PVSS

Ground.

MPAVDD
MPAVSS
MPDVDD
MPDVSS
DPAVDD
DPAVSS
DPDVDD
DPDVSS
AVD33R
AVD33G
AVD33B
AVS33R
AVS33G
AVS33B
ADAVDD
ADAVSS
ADDVDD
ADDVSS
ADGVDD
ADGVSS

Memory PLL analog power 2.5V.

Memory PLL analog ground.
Memory PLL guard ring / digital power 2.5V.
Memory PLL guard ring / digital ground.
Display PLL analog power 2.5V.
Display PLL analog ground.
Display PLL digital power 2.5V.
Display PLL digital ground.
Analog power (+3.3V) for R (V/Pr) channel.
Analog power (+3.3V) for G (Y/Y) channel.
Analog power (+3.3V) for B (U/Pb) channel.
Analog ground for R (V/Pr) channel.
Analog ground for G (Y/Y) channel.
Analog ground for B (U/Pb) channel.
Analog power supply (+2.5V) for the analog display port.
Analog ground for the analog display port.
Digital power supply (+2.5V) for the analog display port.
Digital ground for the analog display port.
Guard ring power for the analog display port.
Guard ring ground for the analog display port.

17

18

PW1235 Block Diagram

2.2.5TA2024 general:
19

The TA2024 is a 10W/ch continuous average two-channel Class-T Digital Audio Power
Amplifier IC using Tripaths proprietary Digital Power Processing technology. Class-T
amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D
amplifiers.
Pin Function Descriptions
Pin(s)
2, 3
4, 9
5, 8, 17
6
7

Name
DCAP2, DCAP1
V5D, V5A
AGND1, AGND2, AGND3
REF
OVERLOADB

1014
11, 15
12
16
18
19

OAOUT1, OAOUT2
INV1, INV2
MUTE
BIASCAP
SLEEP
FAULT

20, 35
22
24, 27; 31, 28
25, 26, 29, 30
13, 21, 23, 32, 34
33
36
1

PGND2, PGND1
DGND
OUTP2 & OUTM2; OUTP1
& OUTM1
VDD2, VDD2 VDD1,
VDD1
NC
VDDA
CPUMP
5VGEN

20

Function
Charge pump switching pins
Digital 5VDC, Analog 5VDC
Analog Ground
Internal reference voltage
A logic low output indicates the input signal
has overloaded the amplifier
Input stage output pins.
Single-ended inputs
Mute control
Input stage bias voltage
Sleep mode control
A logic high output indicates thermal
overload
Power Grounds (high current)
Digital Ground
Bridged outputs
Supply pins for high current H-bridges,
nominally 12VDC.
Not connected
Analog 12VDC
Charge pump output
Regulated 5VDC source used to supply
power to the input section (pins 4 and 9).

TA2024 Block Diagram

2.2.6DS90CF383A General
The DS90C383A/DS90CF383A transmitter converts 28 bits of CMOS/TTL data into four
LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is
transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit
clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65
MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME,
DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock,
the data throughput is 227 Mbytes/
sec. The DS90C383A transmitter can be programmed for Rising edge strobe or Falling edge
strobe through a dedicated pin. The DS90CF383A is fixed as a Falling edge strobe transmitter.

21

Pin Function Descriptions

Pin(s)
1,9,17,26,34
44
5,13,21,29,53
33,35,36,43,49
2,3,50,51,52
54,55,56
4,6,7,11,12,14
8,10
15,19,20,22
23,24,8,16
27
28
30
31
32
37,38,41,42
45,46,47,48
39,40

Name

Function

VCC

Power supply

GND

Ground

DRE0DRE7

8bit red data input

DGE0DGE7

8bit green data input

DBE0DBE7

8bit blue data input

HSYNC
VSYNC
DE
TXCLK IN

Horizontal Sync input

Vertical Sync input
pixel display enable
pixel display clock input
LVDS control

PWRDWN
TXOUT+
TXOUTTXCLKOUT+
TXCLKOUT-

4 channels LVDS data signal output

1 channel LVDS clock signal output

22

DS90CF383 Block Diagram

23

2.2.7DVI Digital Receiver SiI161B

General
The Sil161B receiver uses Panel Link Digital technology to support high-resolution
displays up to UXGA. The Sil161B receiver supports up to true color panels (24 bit/pixel,
16.7M colors) in 1 or 2 pixels/clock mode. In addition, the receiver data output is time
staggered to reduce ground bounce that affects EMI. All Panel Link products are
designed on a scaleable CMOS architecture. This ensures support for future
performance requirements while maintaining the same logical interface. With this
scalable architecture, system designers can be assured that the interface will be fixed
through a number of technology and performance generations.

Pin Function Descriptions

Pin(s)
90
91
85
86
80
81
93
94

Name
RX0+
RX0RX1+
RX1RX2+
RX2RXC+
RXC-

4956

QO0QO7

Function
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input clock pair.
TMDS Low Voltage Differential Signal input clock pair.
8bit odd-pixel Blue output

5966

QO8QO15

8bit even-pixel Green output

6975,77

QO16QO23

8bit odd-pixel Red output

1017

QE0QE7

8bit even -pixel Blue output

2027

QE8QE15

8bit even -pixel Green output

3037
99
100

QE16QE23
RESERVED
OCK_INV

8bit even -pixel Red output

Must be tied HIGH for normal operation.
ODCK Polarity. A LOW level selects normal ODCK
output. A HIGH level selects inverted ODCK output.
This pin enables/disable the HSYNC dejitter function.
To enable the HSYNC function this pin should be tied
high. To
Power Down (active LOW). A HIGH level indicates
normal operation. A LOW level indicates power down
mode.
Output Drive. A HIGH level selects HIGH output drive
strength. A LOW level selects LOW output drive
strength.
Pixel Select. A LOW level indicates one pixel (up to
24-bits) per clock mode using QE[23:0]. A HIGH level
indicates two pixels (up to 48-bits) per clock mode
using QE [23:0] for first pixel and QO[23:0] for second
pixel.
Staggered Output. A HIGH level selects normal
simultaneous outputs on all odd and even data lines.

HS_DJTR

PD

ST

PIXS

STAG_OUT

24

SCDT

PDO

44

ODCK

46
47
48
18,29,43,57,78
19,28,45,58,76
6,38,67
5,39,68
82,84,88,95
99,83,87,89,92
97
98
96

DE
VSYNC
HSYNC
OVCC
OGND
CVCC
GND
DAVCC
AGND
PVCC
PGND
EXT-RES

A LOW level selects staggered output drive.

Sync Detect. A HIGH level is outputted when DE is
actively toggling indicating that the link is alive. A
LOW level is outputted when DE is inactive, indicating
the link is down.
Output Driver Power Down (active LOW). A HIGH
level indicates normal operation. A LOW level puts all
the output drivers only (except SCDT and CTL1) into
a high impedance (tri-state) mode.
Output Data Clock. This output can be inverted using
the OCK_INV pin.
Output Data Enable.
Vertical Sync input control signal.
Horizontal Sync input control signal.
Output VCC
Output GND
Digital Core VCC,
Digital Core GND.
Analog VCC
Analog VCC
PLL Analog VCC
PLL Analog GND.
Impedance Matching Control. In the common case of
50 transmission line, an external 390 resistor must
be connected between AVCC and this pin.

SiI161B Block Diagram

25

26

CHAPTER 3 CHANGHONG PDP TELEVISON PT4206

entire signal flow analyse
3.1Each part signal Disposal Flow general
3.1.1Analog signal Disposal Flow
3.1.1 .1RF Disposal
TDQ-6F7-FMW2 disposal the RF signal
Pin Function Descriptions
Pin(s)
Name
Function
1
VT
Analog tune voltagenot use
2
BTL
+32Vpower
3
BM
+5V power
4
ADD
Ground
5
S0
Color system Switch control
6
S1
Color system Switch control
7
SCL
I2C busclock
8
SDA
I2C busdata
9
SIF
Second sound IF signal output
10
VIDEO OUT
video signal output
11
VIF
Power supply
12
AUDIO OUT
Sound LF signal output(not use)
First the antenna signal enters the Unify RF TUNER N901, enlarge the RF signal , choose the
back track of frequent and mix frequent circuit ,and outputs the IF signal. The video signal from
the 9 pin through the video check wave, differs to clap at the same time the Second sound IF
signal output.
The frequency synthesizing and tuning needs two power supplies when work normally:+ 32
V tune voltage and + 5 V PLL power supply.
Moreover 5 and 6 pin of N901 switch the Color system , sending out from 44 and 50 pin of
PW113.10 pin of N901 outputs video signal ,follows to Q905 ,through the video switch circuit
switching with the AV/ S- VIDEO
Input signal ,after them disposal in VPC3230.

3.1.1 .2

SOUND Disposal

the 9 pin of N901 outputs the second sound IF signal, enlarged by the Q910,following to
Q602 and passing C611 to the 67 pin of MSP3410G to carry on SIF demodulation and the
NICAM identify the decodingThe sound of PC, DVI, AV, YCbCr, and YPbPr are transited to
MSP3440, and then input to the speakers after transits to TA2024 and to the speakers.

.
3.1.1.3

digital signal disposal

In response to input signal of PW113 ,it must convert the input analog video signal, VGA
analog signal and DVI signal into digital or video decode outputinclude three partsone, VGA or
27

YpbPr (analog signal)is converted the signal into A/D by MST9885it is 24bit digital tricolor
signalsecond various video signalsinclude TV signal are disposalled by VPC3230 then
output the signal format ITU-R656 YUV signalThe third part decode DVI1.0 standard digital
signal then output 24bitRGB signal

3.1.1 .4

VGA/YpbPr analog signal disposal

R, G, B signal From the VGA 1, 2, 3 pin through the static electricity protection
circuit switches with video signal from YpbPr input port in PI5V330. After then RGB
signal(PC source) pass C81C82C84 to 544843 pin of MST9885 and A/D converter in it

Moreover , Vertical , Horizontal sync from the VGA 13,14 pin also send to the
synchronous pulse orthopedics circuit after static electricity protect processing.
Horizontal sync after face lifting in 74LCX32 sends to the PI5V330 to the switch , and
then feedback to the 30 pins of MST9885, By the effect of Horizontal sync ,
MST9885 creates PLL lock providing the MST9885 work clock. Vertical sync after
buffer and enlarge in U71 outputs from the 6 pin of U71, and choices in U9(74
LVC126s).In VGA mode ,the signal to the 31 pin of MST9885, provides a Vertical
sync to the MST9885.
The PDP display is the exterior equipments, and need an identify signal to
examined by host when host communication. The 24LC21s of U8( EEPROM) saves
the hardware concerning display parameter.( install etc. such as the factory, model
number, resolution)
MST9885 under the control of PW113 bus, converts the R,G,B input 8 bit digital R,G,B
signal. 67 pin outputs pixel clock signal DATACKThe above signal sends to the PW113

and PW1235s at the same time, disposals the format judged by PW113.
3.1.1.4

Analog video signal disposal

9 pin of N901 outputs video signal passes VN901 and goes to 1 pin of TEA6425Dat the
same time 1 channel AV video signal sends to the 8 pin of TEA6425Dand other channel S-video
signal (YC signal) sends to 65 pin of TEA6425D respectively. The three signals switches in
the TEA6425D. VIDEO or Y signal outputs toVPC3230D from 17pinC signal outputs from
18pinat the same time 19 pin video outputs from19 pinVPC3230 The signal from TEA6425
after switch and A/Dsend to chroma decode circuit ,which can identify PAL/NTSC/SECAM
signal automatically and to each decode after identify. Such as NTSC video after identify the
system switches the TEA6425D channel sends to NTSC 3D comb filter from 14 pin of
TEA6425D. After digital 3D comb filter in uPD64083 YC signal sends back to 7371pin of
VPC3230Dto AD convertor and saturation control etc. The output digital YUV signalswitches
with digital YUV signal after A/D which inputs from 456pinand outputs digital YUV
signal sends to video disposalinclude zoomcontrast panorama modebrightnessgain control

28

tc. After then the signal transforms to from 3140pin digital YUV signal4:2:2(ITU-R656
format )and sends to PW1235 to DEINTERLACE etc

3.1.1 .5 DVI digital signal disposal

We use DVI-D interface
DVI digital signal4channels DS signalfrom DVI jack each send to 90918586
80819394pin of SiI161B. By the control of 1003pin (input bus)after in SiI161B(VCR
data resumesync. Head test enlarge circuitdecode circuit and logic interface circuit)it
outputs digital R G B signalwhich has two modeone mode when 4 pin of SiI161B is low
it output 24bit even pixelwhen 4pin is high it output 48biteven and odd pixel datawe connect
4pin to groundso each signal from 101720273037pin outputs R,G,B even pixel data
switch with 24bit VGA digital signal disposalled by MST9885and send to PW113 to transform
formatfor sure ,the choice is control by PW113
DVI interface 67pin is DDC data channel U724LC21Ais an E2ROMwhich stores
some DVI data parameter information it connect to DDC data channel by busat the moment of
power on the status information is sent to host to identifyafter identifyaccording to E2ROM
information outputs digital signal correctly
VGA signalvideo signalDVI signal after digital disposalsends to video format disposal
ic PW113 to change

the video format outputs the digital R,G,B signal which fits PDP

display driver
PW113 the input video signal after disposalled by PW113outputs 852480 resolution digital
R,G,B signal which fits PDP panel spec and relevant syncclock signal and transform them into
LVDS by DS90CF383send to PDP panel to control the panel display correctly

29

3.2 each information flow

3.2.1 TV

S0

S1

Tuner demodulation
RF

MSP3410G
FmorNICAM demodulation
SIF

67
SRS(WOW)
27

CVBS

sound disposal
28

1
TEA6425 video switch
NTSC video

16

TA2024 sound

amplifier

MUTE

17
When NTSC,
Change the video switch by bus

Sync
88

separate

74

uPD64083 comb filter

83

VPC3230
Identify color system

84

Not NTSC
Y

73
VPC3230 decode

71

Main control signal

1RST1#
High enable
2STANBY control
Low is power ON
3 MUTE high mute
4sound switch
S0S1

Digital video and clock

SV

SO

S1

D/K

1 0

BG
I

1 1
0 1

0 0

PW1235 I channel

SDRAM

BUFF
ER
PW1235E

PW113
SCALER
D

LVDSON

DS90C383

LVDS output

30

5PW1235Econtrol
High enable
BUFFER and polarity
controlled by Q3
6LVDSON control

3.2.2 AV
L

53

54 SRS(WOW) sound disposal

cvbs

MSP3410G
Sound switch

27

28

8
TEA6425
NTSC

16

video switch

17

Sync separate

88
uPD64083

NTSC

switch by bus

74
VPC3230
Identify color system

comb filter

83

MUTE

84

Not NTSC
Y

73
VPC3230

decode

71
Digital video and clock
SV

PW1235

SDRAM

I channel

BUFF
ER
PW1235E

PW113
SCALER
D

LVDSON

DS90C383

LVDS output

31

TA2024 sound amplifier

3.2.3 S-VIDEO

TEA6425 video

53

54

switch
17

18

74

72

MSP3410G
Sound switch

SRS(WOW)

sound disposal
27

28

VPC3230 decode
MUTE
Digital video and clock
SV
PW1235 I
channel

SDRAM

PW1235E

BUFF
ER

PW113
SCALER
D

LVDSON

DS90C383

LVDS output

32

TA2024 sound amplifier

3.2.4 YcbCr
L

MSP3410G
53 Sound switch SRS(WOW) sound disposal

54
27

CVBS

28

8
NTSC video

TA2024 sound amplifier

TEA6425 video
16

MUTE

switch
17

When NTSC,switch video

Sync.
separate

88
uPD64083 comb

VPC3230

fliter

83

signal

74

84

Not NTSC
Y

73

VPC3230 decode

71
Digital video and clock
SV

DS90C383
LVDSON

PW1235

SDRAM

channel
LVDS output

BUFF
ER

PW1235E
PW113
SCALER

disposal

LVDSON

DS90C383

LVDS output

33

3.2.5 YpbPr

VGASEL

Pb Pr

11

47

48

MSP3410G
Sound switch

PI330 switch
4

54 48

43

27

AD9883

MUTE

BUFF
ER
PW1235E
G
PW113
Format identify

PW113 SCALER

LVDSON

DS90C383

LVDS output

34

SRS(WOW) sound disposal

28

TA2024 sound amplifier

3.2.6 VGA

HS R

13 3

6 10

L
50

51

MSP3410G
VGASEL

PI330 switch

Sound switch
SRS(WOW) sound disposal

12 4

HS R

27

28

30 54 48 43
TA2024 sound amplifier
VS

U9

31

G
PW1235 P
SDRAM

MST9885

MUTE

BUFF
ER

channel

PW1235E

Not standard modeadjust

Main AD9883
controlswitch
signalthe channel
1RST1#
High enable
PW113
2STANBY control
Foemat identify
Low is power ON
Signal after vertical sync
3 MUTE
High mute

4VGASEL control
640X480800X600@60Hz signal
High enable
5PW1235E control
High enable
BUFF
G PW113 SCALER
BUFFER and polarity are controlled by Q3
ER
G

D
6LVDSON control
PW1235E
LVDSON

DS90C383

LVDS output

35

3.2.7 DVI

Digital RGB or YPbPr

50

51
MSP3410G

SiL161

Sound switch
SRS(WOW) sound disposal
27

28

G
BUFF
ER

PW1235 P channel
SDRAM

PW1235E

MUTE
Not standard mode
Switch the channel

PW113
Format identify
Signal after vertical sync change
vertical sync 60HZ signal

BUFF
ER

PW113 SCALER

D
PW1235E
LVDSON

DS90C383
LVDS output

36

TA2024

sound amplifier

3.3system control process

After connect the AC power input (we use 3 pins power jackthe GND pin must ground
well).first of all ,standby power workssignal mainboard takes 5V-ST power supply the
powers of PW113 begin to workLED turns red. Resetting after V18V33 power is normal
PW113 initializes the systemsends STANDBYLsignalwhich controls main power begins to
workother power VT9VT5AVCCPVDDAVDDOVCCCVCCPVCCDAVCC
AVDDAVCCDVDAPVDD also work normally.MST9885VPC3230SiI161BDS90CF383
take proper power supply. Moreover LED signal control LED to turn yellow and glitterit is said
that it controls normally At last LVDSON signal from 43pin of PW113is highit let
DS90CF383 begin to workAfter this it is in normal work stateinput source is last time
source before power off
3.3.1when choice VGA mode by remote device PW113 controls MST9885 by I2C
busenable SiI161B and VPC3230let them work in low consume modewhich can save power
and reduce interfereAt the moment VGASEL signal from PW113 output parks VGA input
channel in PI5V330. If VGA signal inputs, MST9885 outputs Horizontal and Vertical Sync
signal and data signaland send to PW113which outputs format commutation data . After
DS90CF383(DS transmitter)it transforms to the signal fitting the PDP panel demand because
SiI161BDS90CF383 both in normal work statewhen DVI signal inputs, display videoif no
VGA signalMST9885 can not output digital Horizontal and Vertical Sync signal after examined
by PW113,displays pc icon on the left and top of PDP panel other part display black. If no
input after 60 sec, it hints to enter save power mode At the moment , MST9885 in normal
work stateexamines VGA signal ceaselesslyso it can arouse automatically in VGA mode. It is
said that when VGA signal inputs, it can work normally from standby state
3.3.2when in TVAVYCbCr mode by remote devicePW113 controls VPC3230 by
2
I Cbusotherwise PW113 controls MST9885 on the fly output in high impedance stateby
I2Cbus.Because tuner N901VPC3230 DS90CF383 all in normal work statewhen video
signal inputsPDP panel display normallyif no video signal inputunder the control of PW113
PDP panel displays blue backgroundif no signal 15 minspower off automatically and into
standby state. It can not arouse automatically
3.3.3When in DVI(digital RGB) mode by remote devicePW113 controls SiI161Band
enables VPC3230and let it working in low consume modeotherwise PW113 controls MST9885
on the flyoutput in high impedance stateby I2C busbecause SiI161BDS90CF383 both in
normal work statewhen DVI signal inputs, display videoif no DVI signalSiI161B do not
output digital Horizontal and Vertical Sync signal after examined by PW113,displays DVI icon
on the left and top of PDP panel other part display black. If no input after 60 sec, it hints to
enter save power modework stateAt the moment ,SiI161B in normal work state examines
DVI signal ceaselesslyso it can arouse automatically in DVI mode. It is said that when DVI
signal inputs, it can work normally from standby state

37

3.4power supply system

3.4.1main power supply
D6Vsteady voltage to 5V supply for VPV3230AD9883 analog power5V-STstandby
powerto PW113AM29LV800BTROM24LC32MAX202EVDD(3.3V)VPC3230
MST9885DS90CF383 power+32VRF tuner tuning powerA6Vsteady voltage to Av
board 5V etc. A12Vsteady voltage to AV board 8V etc.12VAMPsound amplifier
TA2024 power

3.4.2 main power form and power branch

3.4.2.15V-STpower branch
U16 PW113
29527286104123140
171208pin

N803
LM1117-3.3

VUU

U19

U17

XP801
2 pin

5V-ST

N804
LM1117-1.8

24LC32
8pin

29LV800B
37pin

U16
PW113
16376584137185pin

VLL

VPP

U16 PW113
165167pin

NK605
remote head
XP101
11 pin

K board
connect

XPK3
11pin
VDK1
LED

U20
MAX202E

38

3.4.2.2D6V power branch

U1
VPC3230

U5
PI5V330 16 pin

XP801
11 pin

D6V

N802
TA4805F

U27
LM1117-3.3

VCC

U26
LM1117-3.3

U6 AD9883A
262739424546
51525962 pin

VFF

VEE

U6 AD9883A
3435 pin

U3 PW1235
53493123140
175205235 pin

U28
LM1086CSX-2.5

VXX
VYY

39

U3 PW1235
197199 pin

VZZ

U3 PW1235
5860 pin

2.5

U3 PW1235
149163166
pin

3.4.2.3VDD(3.3V) power branch

U10/U12/U14/U15 74LVC16244
7183142 pin

U11 SiL161B
618293843576778
8284889597pin

to reduce interference
U11 power is divided into
VDDVIIVJJ by LC
filter
97 pin is VII power82
848895 pin are VJJ
power

U4 IS42S16400(A)-7T
13914274349pin

U3 PW1235
1429425464698090101109120131143165
180200208216224230237243249256pin

U3 PW1235
515457pin

XP801
8
9pin

U22 DC90C383
1926pin

VDD

VNN

U22 DC90CF383
34pin

VOO

U22 DC90CF383
44pin

U6 AD9883
11222369
7879pin

U71

74LV32
14pin

U1 VPC3230
10293645
52pin

40

VNNVOO is in order to
reduce the interference
from VDD after LC filter

3.4.2.4A6Vpower branch
XP805
1pin

A6V

N806
TA4805F

N601 MSP3410G
6566pin

VCC

N601 MSP3410G
111213pin

N805
TA4805F

N901 TDQ-6F7
311pin

5VTUNER

TV videoSIF
follow amplifer
circuit

N650
TA4805F

N702
LM1117-2.5

5V2

A2.5V

U701 uPD64083
538192
93pin

D2.5V
N701 uPD64083
3132454664
100pin

N703
LM1117-3.3

D3.3V

N701

uPD64083
38pin

N701 small
signal filter
amplifer circuit

5V-3D

N701 input video

and output YC
filter amplifer
circuit

41

3.4.2.5A12Vpower branch

XP805
3pin

N651
TA78M08

+8V

PC/YPbPr sound
amplifer

N902

TEA6425D
20pin

N601

MSP3410G
39pin

AVOUT sound
amplifer

42

Part:Typical Defectives and Repair of PT4206

onered

led do not light

red

Check K board
iack XK01 11 pin
5V power

yes

led do not light

Check jack XP901 2 pin

5V power supply

no

Check mainboard jack XP801

2 pin 5V power

Check
resistance RK2
LBD VDK1

Check circuit
connect

1Check XP801 2 pin short circuit

to ground whether or not
2Check mainboard L801
3Check PW113 reset circuitclock
circuit

yes

43

no

Check power filter

and power jack
AC 220V input

twoThe red led lightsbut doesnt turn to yellow after power on and black display

power oncheck
XP801 4 pin standby
is low0.5Vvoltage

check N803N804
output voltage

No

1check PW113
power impedance
2checkN803
N804

Yes
yes
check X3 14.318M
crystal
1check
connector
2check PDP
power

no

checkXP801 D6VVDD

yes

abnormality

I2Cbus

check PW113
RESET pin
voltage

check AM29LV800BT to
PW113 addressdata
control

normal
1check VPC3230PW1235
power circuit
2check VPC3230PW1235
reset voltage
3check VPC3230PW1235
peripherally circuit

change Y2
crystal

No

check
resetcircuit

Yes

Yes
check bus
circuit and PCB
wire

No

change
AM29LV800BT or
PW113 and wire
between them

44

threeThe red led lightbut turn to other color after power on and black display
change switch
find if there is
icon on the
screen

Yes

follow no
picture to check

Yes

mend

No

check mainboard
J15check the
line

No

check LVDS
signal

No

1LVDS ON is
hign or not
2check PW113
syncpixel
clockRGB data
sinal

Yes

Yes

check PW113
syncpixel
clockRGB data
sinal

checkDS90c383
power supply

Yes

Yes

check crystal
frequentcheck
PW113change

No

check PW113
output port
change PW113

No

check power
supply

check DS90C383
change

45

fourno picture
check if there
is a icon to
display when
source switches

No

CHECK PW113 G-Port

31-35 pin
changePW113

other part is
following
no picture only
DVI

no picture only
VGA

check AD9883A
3031 pin sync

Yes

No

check sync face

lifting circuit
and I/O sync
wave

output abnormality

check SiI161B/169 4448

4742pin GCLKGHS
GVSGFBK

all abnormality

input abnormality

check VGA jack

part abnormality

check sync face

lifting circuit
and peripherally
circuit

checkSiI161B/169
control signal

abnormality

change AD9883A

46

1check signal source

2DVI jack
3change Sii161B

if there is one
state to display
when switch the
source

TVAVS-VDEO
YCbCr all no
picture

check PW1235
power clock

check VPC3230
output

repair abnormality

Yes

check and change

PW1235

only TVAV
S-VIDE Ono
picture

only TVAV is
NTSC no picture

check AV board
connector

check TEA6425D14
pin video outout

joint well

Yes

check TEA6425D
I/O

check uPD64083
I/O filter and
amplifer circuit

check TDQ-6F7
powerbus and
video followwing
outout circuit

check uPD64083
resetclock
power
changeuPD64083

check and change

TDQ-6F7

No

input well,but output bad

check VPC3230
power clock
periphery
circuitchange
VPC3230

check TEA6425
powerbus
change TEA6425

47

only TV no
picture

No

checka
nd
change
TEA642
5D

Yes

check TEA6425D1
pin video signal
input

Five picture dissimilation

picture
dissimilation

colour
dissimilation

all panel green

check liner
voltage circuit

source switch if
one mode is well
or not

checkDS90C383A
(37)-(42)(45)-(4
8)

only VGA colour

dissimilation

only DVI colour

dissimilation

all colour
dissimilation

check AD9883A
and 74LV16244
RGB digital
signal

check Sil161B
and 74LV16244
RGB digital
signal

check mainboard
panel jack

normal

normal

change U8
24LC21A
check56
pin

changeu7
24LC21Acheck
56

mosaic phenomena

check PW113
power

No

change PW113

No
change memorizer
U19 24LC32A
check PW113 and
U19

normal

normal DS90C383A

normal
check PW113
output video
siganl

48

change
DS90C383A
repair output
connector

follow
next
picture

picture
dissimilation

lack colourno
Rno G,no B

plane crossband
interference

lack front
one analog
signal

VGA state

AV/TV state

check C81C82
C84

check PW1235
output data

checkPI5V330

check VPC3230
output

check L901
L902L905
R904R909R910

check VPC3230
input signal

change AD9883A

check and change

VPC3230

No

only VGADVI
not commendatory
state

VGA mode
commendatory
state

DVI mode
commendatory
state

check and change

PW1235

change U8
check5(6)
pin

change U7
check5(6)
pin

checkAD9883A and
peripherally
device

check SiI161B
and peripherally
device

49

sixno sound or small sound

no sound or
small sound

check XP302
XP303sound box
connector

check XP302
XP303
outputsignal

Yes

change sound box

check TA2024
input signal

normal

check TA2024
powermute

check MSP3410G
output signal

Yes

check MSP3410G
input signal

TV

other source

check sound
input

Yes

normal

check and change

TA2024

check MSP3410G output

coupling circuitC629
C630FB5FB6C522C543

checkTDQ-6F7outp abnormality check and change

TDQ-6F7
utSIFsignal

check 67 pin
SISF input

Yes

normal

check MSP3410G
powerclock
resetbus

check SIF filter

amplifer
circuit

no input

normal

check signal
sourcesound
jackinput
coupling circuit

check and change

MSP3410G

50

Annex 1

51

Annex 2

52

53