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Outline
Concurrent versus Sequential
Concurrent statements (chapter 5 of Pedroni)
Using operators
When...else
With Select When
GENERATE
BLOCK
If then else
Case when
Loop
Wait until
Combinational logic is that in which the output of the circuit depends solely on the
current inputs (figure 5.1(a)) in principle, the system requires no memory and can be
implemented using conventional logic gates.
Sequential logic is defined as that in which the output does depend on previous inputs
(figure 5.1(b)) storage elements are required, which are connected to the
combinational logic block through a feedback loop, such that now the stored states
3
(created by previous inputs) will also aect the output of the circuit.
Concurrent code
Concurrency
19-Feb-11
Combinational Logic
Concurrent statements :
Execute at the same time in parallel
Sequential statements :
Execute one at a time in sequence
Concurrent Statements
Order independent
X <=A+B ;
Z <=C+X ;
Z <=C+X ;
X <=A+B ;
Concurrent
Selective (with-select-when)
Conditional (when-else)
Generate
The easiest way to perceive this is to actually draw a schematic of the
operations. Schematics are used to represent hardware, and so they are
concurrent in nature.
10
Library altera;
Use altera.maxplus2.all;
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Entity design_name is
port(signal1,signal2,..:mode type;
signal3,signal4,..:mode type);
End entity design_name;
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Using Operators
13
14
Logical operators
Test
Vector
VHDL
Test Bench
VHDL
Design
Output
Vector
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16
x1
x2
Library ieee;
A
B
Entity exampl1 IS
PORT (x1,x2,x3: IN std_logic;
Logical operators
Examples
Use IEEE.std_logic_1164.all;
f
x3
: OUT std_logic;);
END example1;
ARCHITECTURE Lfun of example1 is
Signal A,B : std_logic;
BEGIN
b
c
b
a
17
f<= A OR B;
f<= A OR B;
END Lfun;
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Figure 5.4
Simulation results of example 5.1.
20
with-select-when
Syntax is
entity SELECTED_ASSIGNMENT is
port (A, B, C, X : in integer range 0 to 15;
Z_CONC : out integer range 0 to 15;
end SELECTED_ASSIGNMENT;
22
w0
w3
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3
s
f
END mux4to1 ;
4-to-1 MUL
s0 s1
: IN
: IN
: OUT
STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;
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Example
---- library statements (not shown)
entity my_test is
port( a3,a2,a1,a0: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
y: out std_logic_vector(3 downto 0));
end entity my_test;
architecture behavior of my_test is
begin
with s select
y <= a3 when 11,
a2 when 10,
a1 when 01,
a0 when others; -- default condition
end architecture behavior;
A3
A3
A2
A2
A1
A1
A0
A0
MUX
Mux
S
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26
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when_else
The signal is assigned a value based on
a condition.
signal_name <= value_1 when condition1 else
value_2 when condition2 else
value_3 when condition3 else
value_n;
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Output
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LIBRARY IEEE;
Input
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY example is
PORT(
X,Y
: IN
Std_Logic;
: OUT
Std_Logic
);
Output
END example;
ARCHITECTURE a OF example IS
BEGIN
Z <= '0' When (X='0' and Y='0') Else
'1' When (X='0' and Y='1') Else
'1' When (X='1' and Y='0') Else
'0';
END a;
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Tri-state Buffer
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.all;
3 ---------------------------------------------4 ENTITY tri_state IS
5 PORT ( ena: IN STD_LOGIC;
6
input: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
7
output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
8 END tri_state;
9 ---------------------------------------------10 ARCHITECTURE tri_state OF tri_state IS
11 BEGIN
12
output <= input
WHEN (ena='0') ELSE
13
(OTHERS => 'Z');
14 END tri_state;
43
15 ----------------------------------------------
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45
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GENERATE
GENERATE is another concurrent statement (along
with operators and WHEN). It is equivalent to the
sequential statement LOOP (chapter 6) in the sense
that it allows a section of code to be repeated a
number of times, thus creating several instances of
the same assignments. Its regular form is the FOR /
GENERATE construct, with the syntax shown below.
Notice that GENERATE must be labeled.
Syntax of FOR / GENERATE:
label: FOR identifier IN range GENERATE
(concurrent assignments)
END GENERATE;
55
IF/GENERATE
An irregular form is also available, which uses
IF/GENERATE (with an IF equivalent; recall that
originally IF is a sequential statement). Here ELSE is not
allowed. In the same way that IF/GENERATE can be
nested inside FOR/GENERATE (syntax below), the
opposite can also be done.
IF / GENERATE nested inside FOR / GENERATE:
label1: FOR identifier IN range GENERATE
...
label2: IF condition GENERATE
(concurrent assignments)
END GENERATE;
...
57
END GENERATE;
56
Example:
SIGNAL x: BIT_VECTOR (7 DOWNTO 0);
SIGNAL y: BIT_VECTOR (15 DOWNTO 0);
SIGNAL z: BIT_VECTOR (7 DOWNTO 0);
...
G1: FOR i IN x'RANGE GENERATE
z(i) <= x(i) AND y(i+8);
END GENERATE;
One important remark about GENERATE (and the same is true for
LOOP, which will be seen in chapter 6) is that both limits of the
range must be static. As an example, let us consider the code
below, where choice is an input (non-static) parameter. This kind
of code is generally not synthesizable.
NotOK: FOR i IN 0 TO choice GENERATE
(concurrent statements)
58
END GENERATE;
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BLOCK
There are two kinds of BLOCK statements:
Simple and
Guarded.
BLOCK
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Simple BLOCK
The BLOCK statement, in its simple form,
represents only a way of locally partitioning
the code. It allows a set of concurrent
statements to be clustered into a BLOCK, with
the purpose of turning the overall code more
readable and more manageable (which might
be helpful when dealing with long codes). Its
syntax is shown below.
label: BLOCK
[declarative part]
BEGIN
(concurrent statements)
65
END BLOCK label;
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Nested BLOCK
Example:
b1: BLOCK
SIGNAL a: STD_LOGIC;
BEGIN
a <= input_sig WHEN ena='1' ELSE 'Z';
END BLOCK b1;
67
Guarded BLOCK
A guarded BLOCK is a special kind of BLOCK, which
includes an additional expression, called guard expression.
A guarded statement in a guarded BLOCK is executed only
when the guard expression is TRUE.
Guarded BLOCK:
label: BLOCK (guard expression)
[declarative part]
BEGIN
(concurrent guarded and unguarded statements)
END BLOCK label;
As the examples below illustrate, even though only
concurrent statements can be written within a BLOCK, with
a guarded BLOCK even sequential circuits can be
constructed. This, however, is not a usual design approach.
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Sequential Code
VHDL code is inherently concurrent. PROCESSES,
FUNCTIONS, and PROCEDURES are the only sections
of code that are executed sequentially. However, as a
whole, any of these blocks is still concurrent with any
other statements placed outside it.
One important aspect of sequential code is that it is not
limited to sequential logic. Indeed, with it we can build
sequential circuits as well as combinational circuits.
Sequential code is also called behavioral code.
The statements discussed in this section are all
sequential, that is, allowed only inside PROCESSES,
FUNCTIONS, or PROCEDURES. They are: IF, WAIT,
CASE, and LOOP.
Sequential Code
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Behavioral Statements
Variables
Processes
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Processes
processname : process(sensitivylist)is
declarations
begin
sequentialstatements
end process processname;
-- sensitivylist : list of signals triggering the process on event
-- declarations: types, variables that will be used in the process
-signal definitions are not allowed here! (behavioral code)
-- processname: identifier of the process (optional)
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Processes
library ieee;
use ieee.std_logic_1164.all;
entity foo is
port(x,y : in std_logic;
z
: out std_logic);
end foo;
architecture beh of foo is
signal s : std_logic;
begin
process(x,y) is
begin
s <= x and y;
z <= not s;
end process;
end architecture beh;
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Wait Statements
wait on sensitivitylist;
wait for time;
wait until condition;
82
Wait Statements
Each process must have a sensitivity list or at
least one wait statement
Example: Two identical definitions
architecture beh of ha is
begin
process(a,b)
begin
sum <= a xor b;
carry <= a and b;
end;
end beh;
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architecture beh of ha is
begin
process --no sens.list
begin
sum <= a xor b;
carry <= a and b;
wait on a,b; -- wait state.
end;
end beh;
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Wait Statements
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If Statements
If statements allow
conditional execution of
statements
May contain multiple
elsif branches and one
else branch
The else branch will be
active if no conditions
are satisfied
Absence of ELSE
results in implicit
memory
if statements may be
nested
ifthenend if
if condition1 then
sequentialstatements
elsif condition2 then
sequentialstatements
else
sequentialstatements
end if;
89
condition
if condition then
statements ;
end if ;
yes
no
statements
if ENABLE = 1 then
Q <= D ;
end if ;
ENABLE
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ifthenend if
if condition then
No
statements A ;
else
statements B ;
end if ;
ifthenend if
Statements B
if condition_1 then
statements A ;
elsif condition_2 then
statements B;
:
end if ;
Yes
condition
Statements A
if A = B then
F <= 1 ;
else
F <= 0 ;
end if ;
yes
Condition_1
Condition_1
Statements B
no
CLK
8
Q
RESET
Binary Counter
ifthenend if
if condition_1 then
statements A ;
elsif condition_2 then
statements B ;
else
statements C ;
end if ;
yes
Condition_2
if RESET = 0 then
Q <= X 00 ;
elsif CLKevent and CLK = 1 then
Q <= Q + 1;
end if ;
91
Statements A
no
92
ifthenend if
priority
yes
Statements A
no
yes
Condition_2
if x= 1 then
F <= A ;
elsif y = 1 then
F <= B ;
else
F <= C;
end if ;
Statements B
no
Statements C
if A > B then
F <= 100 ;
elsif A < B then
F <= 010 ;
else
F <= 001 ;
end if ;
EQV
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Case Statements
if-then-else
4-1 mux shown below
mux4_1: process (a, b, c, d, s)
begin
if s = 00 then x <= a ;
elsif s = 01 then x <= b ;
elsif s = 10 then x <= c ;
else x <= d ;
end if;
end process mux4_1 ;
s
2
a
b
c
d
1
2
3
4:1 MUX
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Case is when
CASE signal X IS
when value_1 =>
statements A ;
when value_2 =>
statements B ;
:
when others =>
statements P ;
END CASE;
Value must Exclusive
When others cover all others value
Value may be:
only one constant (when 101 )
up to two constant (when 3 | 7 | 9 )
Interval
(when 5 to 9 )
Value_1
Case is when
yes
Statements A
NO
Value_2
yes
Statements B
case A is
when 00 => y <= 0111 ;
when 01 => y <= 1011 ;
when 10 => y <= 1101 ;
when 11 => y <= 1110 ;
when others => y <= 1111 ;
end case;
NO
Statements A
97
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s
2
a
b
c
d
1
2
3
4:1 MUX
100
3-to-8 Decoder
A: in STD_LOGIC_VECTOR(2 downto 0);
Y: out STD_LOGIC_VECTOR(0 to 7);
Behavior
for i in 0 to 7 loop
if(i = conv_integer(A))
Y(i) <= 1;
A2
else
0
Y(i) <= 0;
0
end if;
0
end loop;
101
0
1
1
1
1
then
A1 A0
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0 0
0 0
0 0
0 0
0 0
0 0
1 0
01021
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
3-to-8 Decoder
entity decode38 is
port(
A : in STD_LOGIC_VECTOR(2 downto 0);
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end decode38;
architecture decode38 of decode38 is
begin
process(A)
variable j: integer;
begin
j := conv_integer(A);
for i in 0 to 7 loop
if(i = j) then
Y(i) <= '1';
else
Y(i) <= '0';
end if;
end loop;
end process;
end decode38;
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105
106
107
108
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110
111
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Implicit memory
Signals in VHDL have a current value and may
be scheduled for a future value
If the future value of a signal cannot be
determined, a latch will be synthesized to
preserve its current value
Advantages:
Simplifies the creation of memory in logic design
Disadvantages:
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Implicit memory:
Example of incomplete specification
ARCHITECTURE archincomplete OF
incomplete IS
BEGIN
im_mem: PROCESS (a,b)
BEGIN
a
c
IF a = '1'
THEN c <= b;
END IF;
END PROCESS im_mem;
END archincomplete;
Implicit memory:
Example of complete specification
ARCHITECTURE archcomplete OF
complete IS
BEGIN
no_mem: PROCESS (a, b)
BEGIN
IF a = '1'
THEN c <= b;
ELSE c <= '0';
END IF;
END PROCESS no_mem;
END archcomplete;
a
b
CASE versus IF
VHDL code based on IF not to dier from that based on CASE
Example: The codes below implement the same physical
multiplexer circuit.
---- With IF: -------------IF (sel="00") THEN x<=a;
ELSIF (sel="01") THEN x<=b;
ELSIF (sel="10") THEN x<=c;
ELSE x<=d;
---- With CASE: -----------CASE sel IS
WHEN "00" => x<=a;
WHEN "01" => x<=b;
WHEN "10" => x<=c;
WHEN OTHERS => x<=d;
118
END CASE;
----------------------------
Table 6.1
Comparison between WHEN and CASE.
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7-Segment Display
7-Segment Display
VHDL
D(3:0)
Truth table
D
0
1
2
3
4
5
6
7
a
1
0
1
1
0
1
1
1
b
1
1
1
1
1
0
0
1
c
1
1
0
1
1
1
1
1
d
1
0
1
1
0
1
1
0
e
1
0
1
0
0
0
1
0
f
1
0
0
0
1
1
1
0
g
0
0
1
1
1
1
1
0
D
8
9
A
b
C
d
E
F
a
1
1
1
0
1
0
1
1
b
1
1
1
0
0
1
0
0
c
1
1
1
1
0
1
0
0
d
1
1
0
1
1
1
1
0
seg7dec
e
1
0
1
1
1
1
1
1
f
1
1
1
1
1
0
1
1
g
1
1
1
1
0
1
1
1
AtoG(6:0)
Behavior
(Active LOW)
a
f
b
g
b
g
c
e
d
d
digit(3:0)
seg7dec
-- seg7dec
with digit select
ssg <= "1001111"
"0010010"
"0000110"
AtoG
"1001100"
"0100100"
"0100000"
"0001111"
"0000000"
"0000100"
"0001000"
"1100000"
"0110001"
"1000010"
"0110000"
sseg(6:0)
"0111000"
"0000001"
when
when
when
when
when
when
when
when
when
when
when
when
when
when
when
when
"0001",
"0010",
"0011",
"0100",
"0101",
"0110",
"0111",
"1000",
"1001",
"1010",
"1011",
"1100",
"1101",
"1110",
"1111",
others;
121
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Pass
AND
OR
NOT
Addition
Subtraction
Increment
Decrement
END CASE;
SegmentsI <= not Segs;-- invert the 0.s and 1.s
END PROCESS;
END Behavioral;
124
122
Select lines
--1
--2
--3
--4
--5
--6
--7
--8
--9
--A
--b
--C
--d
--E
--F
--0
Operation
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY alu IS
PORT (S: IN STD_LOGIC_VECTOR(2 downto 0);
-- Select for operations
A, B: IN STD_LOGIC_VECTOR(3 downto 0);
-- Input operands
F: OUT STD_LOGIC_VECTOR(3 downto 0));
-- Output
END alu;
Pass A to output
A AND B
A OR B
A'
A+ B
A- B
A+ 1
A- 1
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Comparators
Architecture
Body of
Simple ALU
X
Y
A1
A2
A3
B0
B1
B2
B3
if X = Y then
Z <= '1';
else
Z <= '0';
end if;
X
0
0
1
1
Y
0
1
0
1
Z
1
0
0
1
127
128
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
XNOR
A0
A1
A2
A3
C0
C1
C0
B0
C1
B1
B2
C2
B3
C3
A_EQ_B
entity eqdet4 is
Port ( A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
A_EQ_B : out std_logic);
end eqdet4;
A_EQ_B
C2
C3
C <= A xnor B;
A: in STD_LOGIC_VECTOR(3 downto 0);
B: in STD_LOGIC_VECTOR(3 downto 0);
A_EQ_B: out STD_LOGIC;
end Behavioral;
130
Comparators
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
A_EQ_B
A(n-1:0)
A_GT_B
comp
B(n-1:0)
A_LT_B
A_UGT_B
A_ULT_B
A, B
signed
A, B
unsigned
A(n-1:0)
comp
B(n-1:0)
A_EQ_B
A_GT_B
A_LT_B
A_UGT_B
A_ULT_B
entity comp is
generic(width:positive);
port (
A: in STD_LOGIC_VECTOR(width-1 downto 0);
B: in STD_LOGIC_VECTOR(width-1 downto 0);
A_EQ_B: out STD_LOGIC;
A_GT_B: out STD_LOGIC;
A_LT_B: out STD_LOGIC;
A_ULT_B: out STD_LOGIC;
A_UGT_B: out STD_LOGIC
);
end comp;
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comp
A_EQ_B
A_GT_B
A_LT_B
A_UGT_B
A_ULT_B
133
134
Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}
Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}
Not unique
One method for generating a Gray code sequence:
Start with all bits zero and successively flip the
right-most bit that produces a new string.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
136
bin2gray.vhd
entity bin2gray is
generic(width:positive := 3);
port(
B : in STD_LOGIC_VECTOR(width-1 downto 0);
G : out STD_LOGIC_VECTOR(width-1 downto 0)
);
end bin2gray;
architecture bin2gray of bin2gray is
begin
process(B)
begin
G(width-1) <= B(width-1);
for i in width-2 downto 0 loop
G(i) <= B(i+1) xor B(i);
end loop;
end process;
end bin2gray;
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
gray2bin.vhd
entity gray2bin is
generic(width:positive := 3);
port(
G : in STD_LOGIC_VECTOR(width-1 downto 0);
B : out STD_LOGIC_VECTOR(width-1 downto 0)
);
end gray2bin;
architecture gray2bin of gray2bin is
begin
process(G)
variable BV: STD_LOGIC_VECTOR(width-1 downto 0);
begin
BV(width-1) := G(width-1);
for i in width-2 downto 0 loop
BV(i) := BV(i+1) xor G(i);
end loop;
B <= BV;
end process;
end gray2bin;
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